JPS6144372A - Apparatus for testing logical lsi - Google Patents

Abstract

PURPOSE:To enhance the accuracy of a function test while preventing the cross talk between input and output signal pins, by providing a switch in the vicinity of the output pin of logical LSI to be tested and coupling a tester and the above described logical LSI through this switch. CONSTITUTION:MOS switches 4a, 4b... are provided in the vicinity of the terminal provided to the peripheral edge of an IC socket 2 in which logical LSI1 to be tested is inserted. Signal wires 5a, 5b... each comprising a coaxial cable are connected between the terminal 3 and an LSI tester 6 through the MOS switches. The signal wire 5b connected to the input terminal of the comparator 7 in the LSI tester 6 is connected to the output pin of LSI 1 but, because the MOS switch 4b is turned ON after an output signal becomes stable, the abrupt change in the current in an output circuit is suppressed and the generation of cross talk caused by the mutual inductance between the signal wires can be prevented and erroneous operation in a function test is prevented.

Description

[Detailed Description of the Invention] [Technical Field] The present invention relates to a testing technology for logic integrated circuits.
For example, the present invention relates to a technique that is effective when used in a device for testing CMO5-LSI (large-scale integrated circuit consisting of complementary MO3).

[Background technology] Logic L whose basic configuration is a combination of logic gate circuits
In SI, function testing is performed to check whether the LSI has reached the desired quality level.
and operational margin tests are performed. In that case, conventionally, a device called an LSI tester and a logic LSI inserted into an IC socket are connected through a signal line such as a coaxial cable, and a test signal consisting of appropriate binary data is sent from the tester to each input pin of the logic LSI. Put in. By monitoring and evaluating the output at that time, the operating margin of the signal was measured and whether or not there was a failure in the internal logic gate circuit was diagnosed.

However, the signal line connecting the IC socket and the tester is relatively long and often has a low resistance of about 100Ω.
If the output circuit is implanted with a circuit made of bipolar transistors such as an L circuit, the driving ability of the output circuit is relatively high, so there is no problem even if it is connected to the tester via a heavily loaded signal line. On the other hand, CMOS-
The output circuit has low driving ability like LSI, and EC
When testing an LSI whose signal amplitude is larger than that of an L circuit, if the output signal fluctuates significantly, crosstalk may occur between output signal lines or adjacent input signal lines. .

Noise is added to the input signal, causing malfunctions during function tests. Also, during signal transients, a very large current flows through the output circuit, causing the internal power supply voltage to fluctuate, causing a phenomenon similar to crosstalk, and changing the logic threshold voltage of the internal input circuit. As a result, there was a problem in that accurate function tests and operation margin tests could not be performed.

Especially recently, the number of pins of LS'I is increasing.

One LSI may have hundreds of pins.

In such a logic LSI with a large number of pins, if the levels of dozens or hundreds of output pins are changed at once, crosstalk with input pins is likely to occur. Also, the more pins there are, the longer the signal line will be.

This has the disadvantage that the load increases. Furthermore, in recent LSIs, output characteristics have been improved to increase speed, and changes in output signals have become steeper, making crosstalk more likely to occur. (For information on LSI testers, see, for example, the magazine "Electronic Materials J, November 1981 special issue, pages 193 to 198.") [Object of the Invention] The purpose of the invention is to prevent cross-crossing between input and output signal pins in testing logic LSIs. Preventing talk from occurring,
The purpose is to improve the accuracy of faction tests.

Another object of the present invention is to enable accurate operational margin testing in testing logic LSIs.

The above and other objects and novel features of the present invention will become clear from the description of this specification and the accompanying drawings.

[Summary of the Invention] Representative inventions disclosed in this application will be summarized as follows.

That is, a switch is provided near each terminal of the socket into which the logic LSI to be tested is inserted, and the socket and LSI tester are connected via the switch with a signal line.
The switch on the signal connected to the input pin should always be in a conductive state.

The output signal changes by normally leaving the switch on the signal line connected to the output pin in the off state, and turning it on after the change in the output signal has calmed down to transmit the output state to the LSI tester. At the same time, the load on the LSI is reduced to prevent a large current from flowing to the output circuit in the LSI, and the current does not change suddenly to prevent crosstalk and fluctuations in the internal power supply voltage. This achieves the above objective of improving the accuracy of action tests and operational margin tests.

[Embodiment] FIG. 1 shows an embodiment of an LSI test device according to the present invention.

Terminals 3, 3 provided around the periphery of an IC socket 2 into which a logic LSI 1 such as a CMOS gate array is inserted
．． In the vicinity of .
4b,... are provided, and these MOS switches 4a,
4b, . . . are connected to the terminals 3, 3L, . . .
···It is connected to the. Ico line 5a, 5b,...
- The other end is coupled to the LSI tester 6.

In the above case, the output pin of the logic LSII being tested is
A signal line 5b coupled to an input terminal of a comparator 7 in the LSI tester 6 is connected. The output g of the logic LSII inputted to the comparator 7, Vout, is compared with the expected output level Vr, which is predicted in advance, supplied from the control section inside the LSI tester 6, and it is determined whether or not they match. Note that the resistor R connected to the signal line 5b is a load resistor connected to the input terminal of the high impedance comparator 7. One end of the load resistor R is coupled to, but not limited to, a ground point of the circuit. One end of this resistance R is
Of course, it may be coupled to a suitable potential source.

MOS switches 4a, 4 on each of the above signals 5a and Sb
b is a control signal (g,
C2, C3r and C4 are controlled to turn on and off, respectively. Although not particularly limited, the MOS switch 4a connected to the input pin of the logic LSII to be tested is always turned on by the control signal C1 during testing, so that test signals can be continuously input.

On the other hand, as shown in FIG. 2, the MOS switch 4b connected to the output bin of the logic LSII to be tested outputs an output signal V o which is changed after a certain delay in the internal gate circuit after the input signal Vin changes. After ut becomes stable, it is turned on by the control signal C2 which is changed from low level to high level.

In addition, in the case of the input/output common bin, ll17 in the input mode is controlled (in other words, it is always on, but in the case of the output mode, it is controlled every cycle in the same way as the output pin.
It is turned on/off by a control signal. Further, when the expected output value is don't care, the control signals of the output pin and the input/output common bin remain off.

Therefore, at the time the signal at the output pin of the logic LSII is changed, the MOS switch 4b is turned off, so the large capacitance of the signal line 5b is not connected to the output circuit inside the LSI at that time. The output will change even when there is no power.

Therefore, when the output signal V out changes, LS
A large current is prevented from flowing through the output circuit inside I. This suppresses the occurrence of crosstalk between the signal lines 5a and Sb.

Furthermore, when the MOS switch 4b is turned on after the output signal Vout changes, and the signal line 5b and the load resistor are connected to the output pin of the LSI, the level of the signal line 5b is changed to the output signal Vout. A current is passed through the output circuit inside the LSI so as to change the level accordingly.

However, at this time, by appropriately setting the characteristics of the MOS switch 4b, the level change on the signal line 5b can be made more gradual than that of the output circuit due to its on-resistance and parasitic capacitance.

Therefore, even if the signal a5b is connected to the output pin by turning on the MOS switch 4b, a sudden current change is prevented from occurring in the output circuit inside the LSI. Then, after the MOS switch 4b is turned on, a certain period of time (5
After the level of the signal line 5b has been determined (approximately 0 ns), the test strobe signal TS is supplied from the control section in the LSI tester 6 to the comparator 7, and the test strobe signal TS is supplied to the comparator 7.
A comparison with an expected output level Vr predicted in advance is performed at the timing of the strobe signal TS.

Due to the above-mentioned effects, in this embodiment, even if the signal line 5b with a large load is connected to the logic LSII to be tested,
Since sudden current changes in the output circuit are suppressed, losstalk caused by mutual inductance between signal lines is prevented from occurring. As a result, there is no risk of noise being added to the input signal due to crosstalk, and malfunctions in function tests are prevented.

In addition, since sudden changes in current in the output circuit inside the logic LSI are suppressed, fluctuations in the internal power supply voltage are reduced, and a phenomenon similar to crosstalk between input and output bins due to fluctuations in power supply voltage is reduced. In addition to preventing the occurrence of
This prevents the logic threshold voltage of the input circuit from changing due to fluctuations in the ff1gff1 pressure, making it possible to perform accurate operating margin tests.

Note that in a logic LSI such as a gate array, it is not determined which bin is an input bin or an output pin, so in the above embodiment, in order to have versatility, it is connected to the input pin of the logic LSI (= branch line). A MOS switch 4a is also provided on the MOS switch 5a. However, the present invention is not limited to this, and when testing a logic LSI with fixed input/output pins, a signal line 5b connected to the output pin is provided. A MOS switch may be provided only on the top.

[Effect] A switch is provided near each terminal of the socket into which the logic LSI to be tested is inserted, and the socket and LSJ tester are connected via a signal line through this switch, so that the signal connected to the output pin The load when the output signal changes can be reduced by leaving the switch on the line in the off state and turning it on after the change in the output signal has calmed down to transmit the output state to the LSI tester. TeL
By preventing a large current from flowing into the output circuit within the SI and preventing the current from changing rapidly, crosstalk between input and output pins and fluctuations in the internal power supply voltage are prevented. This has the effect of improving the accuracy of faction tests and operational margin tests.

Although the invention made by the present inventor has been specifically explained above based on Examples, it goes without saying that the present invention is not limited to the above Examples and can be modified in various ways without departing from the gist thereof. Nor. For example, in the above embodiment, the switches 4a and 4b provided near the IC socket
Although each of these MOS switches is constructed using discrete MOSFETs, it is also possible to incorporate these MOS switches into ICs.

[Field of Application] In the above explanation, the invention made by the present inventor will be mainly explained in terms of CMOS-LS, which is the field of application that is its background.
Although the description has been made regarding the application to I, it is not limited thereto, and is applicable to TTL logic LSI with large logic amplitude.
In addition, it can be used in logic LSIs where the length of the signal line connecting the socket and the tester must be long due to the large number of bins.

[Brief explanation of drawings]

FIG. 1 is a circuit configuration diagram showing an embodiment of the present invention applied to a logic LSI test device, and FIG. 2 is a timing chart showing the timing of signals of each part in the circuit. l...Logic LSI, 2...IC socket, 3...
...Socket terminal, 4a, 4b...Switch (M
OSFET), 5 a, 5 b-connection signal line, 6...
... LSI tester, 7... Comparator.

Claims (1)

[Claims] 1. A switch is provided near at least the output pin of the logic LSI to be tested, and the logic LSI is
and an LSI tester are connected by a signal line, and the switch is made conductive after the level of the output pin of the logic LSI is stabilized. 2. The logic LSI is inserted into a socket, and a signal line to be coupled to the tester is connected to the logic LSI through a switch provided near the socket. Logic LSI test equipment. 3. The logic LSI testing device according to claim 1 or 2, wherein the switch is composed of a discrete MOSFET.