JPS6135581B2 - - Google Patents
Info
- Publication number
- JPS6135581B2 JPS6135581B2 JP18827880A JP18827880A JPS6135581B2 JP S6135581 B2 JPS6135581 B2 JP S6135581B2 JP 18827880 A JP18827880 A JP 18827880A JP 18827880 A JP18827880 A JP 18827880A JP S6135581 B2 JPS6135581 B2 JP S6135581B2
- Authority
- JP
- Japan
- Prior art keywords
- memory
- access
- data
- data processing
- parallel
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
- 238000001514 detection method Methods 0.000 claims description 2
- 238000009434 installation Methods 0.000 claims 1
- 238000010586 diagram Methods 0.000 description 5
- 101100236857 Prunus serotina MDL4 gene Proteins 0.000 description 2
- 102100040841 C-type lectin domain family 5 member A Human genes 0.000 description 1
- 101150008824 CLEC5A gene Proteins 0.000 description 1
- 101150056111 MDL1 gene Proteins 0.000 description 1
- 101100386697 Magnaporthe oryzae (strain 70-15 / ATCC MYA-4617 / FGSC 8958) DCL1 gene Proteins 0.000 description 1
- 238000000034 method Methods 0.000 description 1
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/14—Handling requests for interconnection or transfer
- G06F13/16—Handling requests for interconnection or transfer for access to memory bus
Landscapes
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Complex Calculations (AREA)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP18827880A JPS57113165A (en) | 1980-12-29 | 1980-12-29 | Data processor |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP18827880A JPS57113165A (en) | 1980-12-29 | 1980-12-29 | Data processor |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS57113165A JPS57113165A (en) | 1982-07-14 |
| JPS6135581B2 true JPS6135581B2 (de) | 1986-08-13 |
Family
ID=16220852
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP18827880A Granted JPS57113165A (en) | 1980-12-29 | 1980-12-29 | Data processor |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS57113165A (de) |
Families Citing this family (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS618785A (ja) * | 1984-06-21 | 1986-01-16 | Fujitsu Ltd | 記憶装置アクセス制御方式 |
| JPS61153745A (ja) * | 1984-12-27 | 1986-07-12 | Fujitsu Ltd | 記憶装置書き込み制御方式 |
| JPS63120374A (ja) * | 1986-11-10 | 1988-05-24 | Hitachi Medical Corp | 画像ワ−クステ−シヨン |
-
1980
- 1980-12-29 JP JP18827880A patent/JPS57113165A/ja active Granted
Also Published As
| Publication number | Publication date |
|---|---|
| JPS57113165A (en) | 1982-07-14 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US4918587A (en) | Prefetch circuit for a computer memory subject to consecutive addressing | |
| EP0280251B1 (de) | Steuerungsanordnung für gemeinschaftlichen Speicher | |
| CA2245106A1 (en) | Method and system for input/output control in a multiprocessor system utilizing simultaneous variable-width bus access | |
| KR980004055A (ko) | 이중 포트 메모리와 이것을 이용한 시스템 및 방법 | |
| JPS62115571A (ja) | ベクトルアクセス制御方式 | |
| US4764896A (en) | Microprocessor assisted memory to memory move apparatus | |
| JPH0128972B2 (de) | ||
| EP0223607B1 (de) | Vektorverarbeitungssystem | |
| JPS6135581B2 (de) | ||
| KR930008639A (ko) | 메모리 콘트롤라 및 데이타 처리 시스템 | |
| JPH0358163A (ja) | 疎結合型マルチプロセッサシステム | |
| JP3005456B2 (ja) | ベクトル処理装置 | |
| JPH0341856B2 (de) | ||
| JPS6349257B2 (de) | ||
| JPS61118847A (ja) | メモリの同時アクセス制御方式 | |
| JP2946561B2 (ja) | マルチプロセッサシステム | |
| JPS6363940B2 (de) | ||
| JPS62128342A (ja) | メモリアクセス制御方式 | |
| JPH02254551A (ja) | オペランド読出方式 | |
| JPS61153745A (ja) | 記憶装置書き込み制御方式 | |
| JPS6356573B2 (de) | ||
| JP2913702B2 (ja) | マルチプロセッサシステムのアクセス受付制御方式 | |
| JP2612715B2 (ja) | アドレスバス制御装置 | |
| JPS61105788A (ja) | マイクロコンピユ−タシステムのアドレス選択回路 | |
| JPH0696032A (ja) | 並列処理システム |