JPS6132475A - Thin film fet - Google Patents

Abstract

PURPOSE:To obtain the titled element which performs high-performance action by a method wherein a required substrate is provided with an amorphous or polycrystalline semiconductor layer, and the current in the state of non-conduction is restricted by a potential barrier, using a metallic film having a higher potential barrier than that of this substrate for source-drain electrodes. CONSTITUTION:The TFT active region is formed by patterning an a-Si 16. Next, a Cr film 17 is deposited by oblique evaporation so that step cuts may generate at the gate edge; then an Al film is evaporated. Heating is carried out in such a manner than the potential barriers of the a-Si 16 and the Cr film become stronger. The pattern is formed, and a source electrode 18 is formed by etching only the Al film with phospho-nitric acid. A source contact electrode 17 self-aligned with a gate insulation film 15 by utilizing step cuts at the gate edge is protected with resist, and the Cr film at unnecessary parts is removed with ammonium ceric nitrate. Finally, the insulation film 13 at the drain electrode 12 lead-out is removed.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Application of the Invention] The present invention relates to a thin film field effect transistor and a method for manufacturing the same, and particularly to a structure suitable for a thin film field effect transistor for driving a liquid crystal.

[Background of the invention]

In recent years, thin film field effect transistors (TPT) using amorphous or polycrystalline semiconductor thin films produced by glow discharge or vacuum deposition have attracted attention. In particular, since the semiconductor thin film can be formed at a low temperature, an inexpensive, large-area insulating substrate can be used as a substrate for forming a thin film semiconductor device.

In addition, microfabrication and integration are possible using conventional lithography technology as is. Figure 1 is JP-A-58-
FIG. 1 is a diagram schematically showing the structure of a conventional TPT shown in No. 148458 and the like. Here, 1 is an insulating substrate, 2 is a gate electrode, 3 is a gate insulating film, and 4 is amorphous silicon (A-5T) or polysilicon (poly-S).
amorphous or polycrystalline semiconductor layers such as i), 5 and 6 are source and drain electrodes, respectively, and 7 and 8 are impurity-doped semiconductor layers for obtaining good ohmic contact.

In TPTs that use amorphous or polycrystalline semiconductors for the semiconductor layer, carrier mobility is extremely low compared to those that use single-crystalline semiconductors due to defects caused by polycrystalline grain boundaries such as grain boundary scattering in the semiconductor. There is a drawback. Therefore, the on-current is small and the operating frequency limit of the TPT is low. Especially a
-8i is approximately 0.1 (cm"/V-
In other words, in order to improve the performance of a TPT using an amorphous or polycrystalline semiconductor, which operates only with a carrier mobility of sec), it is effective to reduce the channel length in order to compensate for the low mobility.

However, in a TPT whose purpose is to have a large area, it is difficult to reduce the source-drain gap to about 10 μm or less by photoetching in terms of accuracy and yield. Shorter TPT channels must be realized without photo-etching, and vertical TPTs are stacked in layers parallel to the substrate.
has been devised. FIG. 2 is a diagram schematically showing the manufacturing of a conventional vertical TPT. Since the channel length of a vertical TPT is determined by the thickness of the semiconductor layer, it is possible to form a submicron-order channel with accuracy and good reproducibility.

These TPTs are MOS F using single crystal silicon.
It shows similar electrical characteristics to ET, but the fundamental difference in the operating principle is that the channel cutoff conditions of the transistor are different from those of MOS.
The FET utilizes the reverse characteristic of the PN junction, whereas the TPT utilizes the high resistance of the semiconductor layer 4. That is, in order to reduce the off-state current of the TPT in the non-conducting state, it is necessary that the resistance of the semiconductor layer 4 is sufficiently high. However, in the vertical TFT shown in FIG. 2, the semiconductor layer is thin and the cross-sectional area through which the current flows is large, so the off-state current increases. Furthermore, when the thickness of the semiconductor layer 4 becomes approximately 2 μm, carriers are injected from the metal electrode 5.6 and the impurity-doped semiconductor layers 7 and 8 for ohmic contact, and the off-state current rapidly increases. Furthermore, the influence of parasitic capacitance between the source and drain is large, resulting in significantly poor high frequency characteristics.

Generally, a vertical structure is used to shorten the channel length of TPT and improve its performance. In this case, in the conventional TPT having a vertical structure, the off-state current rapidly increases as the channel length decreases, and the parasitic capacitance also increases, so that there is no substantial improvement in performance.

Incidentally, related to the manufacturing method of vertical TPT and sheaths, for example, Japanese Patent Application Laid-open Nos. 58-63173 and 58-97
Publication No. 868 and the like can be mentioned.

[Purpose of the invention]

An object of the present invention is to provide a thin film field effect transistor that operates with higher performance than conventional thin film field effect transistors using amorphous or polycrystalline semiconductors, and a method for manufacturing the same.

[Summary of the invention]

The gist of the present invention is as follows. By forming metal films and semiconductor layers in parallel layers on a predetermined substrate and running carriers in a direction perpendicular to the substrate, a T with a short channel length can be achieved.
Form F'T. In this case, by using a material with a high potential barrier at the interface with the semiconductor for the metal film, injection of carriers is suppressed in a non-conducting state, thereby reducing off-state current. In addition, a gate electrode and a gate insulating film are formed in advance, and the source/drain electrodes are formed in a self-aligned manner using the edge of the gate to reduce the parasitic capacitance between the gate/drain and the source. It is something that forms.

[Embodiments of the invention]

Examples of the present invention will be described below with reference to FIGS. 3(a) to 3(d). First, a Cr film 12 is deposited on a glass substrate 11 to a thickness of 2
A SiN film 13 having a thickness of 2,000 wafers is deposited thereon by plasma CVD to serve as an insulating film between the drain and the gate. Next, a Ta film is deposited to a thickness of about 2 μm by sputtering, and then patterned to form a gate electrode 1.
form 4. This gate electrode 14 is anodized in a 0.1% citric acid solution to form a gate insulating film 15 with a thickness of 3000 mm. After protecting the lead-out portion of the drain electrode I2 with a resist, etching is performed using the gate electrode 14 and the gate insulating film 15 as a mask to form a Cr film 12 that will become the drain electrode. Next, after depositing amorphous A-8I16 to a thickness of 8,000 layers by plasma CVD, plasma etching A-8I16 was applied for 30 minutes to create a step cut in A-8I16 at the edge of the gate electrode.
Remove 00 people. Next, a-5t16 is patterned to form the TPT active region (C). Next, a Cr film is deposited to a thickness of 1,000 layers by oblique evaporation so that a step cut occurs at the edge of the gate, and then an AQ film is deposited to a thickness of 5,000 layers. Heating is performed at 200° C. for 30 minutes so that the potential barrier between a-8i 16 and the Cr film becomes strong. Next, a pattern is formed and only the AQ film is etched with phosphoric nitric acid to form the source electrode 18. The source contact electrode 17, which is self-aligned to the gate insulating film 15, is protected by a resist using the step cut at the edge of the gate, and unnecessary portions of C are removed.
Remove the r film with ceric ammonium nitrate. Next, the insulating film 13 at the extraction portion of the drain electrode 12 is removed (
d).

Note that the present invention is not limited to the above embodiments.

For example, a source that forms a potential barrier at the interface with a semiconductor layer.
The drain contact electrode 12° 17 is made of an impurity-doped semiconductor layer with a high potential barrier, Ni, W, Ta, Mo, or T.
It may be a metal or silicide containing i or the like. Also,
The semiconductor layer may be a polycrystalline semiconductor such as poly-Si or a compound semiconductor such as a-8iC instead of a-8i. Furthermore.

The method of forming these semiconductors is the thermal decomposition method instead of the CVD method.
Any method such as vapor deposition or sputtering may be used.

Further, the gate insulating film may be made of any material or formed by any method as long as it can be used as a mask when removing the drain electrode and the insulating film between the drain and the gate.

〔Effect of the invention〕

According to the present invention, the potential barrier at the interface between the source/drain electrode and the semiconductor layer reduces the injection of carriers from the electrode into the semiconductor layer, making it possible to lower the off-state current in a non-conducting state. In addition, since the overlap between the gate/drain electrode and the source electrode can be reduced to zero, the parasitic capacitance between these electrodes can be minimized, which, together with the reduction of the channel length, improves the operating characteristics of the TPT circuit. can be significantly improved. Since the source/drain contact electrodes can be easily self-aligned with the gate electrode and gate insulating film, strict accuracy in mask alignment is no longer necessary, allowing for miniaturization of TPT circuits.

High integration can be achieved easily.

[Brief explanation of the drawing]

Figures 1 and 2 are cross-sectional views of TPT with conventional structure, and Figure 3 (
, ) to (d) are cross-sectional views showing the manufacturing process of TPT according to an embodiment of the present invention. DESCRIPTION OF SYMBOLS 1... Insulating substrate, 2... Gate electrode, 3... Gate insulating film, 4... Amorphous semiconductor layer, 5, 6... Source/drain electrode, 7, 8... Impurity-doped semiconductor layer, 11...Glass substrate, 12...Drain electrode (
Cr layer), 13... SiN film (insulating film), 14...
Gate electrode (Ta film), 15... Gate insulating film (tantalum oxide film), 16... A-8i film, 17... Source contact electrode (CCr film), 18... Source electrode (
AQ). γ 1 Figure Y 3 Figure (^)

Claims (1)

[Claims] 1. A metal film having an amorphous or polycrystalline semiconductor layer on a predetermined substrate and having a high potential barrier to this semiconductor layer is used as the source/drain electrode, and a non-conducting current is passed through the potential barrier. A thin film field effect transistor characterized by being limited by.