JPS61287335A - Parity generation circuit - Google Patents

Abstract

PURPOSE:To realize a parity generation circuit at serial data transfer with a simple circuit by using a binary counter so as to count a one level of a serial data to an input circuit thereby forming a parity bit of the serial data. CONSTITUTION:A binary counter circuit 60 generating a parity bit from a serial transmission/reception data and a parity level selection circuit 80 selecting the level of the parity bit generated by the circuit 60 in an even number parity or an odd number parity are provided. Since the output of a data latch circuit 68 is inverted at each input of '1' level as a serial data STD, the output of the circuit 60 is an even number parity corresponding to the serial data STD. The output from the circuit 60 is outputted at the original level via a transfer gas 83 at the selection of the even number parity by the parity level selection circuit 80 and outputted via a transfer gate 82 after being inverted by an invert er 81 at the selection of odd number parity and outputted via a transfer gate 85 in the timing of a control signal T.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to a serial transfer circuit that serially transfers data, and more particularly to a parity generation circuit that generates parity bits from this transfer data.

[Technical Background of the Invention] In order to detect and correct the erroneous data when an error occurs in the data during data transfer during the transfer route,
It is common practice to add a parity bit to data and transfer it.

Figure 4 shows the conventional parity used for such applications.
The configuration of the generation circuit is shown. This parity generation circuit is for the case where the transfer data is 8 bits, and the 8 bits of data Do to D7 are converted into 4 exclusive OR circuits (exclusive OR circuits) of 2 bits each. 11
The outputs of two exclusive OR circuits 11 and 12 are supplied to exclusive OR circuit 15, and the outputs of the remaining two exclusive OR circuits 13 and 14 are supplied to exclusive OR circuits 11 and 14. are supplied to the circuit 16 respectively, and further the above 2
The outputs of the exclusive OR circuits 15 and 16 are supplied to the exclusive OR circuit 17, and the outputs of the exclusive OR circuit 17 are for odd parity (○DD) and even parity (E
VEN) is supplied to the exclusive OR circuit 18 together with a control signal 0/E for selecting the signal 0/E.

Then, the output of this exclusive OR circuit 18 is a parity signal.
It is outputted as odd parity or even parity PAR through a transfer gate 19 whose switch is controlled by the generation timing signal T.

FIG. 5 is a circuit diagram showing a configuration in which the conventional parity generation circuit described above is used in a serial data transmission circuit for transmitting serial data.

This serial data transmission circuit is connected in multiple stages with transmission buffers 20 whose number corresponds to the number of bits of the transmission data, and for example, 8-bit transmission data TDO to TD7 outputted from the CPU etc. via an internal bus are sent to each transmission buffer. It is supplied in parallel to the inverter 21 in the buffer 20. The output of this inverter 21 is sent via a transfer gate 22 which is switch-controlled by a control signal IB synchronized with the output clock signal CLK, in order to take in each transmission data from the internal bus of the CPU or the like to each transmission buffer 20. It is supplied to each inverter 23. The outputs of these inverters 23 are supplied in parallel as the data Do to D7 to the parity -/' generation circuit 30 configured as shown in FIG. ing. The output of each of these inverters 24 is fed back to the input side of each of the inverters 23 via a transfer gate 25 whose switch is controlled by an inverted clock signal n.

That is, within each transmission buffer 20, an inverter 23.
24 and the transfer gate 25 constitute a data latch circuit in the form of a positive feedback circuit. A transfer gate 27 whose switch is controlled by a shift pulse signal SP synchronized with the clock signal CLK and a transfer gate 28 whose switch is controlled by the inverted OFF signal CLK are connected in series to the circuit point 26 which is the data latch point. One end of the transfer gate 28 in the transmission buffer 20 for lower bits is connected to the circuit point 26 in the transmission buffer 20 for upper bits, and the transmission buffer 20 is supplied with the most significant bit, that is, data TD7.
Odd or even parity bits outputted from the parity generating circuit 30 are supplied to one end of the transfer gate 28 in the parity generating circuit 30.

In this serial data transmission circuit, the clock signal CLK
When the transfer gate 22 is opened by the synchronization control signal IB, eight pits of transmission data TDO to TD7 are taken into the circuit point 26 in each transmission buffer 20. This data is then supplied in parallel to the parity generation circuit 30 via each inverter 23 as the data Do to D7.

The parity generation circuit 30 generates these data DO to D.
7 to generate parity and output it to the transmission buffer 20 of the most significant bit. On the other hand, in each transmission buffer 20, the transfer gate 25 is opened by the inverted clock signal CLK, and each 1-bit input data is latched by the data latch circuit described above. Thereafter, the latch data in each transmission buffer 20 is transferred to the lower bit transmission buffer 20 via the transfer gate 28, 27 in each transmission buffer 20 by the shift pulse signal SP and inverted clock signal CLK, and The data is sequentially output one bit at a time from the transmission buffer 20 as serial transmission data STD. At this time, the parity generated by the parity generation circuit 30 is added to the end of this data STD.
bits will be added.

FIG. 6 is a circuit diagram showing a configuration in which the conventional parity generating circuit described above is used in a serial data receiving circuit for receiving serial data. This serial data receiving circuit has multiple receiving buffers 40 connected in a number corresponding to the number of bits of received data. Each of these reception buffers 40 is configured similarly. That is, this reception buffer 40 includes the transmission buffer 20 of FIG.
Similarly, the transformer 77 gate 43 is switch-controlled by the inverters 41 and 42 and the inverted clock signal CLK.
A data latch circuit in the form of a positive feedback circuit with circuit point 44 as a data latch point is provided. A transfer gate 45 whose switch is controlled by the shift pulse signal SP and a transfer gate 46 whose switch is controlled by the inverted clock signal CLK are connected in series to the circuit point 44.

The outputs of the inverters 41 are supplied in parallel to the parity generation circuit 30 configured as shown in the fourth section as the data Do to D7, and the outputs of the inverters 41 are fed to one input terminal of an AND gate 47. is also supplied. A control signal Bl synchronized with a clock signal CLK for outputting received data from each receiving buffer 40 is supplied to the other input terminal of each AND gate 47, and the received 8-bit data XDO to XD7 is input to each of these AND gates. 47.

Further, one end of the transfer gate 46 in the lower bit receiving buffer 40 is connected to the upper bit receiving buffer 40.
The serial data STD input to the serial data receiving circuit of FIG. 5 is supplied to one end of the transformer 77 gate 46 in the receiving buffer 40 of the most significant bit.

Furthermore, the reception parity PAR added to the end of this serial data STD is sent to the parity comparison circuit 50 along with the parity generated by the parity generation circuit 30.
Here, a match or mismatch between the two parities is detected and a parity check is performed.

In this serial data receiving circuit, the inverted clock signal C
The transfer 1 gate 46.45 is opened by LK and the shift pulse signal SP, and the serial data STD is sequentially fetched into the circuit point 44 in the reception buffer 40, and is supplied in parallel to the parity generation circuit 30 via each inverter 41. be done. Thereafter, transfer gates 43 are opened and one bit of data is latched in each receive buffer 40. Meanwhile, the parity generation circuit 30 generates parity bits from these latch data and outputs them to the comparison circuit 50. On the other hand, when the received parity PAR added to the end of the serial data STD is supplied to the comparison circuit 50, the comparison circuit 50 compares both parities and performs a parity error check.

As a result of this error check, if there is an error in the received data XDo to XD7, the error is corrected by a circuit not shown.

[Problems with the Background Art] Incidentally, in the conventional serial data transmitting/receiving circuit as described above, transmitting/receiving data is taken in parallel to the parity generating circuit 30 for parity bit generation. As shown in the figure, this inevitably results in a large circuit configuration. In addition, the parity bit used in the serial data transfer circuit is immediately taken into the transmission buffer 20 at the time of transmission and into the comparison circuit 50 at the time of reception, so that the parity generation circuit 30 is not used. The frequency is extremely low and it is wasteful in terms of circuitry.

[Purpose of the Invention] This invention was made in consideration of the above circumstances, and its purpose is to improve parity during serial data transfer, which conventionally requires a large circuit configuration to reduce the frequency of use.
The goal is to realize a generation circuit with an extremely simple circuit.

[Summary of the Invention] In order to achieve the above object, in this invention, serial data is supplied, and a parity bit of the serial data is formed by counting the number of inputs of one level of this data with a binary counter. That's what I do.

[Embodiments of the invention] Hereinafter, one embodiment of the present invention will be described with reference to the drawings.

FIG. 1 is a circuit diagram showing the configuration of a parity generation circuit according to the present invention. This parity generation circuit includes a binary counter circuit 60 that generates parity bits from serial transmitted and received data, and a binary counter circuit 60 that generates parity bits from serial transmitted and received data.
Parity generated by selecting the bit level according to even parity or odd parity
It is composed of a level selection circuit 80.

The binary counter circuit 60 is a data latch in the form of a positive feedback circuit consisting of two series-connected inverters 61 and 62 and a transfer gate 63 inserted between the output terminal of the inverter 62 and the input terminal of the inverter 61. A data latch circuit 6 consisting of a circuit 64, two inverters 65 and 66I5, and a transfer gate 67.
8. Transfer gate 6 inserted between the one data latch circuit 64 and the other data latch circuit 68
9. Transfer gate 70 inserted between the output terminal of the first-stage inverter 65 of the other data latch circuit 68 and the input terminal of the first-stage inverter 61 of one data latch circuit 64; the other data latch circuit 68; The input terminal of the first stage inverter 61 and the ground potential Vss application point (
a transformer 77 inserted between the logic "0" level point), a gate 71, an AND gate 72 to which serial data STo for transmission or reception and a sampling signal SMP for sampling this data are input; It is composed of an inverter 73 that inverts the output of the gate 72.

The transfer gates 63 and 69 are switch-controlled by the output of the AND gate 72, and the transfer gates 67 and 70 are controlled by the output of the inverter 73. Furthermore, the transfer gate 71 is configured to transmit and receive data. The switch is controlled by a reset control signal R8 outputted from a control circuit (not shown) at each start time.

The parity level selection circuit 80 includes an inverter 81 to which the output of the data latch circuit 68 in the binary counter circuit 60 is supplied, a transfer gate 82 to which the output of the inverter 81 is supplied, and a transfer gate 82 to which the output of the data latch circuit 68 in the binary counter circuit 60 is supplied. From a transfer gate a3 whose output is supplied to one end and whose other end is commonly connected to the other end of the transfer gate 82, and from a transfer gate 85 whose one end is connected to the other end common connection point 84 of both transfer gates 82 and 83. The transfer gate 83 is supplied with a control signal O/E for selecting odd parity - 1 even parity.
2 is supplied with this signal 0/E via an inverter 86. Further, the transfer gate 85 is switch-controlled by the parity generation timing signal T.

In the parity generation circuit having such a configuration, the binary counter circuit 60 outputs "1" as the serial data STD.
'' level is input, its output, that is, the output of the data latch circuit 68, is inverted. In other words, immediately after the power is turned on, the transfer gate 71 is inverted by the reset signal R8.
is opened, the input of the inverter 65 in the data latch circuit 68 is set to the "OI+" level, the output is set to the "1" level, and the output of the inverter 66 is set to the "0" level. At this time, the serial data STD is at the "OI+" level, and the transfer gates 67 and 70 are opened by the output of the inverter 73, which is at the "1°" level. Therefore,
In the initial state, the input of the inverter 61 in the data latch circuit 64 is set to the "1" level via the transfer gate 70, the output of this inverter 61 is set to the 110 II level, and the output of the inverter 62 is set to the 1" level. be done.

Next, first of all, "1" as serial data STD.
Assume that a level is input. This allows and gate 7
A "1" level signal is output from the transfer gate 63 instead of the transfer gates 67 and 70.
and 69 will be opened. When the transfer gate 63 is opened, the data latch circuit 64 operates to latch the "1" level output of the inverter 62, and at the same time, this latch output is output to the data latch circuit 68 via the transfer gate 69. Therefore, at this time, the output of the data latch circuit 68 is set to the "1" level.

After this, the output of the AND gate 72 is set to the ``O'' level, and the transfer gates 67 and 70 are opened in the same way as described above, so the data latch circuit 68 operates and the ``1'' level output of the inverter 66 is latched. At the same time, this latch output is outputted to the data latch circuit 64 via the transfer gate 70.This state continues until the next "1" level is input as the serial data STD. And then as serial data STD ゛′
When the 1° level is input, the transformer 77 gate 63
and 69 are opened, and the data latch circuit 64 operates to latch the "°0" level output of the inverter 62, and at the same time, this latch output is output to the data latch circuit 68 via the transfer gate 69. Therefore, at this time, the output of the data latch circuit 68 is inverted to the "0" level. Similarly, the output of the data latch circuit 68 is inverted every time the II 1 I+ level is inputted as the serial data STD.

As a result, the output of the binary counter circuit 60 becomes even parity corresponding to the serial data STD. The output from the binary counter circuit 60 is outputted at the same level through the transformer 77 gate 83 in the parity level selection circuit 80 when an even parity is selected in which the control signal 0/E is set to the "1" level. When odd parity is selected with control signal 0/E set to "O" level, it is inverted by inverter 81 and then output via transfer gate 82, and further output via transformer 77 gate 85 at the timing of control signal T. be done.

As described above, the above embodiment circuit is composed of seven inverters and eight transformer 77 gates, and if a CMOS inverter is used for each inverter and an N-channel MOS transistor is used as a transfer gate, a total of 22 It can be configured with a MOS transistor.

When the conventional circuit shown in FIG. 4 is realized with a 0MO8 configuration, one exclusive OR circuit is composed of 16 MoS transistors, and a total of 129 MoS transistors are required. The number of elements can be significantly reduced compared to conventional methods.

FIGS. 2 and 3 each show an example of application of the present invention. FIG. 2 is a circuit diagram showing a configuration when the parity generation circuit of the above embodiment is used in a serial data transmission circuit for transmitting serial data. This serial data transmission circuit is connected in multiple stages with transmission buffers 90 whose number corresponds to the number of bits of the transmission data. The output of this inverter 91 is supplied in parallel to the inverter 91 in each transmission buffer 90.The output of this inverter 91 is controlled in synchronization with the clock signal CLK to take in each transmission data from the internal bus of the CPU etc. to each transmission buffer 90. It is supplied to each inverter 93 via a transfer gate 92 whose switch is controlled by signal IB.The output of each of these inverters 93 is
4 can be supplied. The output of each of these inverters 94 is fed back to the input side of each of the inverters 93 through a transfer gate 95 whose switch is controlled by an inverted clock signal CLK. That is, each transmission buffer 9
0, inverters 93 and 94 and transfer gate 95 constitute a data latch circuit in the form of a positive feedback circuit. The circuit point 96, which is the data latch point of this data latch circuit, is connected to the inverted clock signal CLK.
A transfer gate 97 whose switch is controlled by the shift pulse signal SP and a transfer gate 98 whose switch is controlled by the shift pulse signal SP are connected in series. The transfer gates 97 and 98 are omitted in the transmission buffer 90 to which the least significant bit, that is, the data TDO is supplied, and the serial transmission data STD is output from the circuit point 96. One end of the transformer 77 gate 99, which is opened at the parity output timing, is connected to the input end. Further, the serial transmission data STD outputted from the transmission buffer 90 of the least significant bit is sequentially supplied to the parity generation circuit 100 configured as shown in FIG. is supplied to the other end of the transfer gate 99.

In this serial data transmission circuit, when the transfer gate 92 is opened by the control signal ■B, 8-bit transmission data TDO to TD'7 are transferred to each transmission buffer 90.
The signal is taken into circuit point 96 within. Thereafter, the transfer gate 95 is opened by the inverted clock signal CLK, each 1-bit input data is launched by the data latch circuit, and then the latched data in each transmission buffer 90 is transferred to the shift pulse signal SP and the inverted clock signal CLK.
Accordingly, the transfer gate 9 in each transmission buffer 90
7.98 through the lower bit transmission buffer 90
and is output from the least significant bit transmission buffer 90 as serial transmission data STD. At this time, this data STD is also supplied to the parity generation circuit 100, where a parity bit is generated.

The generated parity bits are transferred to the transfer gate 99.
is supplied to the least significant bit transmission buffer 90 via
Here, it is added to the end of the serial transmission data STD.

FIG. 3 is a circuit diagram showing a configuration when the parity generating circuit of the above embodiment is used in a serial data receiving circuit for receiving serial data.

In this serial data receiving circuit, receiving buffers 40 similar to the conventional one shown in FIG. 5 are connected in multiple stages in a number corresponding to the number of bits of the received data.

In this case, the most significant bit receive buffer 40
The output of the inverter 41 is sequentially supplied to a parity generation circuit 100 configured as shown in FIG.

In this serial data receiving circuit, the inverted clock signal C
Transfer gates 46 and 45 are opened by LK and shift pulse signal SP, and serial data STD is sequentially fetched into circuit point 44 in reception buffer 40 and simultaneously supplied to parity generation circuit 100. after that,
While the transfer gate 43 is opened and one bit of data is latched in each receive buffer 40, the parity generation circuit 100 generates a parity bit from the supplied data and outputs it to the comparison circuit 50. On the other hand, when the received parity PAR added to the end of the serial data STD is supplied to the comparison circuit 50, the comparison circuit 50 compares both parities and performs a parity error check. As a result of this error check, the received data
If there is an error in XD7, it is corrected by a circuit not shown.

In this way, in the serial data transmitting/receiving circuit of the above application example, when serial data is sequentially transferred to each transmitting buffer 90 or receiving buffer 40, the parity generating circuit 1
Since the parity is generated using 00, the parity generation circuit 1 is
00 can be used more frequently.

It goes without saying that the present invention is not limited to the above-mentioned embodiments, and that various modifications can be made. For example, in the above embodiment, the binary counter circuit 60 basically uses two data latch circuits 64 and 68, but this can be any type of binary counter circuit. can also be used.

[Effects of the Invention] As described above, according to the present invention, it is possible to provide a parity generation circuit for serial data transfer that is frequently used and can be realized with an extremely simple circuit.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram showing the configuration of an embodiment of the parity generation circuit according to the present invention, FIGS. 2 and 3 are circuit diagrams showing the configuration of an applied example of the present invention, and FIG. The circuit diagrams of the parity generation circuit, FIGS. 5 and 6, are circuit diagrams of application example circuits using the above-mentioned conventional parity generation circuit, respectively. 40... Reception buffer, 60... Binary counter circuit, 80... Parity-level selection circuit, 90...
- Transmission buffer, 100... Parity generation circuit. Applicant's agent Patent attorney Takehiko Suzue Figure 3

Claims (1)

[Claims] 1. A parity generation circuit characterized in that serial data is supplied and a binary counter that counts the number of inputs of one level of the serial data forms parity of the serial data.