JPS6124120A - Reset circuit of latching relay - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

TECHNICAL FIELD The present invention relates to a reset circuit that brings a latching relay into at least one stable state when a DC power supply is cut off due to a power outage or the like.

BACKGROUND TECHNOLOGY Conventionally, in latching relays that include integrated circuits, an auto-set circuit that sets a relay switch or an auto-reset circuit that resets a relay switch when power is restored after a power outage occurs as a countermeasure against a power outage is built into the integrated circuit. However, it does not have a function to instantly reset the relay switch in the event of a power outage. Therefore, during a power outage, the switching state of the relay switch of the latching relay remains as it was before the power outage, and cannot be reset.

OBJECT An object of the present invention is to solve the above-mentioned technical problems and to provide a latching relay reset circuit that sets the latching relay to at least one stable state when a power outage occurs.

Embodiment FIG. 1 is an electrical circuit diagram of an embodiment of the present invention. The positive terminal of the DC power supply E is connected to the diode D1 via the switch SW.
is connected to the anode of transistor Q1, and is also connected to the base of transistor Q1 through a resistor all'i. The negative pole of the DC power supply E is connected to the base of the transistor Q1 via a resistor R2, and is connected to the collector of the transistor Q1 and the ground terminal GND of the latching relay RY. Diode D1
The cathode of is connected to the launching relay R via the resistor R3-f.
It is connected to a reset terminal R that receives a reset signal for setting one of Y to a stable state, and is also connected to the emitter of the transistor Q1 via a resistor R3. In addition, the cathode of diode D1 is connected to the power supply terminal V of latching relay RY.
Connected to cc.

Power terminal Vcc and ground terminal GN of latching relay BY
A capacitor C1 is connected between the capacitor D and the capacitor C1. In the circuit configured as described above, the switch SW is used to explain the power outage state, and when the switching state is on, @normal power energization is performed, and when the switching state is off, it indicates that normal power is applied. Indicates that a power outage is occurring.

First, make a new one for each input terminal of the latching relay RY. The set terminal S is given a set signal that sets the relay switch of the latching relay RY to the other stable state; in this case, when the set terminal sl is brought to ground,
The relay switch is set and then remains set even if the set signal is turned off. A reset signal for resetting all relay switches is given to the reset terminal R.
In this case, when the reset terminal R is completely grounded, the relay switch will be reset, and will remain reset even if the reset signal is subsequently turned off. The relay switch performs set and reset operations both when the monostable terminal Mi is grounded and when the signal applied to the monostable terminal M becomes high level even after being separated from the ground. The autoset/reset terminal is connected to ground, and when the power is turned on to the latching relay RY, the relay switch is instantly set. This is called an autoset function. Further, the autoset/reset terminal is left open, and when the latching relay RY is powered on, the relay switch is reset at that moment. This is called the auto-reset function. In this way, when each of the above-mentioned signals is applied to each input terminal of latching relay RY, the relay switch performs switching operation according to the signal. Let's do it.

Hereinafter, the operation of the circuit shown in FIG. 1 will be explained.
When W is on, that is, when a power outage has not occurred, the base of the PNP transistor Q1 is biased by the resistors R1 and R2, and its emitter is biased by the resistor R3. transistor Q
The resistance values of resistors R1, R2, and R3 are respectively set so that one of the resistors R1, R2, and R3 is turned off. Therefore, by lowering the set terminal S1 of the latching relay RY, the monostable terminal M, and of course the 1 set terminal R, all of them are grounded, resulting in a low level signal. If given, the above-mentioned launching and relay operations can be performed.Next, the entire operation in a state where the switch SW is turned off, that is, a power outage has occurred, will be explained. When the switch SW is turned off, the current from the DC power source E is cut off, thereby discharging the electric charge of the capacitor C1. The discharge current from this capacitor C1 is passed through the resistor R by the diode D1.
1 does not flow to the transistor Q through the resistor R3t.
1 emitter. This causes the base of transistor Q1 to flow to line 11 through resistor R3, transistor Ql, and resistor R2i, and
turns on. As a result, the emitter potential of transistor Q1 becomes low level and a low level reset signal is applied to the reset terminal R of latching relay RY.The relay switch of latching relay RY is reset and even after the reset signal is cut off. Retain all reset states. As described above, at the moment when a power outage occurs, the discharge current of the capacitor C1 turns on the transistor Qle and resets the relay switch of the latching relay RY.

Note that the integrated circuit of latching relay RY includes a current source circuit as shown in Figure 2, and when the input terminal is open, resistance R? The flowing current 11 flows through the transistor TK@ through the diodes d4 and d5t, and the transistor T is turned on.

Further, when the input terminal A is grounded, the current 12 flowing through the resistor R flows to the ground via the diode d3, and the transistor is turned off. Therefore, when input terminal A is open, output B from the collector of transistor T is low level, and when input terminal A is grounded, output B from the collector of transistor T is high level, and such output B is latched. This becomes the input signal for relay BY.

FIG. 3 is an electrical circuit diagram of another embodiment of the present invention. In FIG. 3, components corresponding to those shown in FIG. 1 are given the same reference numerals. This circuit sets the latching relay RYE during a power outage.

In FIG. 3, the positive electrode of DC power supply E is connected to the anode of diode D1 via switch SW, and to the pace of transistor Q1 via resistor R1.

The negative pole of the DC power supply E is connected to the transistor Q via the resistor R2i.
1, the collector of transistor IQI, and the ground terminal GND of latching relay RY. The cathode of the diode D1 is connected to the set terminal S of the launching relay RY via a resistor R31, and is also connected to the emitter of the transistor Q1 via a resistor R3. A capacitor CI is connected between the power terminal Vcc of the launching relay RY and the ground terminal GND.In the circuit configured as described above, the switch SW is When the switching state is on, it indicates that normal power energization is occurring, and when the switching state is off, it indicates that a power outage has occurred.

First, each input terminal of launching relay RY will be explained. A set signal for setting the relay switch is applied to the set terminal S. In this case, when the set terminal S is grounded, the relay switch is set and remains set even after the set signal 9 is turned off. The reset terminal R is provided with a reset terminal that resets the relay switch, and in this case, when the reset terminal RfW is set to ground,
The relay switch is reset and then remains reset even if the reset signal is turned off. When the monostable terminal M2 is dropped to the ground, and when the signal applied to the monostable terminal M2 becomes high level even after the monostable terminal M2 is removed from the ground, the relay switch performs set and reset operations in both cases. Connect all autoset/reset terminals to ground, and connect the launching relay RY Ki.
When te is turned on, the relay switch is set at that moment. This is called the full auto-set function. Further, the auto-sent/reset terminal is left fully open, and when the latching relay I7Y is plugged in, the relay switch is reset at that moment. This is called the gold auto-reset function. When the aforementioned signals are applied to each input terminal of the launching relay RY in this manner, the relay switch performs a switching operation in response to the signals.

The operation of the circuit shown in FIG. 3 will be explained below. switch S
When W is on, that is, when no power outage has occurred, the pace of PNP transistor Q1 is biased by resistor R1 and resistor R2, and its emitter is biased by resistor R3, so that transistor Q1
The resistance values of the resistors R1, R2, and R3 are set so that the resistors R1, R2, and R3 are turned off. Therefore, by grounding the set terminal S, mono-staple terminal M, and reset terminal R of the latching relay RY to provide a signal at the ground level, the above-described latching relay can be operated.

Next, the entire operation in a state in which the switch SW is turned off, that is, in a state in which a power outage has occurred, will be explained. When the switch SW is turned off, the current from the DC power supply E is cut off, thereby discharging the charge in the capacitor C1. The discharge current from this capacitor C1 is passed through the resistor R1 by the diode D1.
It does not flow toward the transistor Q1, but flows through the resistor 831 to the emitter of the transistor Q1. This causes the pace current of transistor Q1 to flow through resistor R3, transistor Ql, and resistor R2.
through line 11, turning on transistor Ql. As a result, the emitter potential of transistor Q1- becomes low level, and the cent terminal S of latching relay RY
When a low-level set signal is applied to , the relay switch of latching relay RY is set, and the full set state is maintained even after the center signal is cut off. At the moment when a power outage occurs, the discharge current of the capacitor C1 turns on the transistor JQl and sets the relay switch of the latching relay RY.

As described above, according to the present invention, a latching relay can be used at the first power outage? By setting at least one of the stable states, the switching state of the latching relay can be automatically set to the initial state before all power is turned on, and the operation of circuits etc. driven by the output of the latching relay can be automatically set. Improved reliability. Furthermore, power consumption can be reduced by using a latching relay.

[Brief explanation of drawings]

Fig. 1 is an electrical circuit diagram of one embodiment of the present invention, Fig. 2 is an electrical circuit diagram of a current source circuit included in the integrated circuit of latching relay RY, and Fig. 3 is an electrical circuit diagram of another embodiment of the present invention. It is a circuit diagram. C1...Capacitor, Dl...Diode, E...
・DC power supply, R1-R3...resistance, SW...switch, RY...latching relay, Ql...transistor Agent Patent attorney Kei Nishi Partial procedural amendment November 22, 1980

Claims (1)

[Claims] a diode connected in the forward direction to the DC power supply, a capacitor that stores the charge of the DC power supply via the diode, a latching relay to which operating power supply terminals are connected to both ends of the capacitor, and a latching relay connected to the DC power supply in the forward direction; A latching relay reset circuit comprising: a switching element that performs a switching operation based on a discharge current from the capacitor and generates a signal for setting the latching relay to at least one stable state.