JPS61230351A - Hybrid integrated circuit - Google Patents
Hybrid integrated circuitInfo
- Publication number
- JPS61230351A JPS61230351A JP60070840A JP7084085A JPS61230351A JP S61230351 A JPS61230351 A JP S61230351A JP 60070840 A JP60070840 A JP 60070840A JP 7084085 A JP7084085 A JP 7084085A JP S61230351 A JPS61230351 A JP S61230351A
- Authority
- JP
- Japan
- Prior art keywords
- film
- hybrid integrated
- insulating substrate
- circuit
- film resistor
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/16—Printed circuits incorporating printed electric components, e.g. printed resistor, capacitor, inductor
Landscapes
- Apparatuses And Processes For Manufacturing Resistors (AREA)
Abstract
Description
【発明の詳細な説明】
〔発明の利用分野〕
本発明は、機能トリミング用の膜抵抗体を備えそ混成集
積回路に関する。DETAILED DESCRIPTION OF THE INVENTION [Field of Application of the Invention] The present invention relates to a hybrid integrated circuit comprising a film resistor for functional trimming.
従来より、電子装置の回路を調整するトリミング方法と
して、例えば特開昭58−68905号公報に記載され
るように、回路を動作させながら膜抵抗体をレーザ光線
等によってトリミングする機能トリミング方法が知られ
ている。Conventionally, as a trimming method for adjusting the circuit of an electronic device, a functional trimming method has been known in which a film resistor is trimmed using a laser beam or the like while the circuit is operating, as described in Japanese Patent Laid-Open No. 58-68905, for example. It is being
第4図及び第5図は、従来の混成集積回路を例示する斜
視図であって、1は絶縁基板、2は電子回路ブロック、
3は機能トリミング用の膜抵抗体、4は半固定抵抗、5
はリードである。4 and 5 are perspective views illustrating conventional hybrid integrated circuits, in which 1 is an insulating substrate, 2 is an electronic circuit block,
3 is a membrane resistor for functional trimming, 4 is a semi-fixed resistor, 5 is a semi-fixed resistor.
is the lead.
これらの図において、絶縁基板1の一面には増幅器や発
掘器等の電子回路ブロック2が搭載され、他面には 膜
抵抗体3と半固定抵抗4とが搭載されており、これらは
図示しない導体パターンにより結線されている。かかる
混成集積回路は、絶縁基板1の両側端に設けられた複数
本のリード5を介して図示しないプリント基板に半田接
続され・るが、このときの実装上の問題から、リード5
が第4図に示すように電子回路ブロック2を設けた面側
に延びるものと、第5図に示すように膜抵抗体3を設け
た面側に延びるものとがある。In these figures, an electronic circuit block 2 such as an amplifier and an excavator is mounted on one side of an insulating substrate 1, and a membrane resistor 3 and a semi-fixed resistor 4 are mounted on the other side, which are not shown. Connected by a conductor pattern. Such a hybrid integrated circuit is soldered to a printed circuit board (not shown) via a plurality of leads 5 provided at both ends of an insulating substrate 1, but due to mounting problems at this time, the leads 5
As shown in FIG. 4, there is one that extends toward the surface on which the electronic circuit block 2 is provided, and one that extends toward the surface on which the film resistor 3 is provided, as shown in FIG.
このようにして、リード5の方向が互いに反対の2捌類
の混成集積回路を親基板であるプリント基板に半田接続
した後1当該混成集秋回路を含むプリント基板に組込ま
れた回路を動作させ、その回路全体の特性を測定しつつ
機能トリミング装置(図示せず)を用いて上記膜抵抗体
3をトリミングすることにより、プリント基板もしくは
当該プリント基板が組込まれる電子装置の特性を調整す
る。In this way, after soldering the two types of hybrid integrated circuits with the leads 5 in opposite directions to the printed circuit board that is the parent board, 1. the circuit incorporated in the printed circuit board including the hybrid integrated circuit is operated. By trimming the film resistor 3 using a functional trimming device (not shown) while measuring the characteristics of the entire circuit, the characteristics of the printed circuit board or the electronic device in which the printed circuit board is incorporated are adjusted.
しかしながら、上記従来例にあっては、り一ド5の延出
方向に対する膜抵抗体3の形成面が互いに逆となる2a
[類の混成集積回路をプリント 基板に半田接続するた
め、それぞれの膜抵抗体3をトリミングするための2種
類の機能トリミング装置が必要となり、あるいはこれを
1つのもので行う場合は極めて複雑な構造の機能トリミ
ング装置が必要となり、その結果、混成集積回路を含む
回路全体の製造コストが高くなるという欠点があった。However, in the above-mentioned conventional example, the formation surfaces of the membrane resistors 3 with respect to the extending direction of the electrodes 5 are opposite to each other.
[In order to solder-connect a hybrid integrated circuit to a printed circuit board, two types of functional trimming devices are required to trim each film resistor 3, or if this is done with one device, an extremely complicated structure is required. This method requires a functional trimming device, which has the drawback of increasing the manufacturing cost of the entire circuit including the hybrid integrated circuit.
本発明の目的は、上記従来技術の欠点を除き回路のトー
タルコストを下げることのできる混成集積回路を提供す
るにある。SUMMARY OF THE INVENTION An object of the present invention is to provide a hybrid integrated circuit that eliminates the drawbacks of the prior art described above and can reduce the total cost of the circuit.
この目的を達成するために、本発明は絶縁基板の表裏両
面に機能トリミング用の膜抵抗体を分割して設け、いず
れか一方の面側の膜抵抗体をトリミングすることにより
、リードの延出方向に拘らず同一の機能トリミング装置
を用いて回路の特性を調整できるようにした点に特徴が
ある。In order to achieve this object, the present invention provides film resistors for functional trimming on both the front and back sides of an insulating substrate, and trims the film resistor on either side to extend the leads. The feature is that the circuit characteristics can be adjusted using the same functional trimming device regardless of the direction.
以下、本発明の実施例を図面について説明する。 Embodiments of the present invention will be described below with reference to the drawings.
第1図及び第2図は本発明忙よる混成集積回路の断面図
であって、6は膜導体、7はスルーホール導体、8.9
は膜抵抗体であり、第4図及び第5図に対応する部分に
は同一符号を付けである。1 and 2 are cross-sectional views of a hybrid integrated circuit according to the present invention, in which 6 is a membrane conductor, 7 is a through-hole conductor, and 8.9 is a through-hole conductor.
is a film resistor, and parts corresponding to FIGS. 4 and 5 are given the same reference numerals.
第1図及び第2図において、絶縁基板1の表裏両面には
所望のパターンの膜導体6が形成され、また絶縁基板1
の表裏両面を導通するようにスルーホール導体7が形成
されている。このスルーホール導体7と絶縁基板1の一
面に形成された前記膜導体6との間には第1の膜抵抗体
8が形成され、また、スルーホール導体7と絶縁基板1
の他面に形成された膜導体6との間には第2の膜抵抗体
9が形成されており、さらに第2の膜抵抗体9が形成さ
れた側の絶縁基板1上には膜導体6と接続するように電
子回路ブロック2が半田付けされている。1 and 2, film conductors 6 of a desired pattern are formed on both the front and back surfaces of the insulating substrate 1, and the insulating substrate 1
A through-hole conductor 7 is formed so as to conduct electricity between both the front and back sides. A first film resistor 8 is formed between the through-hole conductor 7 and the film conductor 6 formed on one surface of the insulating substrate 1.
A second film resistor 9 is formed between the film conductor 6 formed on the other surface, and a film conductor is further formed on the insulating substrate 1 on the side on which the second film resistor 9 is formed. An electronic circuit block 2 is soldered to be connected to 6.
絶縁基板1の両端には、表裏両面の膜導体6と接続する
ようにリード5が半田付けされているが、このリード5
は、第1図では第2の膜抵抗体9が形成された面側に延
出しており、第21図では第1の膜抵抗体8が形成され
た面側に延。Leads 5 are soldered to both ends of the insulating substrate 1 so as to be connected to the film conductors 6 on both the front and back surfaces.
In FIG. 1, it extends to the side where the second film resistor 9 is formed, and in FIG. 21, it extends to the side where the first film resistor 8 is formed.
出している。It's out.
このように、絶縁基板1に対するリード5の延出方向が
互いに異なる2糎類の混成集積回路を図示しないプリン
ト基板にリード5を介して半田接続した後、これら混成
集積回路を含むプリント基板に組込まれた回路を動作さ
せ、その回路全体の特性を測定しつつ上記膜抵抗体8も
しくは9をトリミングする。かかる機能トリミングは、
第1図に示す構造の混成集積回路では第1の膜抵抗体8
を、第2図に示す構造の混成集積回路では該第1の膜抵
抗体8の反対面に設けた第2の膜抵抗体9をトリミング
すれば良く、それ故、1つの機能トリミング装置(図示
せず)を用いて2種類の混成集積回路の機能トリミング
を行うことが可能となる。In this way, two types of hybrid integrated circuits, in which the extending directions of the leads 5 with respect to the insulating substrate 1 are different from each other, are soldered to a printed circuit board (not shown) via the leads 5, and then assembled into the printed circuit board containing these hybrid integrated circuits. The film resistor 8 or 9 is trimmed while operating the circuit and measuring the characteristics of the entire circuit. Such feature trimming is
In the hybrid integrated circuit having the structure shown in FIG.
In the hybrid integrated circuit having the structure shown in FIG. 2, it is only necessary to trim the second film resistor 9 provided on the opposite surface of the first film resistor 8. Therefore, one functional trimming device (FIG. (not shown) can be used to perform functional trimming of two types of hybrid integrated circuits.
第5図は混成集積回路化の可能な電子回路の一例を示す
回路図であって、2は増幅器等の電子回路ブロック%
R4e B雪は可変抵抗であり、これら可変抵抗R1,
R雪のいずれか一方を調整することにより、入力に対す
る出力値を所望の値に調整できるようになっている。第
1図及び第2図に示す混成集積回路は、かかる回路を集
積化した具体例であり、第1の膜抵抗体8がR1に、第
2の膜抵抗体9がR2にそれぞれ相当し、そわ故、第1
の膜抵抗体8をトリミングした場合も第2の膜抵抗体9
をトリミングした場合も、電子回路ブロック2の電気的
特性を同じように調整することが可能となる。FIG. 5 is a circuit diagram showing an example of an electronic circuit that can be made into a hybrid integrated circuit, and 2 is an electronic circuit block percentage such as an amplifier.
R4e B snow is a variable resistance, and these variable resistances R1,
By adjusting either one of the R snows, the output value relative to the input can be adjusted to a desired value. The hybrid integrated circuit shown in FIGS. 1 and 2 is a specific example of integrating such circuits, in which the first film resistor 8 corresponds to R1, the second film resistor 9 corresponds to R2, and Because of the fidget, number 1
Even when trimming the second film resistor 8, the second film resistor 9
Even when the electronic circuit block 2 is trimmed, the electrical characteristics of the electronic circuit block 2 can be adjusted in the same way.
以上説明したように、本発明によれば機能トリミング用
の膜抵抗体を絶縁基板の表裏両面に分割して設け、いず
れか−面側の膜抵抗体をトリミングするようにしたため
、リードの延出方向が互い忙反対である2種類の混成集
積回路を同一の回路基板に半田接続した場合においても
これら混成集積回路を同一型式の機能トリミング装置を
用いてトリミングでき、それ故、2′!11類あるいは
極めて複雑な機能トリミング装置を必要としていた従来
技術に比べて回路のトータルコストを下げることができ
る。As explained above, according to the present invention, the film resistor for functional trimming is provided separately on both the front and back surfaces of the insulating substrate, and the film resistor on either side is trimmed, so that the leads can be extended. Even if two types of hybrid integrated circuits with opposite directions are soldered to the same circuit board, these hybrid integrated circuits can be trimmed using the same type of functional trimming device, and therefore 2'! The total cost of the circuit can be lowered compared to the conventional technology which requires a category 11 or extremely complicated function trimming device.
第1図及び第2図は本発明による混成集積回路の一実施
例を示す断面図、第3図は混成集積回路化の可能な電子
回路の一例を示す回路図、第4図及び第5図は従来の混
成集積回路の一例を示す斜視図である。
1・・・絶縁基板、 2・・・電子回路ブロック
、5・・・リード、 6・・・膜導体、7・・
・スルーホール導体、
8.9・・・膜抵抗体。
第 3 区
躬 )囚1 and 2 are cross-sectional views showing one embodiment of a hybrid integrated circuit according to the present invention, FIG. 3 is a circuit diagram showing an example of an electronic circuit that can be made into a hybrid integrated circuit, and FIGS. 4 and 5 1 is a perspective view showing an example of a conventional hybrid integrated circuit. DESCRIPTION OF SYMBOLS 1... Insulating substrate, 2... Electronic circuit block, 5... Lead, 6... Film conductor, 7...
・Through-hole conductor, 8.9...Membrane resistor. 3rd Ward) Prisoner
Claims (1)
を絶縁基板上に設けてなる混成集積回路を、前記リード
を介して他の回路基板に接続し、回路を動作させながら
前記膜抵抗体をトリミングすることにより、当該回路の
電気的特性を調整するようにしたものにおいて、前記絶
縁基板の表裏両面に前記膜抵抗体を分割して設け、これ
ら膜抵抗体のいずれか一方をトリミングすることにより
、回路の電気的特性を調整できるようにしたことを特徴
とする混成集積回路。1. A hybrid integrated circuit including at least an electronic circuit block, a membrane resistor, and a lead provided on an insulating substrate is connected to another circuit board via the lead, and the membrane resistor is trimmed while operating the circuit. In the device in which the electrical characteristics of the circuit are adjusted by doing so, the film resistor is dividedly provided on both the front and back surfaces of the insulating substrate, and by trimming one of these film resistors, A hybrid integrated circuit characterized by being able to adjust the electrical characteristics of the circuit.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP60070840A JPS61230351A (en) | 1985-04-05 | 1985-04-05 | Hybrid integrated circuit |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP60070840A JPS61230351A (en) | 1985-04-05 | 1985-04-05 | Hybrid integrated circuit |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS61230351A true JPS61230351A (en) | 1986-10-14 |
Family
ID=13443159
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP60070840A Pending JPS61230351A (en) | 1985-04-05 | 1985-04-05 | Hybrid integrated circuit |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS61230351A (en) |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH0438132U (en) * | 1990-07-27 | 1992-03-31 | ||
US20110193204A1 (en) * | 2010-02-05 | 2011-08-11 | Hynix Semiconductor Inc. | Semiconductor device |
-
1985
- 1985-04-05 JP JP60070840A patent/JPS61230351A/en active Pending
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH0438132U (en) * | 1990-07-27 | 1992-03-31 | ||
US20110193204A1 (en) * | 2010-02-05 | 2011-08-11 | Hynix Semiconductor Inc. | Semiconductor device |
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