JPS61234067A - High density dram cell - Google Patents

Abstract

PURPOSE:To prevent a current from leaking by forming a thick oxide film for separating between cells at the center of the bottom of a trench on a high density substrate, thereby eliminating a punch through in the deep trench portion. CONSTITUTION:A trench is formed by etching in the depth deeper than the thickness in a P-type epitaxial layer 2. In other words, the trench is formed in the depth deeper than the upper surface of a P-type Si substrate 1. A thick oxide film 3 is formed as a thick insulating film in the bottom of the trench so as to be slightly higher than the upper surface of the substrate 1, the cells are separated at A-A' line into the thick film 3 and the substrate 1 to separate between the cells. Thus, the leakage of the current due to the punch through in the portion deeper than the trench which was a disadvantage for a trench capacitor can be prevented.

Description

Detailed Description of the Invention (Field of Industrial Application) The present invention provides a high-density DRAM that prevents leakage current due to punch-through in the deep part of a trench and enables high-density DRAM. Regarding DRAM cells.

(Prior art) Conventional structure of DRAM cell in this building t-8ympoa-
ium on VLSI Technology 1
Fig, 1 of 984, P, P 18 (hereinafter referred to as the first known document) and IEDM 1984 P, P 2
48 (hereinafter referred to as wJ2 public literature), Fig. 1 shows this.

Both figs of this first known document 1 and second known document 2
Both of the cell capacitances are formed by forming n regions on the inner surfaces (side surfaces and bottom surfaces) of the trench type capacitor, and are used in one cell.

As shown in item (D) of Table 2, the cell capacity in the first known document is COX + ΔCox + CJ ・・・・・・・・・
It becomes 111.

Here, Cox is the gate oxide film capacitance of the St flat part outside the trench, and ΔCox is the gate oxide film capacitance % in the trench part.
J is the sum of the N+P- junction capacitance at the epitaxial portion and the N''P+ junction capacitance at the trench bottom.

Also, the cell capacity of the second known document is 'l' of the first known document.
The cell structure corresponds to the (C) term of ABLE 2, C
OX+ΔCox・・・・・・・・・
- The capacitance corresponds to (2), and the capacitance for pCJ is smaller than that of the cell in the first known document, but the operating function as a one-transistor cell is basically the same.

(Problem that the invention attempts to solve) However, the above structures have the following drawbacks in common.

When +11.2 capacitors are considered, it becomes as shown in Fig. 1 of the first known document. As shown in Fig. 3, the disadvantage of such a structure is that the deep region of the trench does not contain the impurities implanted by channel stop ions, so the nine layers expand from each other's trench sides greatly, and the punch Leakage current is likely to occur due to the through phenomenon.

Therefore, when considering the submicron level of 1 megabit DRAM and beyond in the future, it will no longer be possible to narrow the spacing between these capacitors, making it unsuitable for high density.

(2) In these structures, one trench is occupied by one capacitor, so a thin silicate film on the bottom surface is used for the capacitor.

In the future, when a small trench is formed by etching, the bottom of the trench will be formed with a triangular abrasion convex part, so electrode concentration and active dyes will easily remain in this part, and gate film breakdown will occur in this part. It becomes a problem.

This invention solves the problems of the above-mentioned prior art.
A high-density DRA that solves the problems of leakage current due to punch-through phenomenon, making it impossible to increase density, and gate film breakdown easily occurring at the bottom of the trench.
M cell t- provides.

(Means for Solving the Problems) According to the present invention, in a high-density DRAM cell, a thick oxide film for cell isolation is formed on a heavily doped substrate at the center of the bottom of a trench.

(Function) According to the present invention, since the high-density DRAM cell is configured as described above, punch-through in the deep part of the trench is eliminated, and leakage current is prevented, and the field part In addition, both sides of the trench can be used with different cells, thus eliminating the above-mentioned problem.

(Example) Hereinafter, an example of a high-density DRAM cell of the present invention will be described based on the drawings. FIG. 1 is a sectional view showing the configuration of one embodiment, and FIG. 2 is an enlarged perspective view taken along line AA' in FIG. 1.

In both FIG. 1 and FIG. 2, 1 is P-type St
Q in the substrate is 5 from the impurity concentration of the n-type diffusion layer 4, which will be described later.
192G containing more than double the concentration of boron
-3 (more than 1010 cWl).

P-epitaxial layer 2 on P-OP W Si substrate 1
is growing. This P-epitaxial layer 2-4μ
Contains low concentration boron of m (1o15 1016 Tsuba-3)
I'm reading.

A trench is formed in this P-epitaxial layer 2 by etching to a depth greater than the depth of this P-epitaxial layer 2. That is, the trench is formed slightly deeper than the upper surface of the P-type St substrate 1.

At the bottom of this trench, a thick oxide film 3 is formed as a thick insulating film so as to be slightly higher than the top surface of the P-type S1 substrate 1. Due to this strong oxide film 3, P-type St substrate 1, and impurity concentration, apart from the curve on the A-A' line in Figure 1,
We are trying to separate cells.

Further, as shown in the second factor, the surfaces of the trench used for the capacitor are the B surface, the 0 surface, the D surface, and the E surface.

Furthermore, an n-type diffusion layer 4 is formed on the inner surface of the trench. This n-type diffusion layer 4 (which may be omitted if the cell plate is of the Vce type) is formed, and a capacitor oxide film 5 is formed on its outer surface. The inner surface of this capacitor oxide film 5 is the B side in FIG. 2, and the upper surface is the 0 side in FIG. The upper surfaces of the n-type region 4 and the capacitor oxide film 5 are formed on the P'' epitaxial layer 2.

Further, a polysilicon layer is formed in the trench, and this polysilicon layer fills the trench.

On the P- epitaxial layer 2, an n+ diffusion layer 7. and a bit line N+ diffusion layer 10 are formed,
Between the N diffusion layers 7 and 10, a gate film 8 of a transfer gate transistor is formed on the P- epitaxial layer 2, and a transfer gate film 9 is formed thereon.

In this way, one transistor (ITr) is formed on the left side and the right side of the line A-A' in FIG. It is being said.

FIGS. 3A to 3G are diagrams showing the manufacturing process of the high-density DRAM cell of the present invention configured as described above. First, as shown in FIG. 3(A), a 2- Contains 4μm of low concentration boron (10151
016 cm-3) Grow P-epitaxial layer 2. Next, trench 3a is selectively etched to a depth equal to or greater than the thickness of P-epitaxial layer 2.

Next, as shown in FIG. 3(B), the PSG film 1 is deposited on one surface, and a resist 12 is applied thereon. Using this resist 12 as a mask, a pattern is left on the trench 3a. , n-type diffusion layer 4 (containing phosphorus concentration 10172×10 an ) selectively by diffusion on PSG film 1
form.

At this time, since the boron concentration of the P-type Sl substrate 1 is higher than the phosphorus concentration of the n-type diffusion layer 4, the structure is such that the n-type diffusion layer 4 is not formed on the bottom surface portion.

Subsequently, as shown in FIG. 3C, a thick oxide film 3 is formed by etching, leaving a thickness of 13 to 1.0 μm on the bottom PSG film 1 to be used as a field oxide film.

If the n-type diffusion layer 4t is not required (when the cell plate is used at Vcc and the combined capacitance of the n-type diffusion layer 4 and the P-epitaxial layer 2 is not used as a capacitance), The same is possible if a 1-doped SLO snow film is used.

Next, the first resist 12 on the PSG film 1 was removed, and as shown in FIG.
As shown in C), @l gate film 13 (Sins film 10
0A or 5ift 50A + 5isN4100
A) is formed on the entire surface, and the first polysilicon 14 containing phosphorus is deposited thereon to a thickness greater than that above the trench 3a.

Thereafter, patterning is carried out using a conventional method to form a capacitor oxide film 5 and a capacitor portion made of polysilicon, as shown in FIG. 3(D). At this time, this pattern needs to be formed so that the n-type diffusion layer 4 is also inside.

Next, as shown in FIG. 3(E), a second gate oxide film 1 is formed.
5tO2 film 200A of No. 5 and the entire surface of second polysilicon 16t-300OA containing phosphorus.

Next, as shown in FIG. 3(F), the gate portion of the transistor forming the transfer gate and the peripheral circuit, that is, the gate film 8, the transformer 7, and the agate 9 are patterned using the usual method, and then As ion implantation is performed. And the drain region of the n diffusion layer 7 and the N+ diffusion layer 10t of the bit line? Form. At this time, the impurity concentration of the source/drain region is higher than that of the n-type diffusion layer 4! 11102-10
Since it is three times higher, the overlap part (part B) has n soil layers.

From then on, as shown in m3 diagram (G), normal intermediate insulation Bl
&17 is deposited on the entire surface, the contact part 1st is opened, and A
A pattern of the t-wiring layer 19 is formed.

(Effects of the Invention) As described above in detail, the present invention has the following effects.

il+ and the distance mi between the cells at the bottom of the trench, it is possible to prevent leakage current due to punch-through in the deep part of the trench, which is a drawback of trench capacitors.

+21, since both sides of one trench are used by different cells, higher density is possible.

(3) Since the bottom part of the trench is used as the field part, it solves the drawback of trench capacitors, which is the low breakdown electric field of the gate dielectric film at the bottom part, and can also be used for trench type isolation. can.

+41, the P+ substrate concentration at the bottom of the trench is used as the channel stop concentration, making it possible to eliminate the normally required chance implant process.

(5) Since the structure has a P-thousand bitaxial layer on a Psi substrate, the structure shown in the first known document has (a
It has the following advantages: a) high resistance to contact errors, Φ) good crystallinity of the P-epitaxial layer, (c) good dielectric strength of the gate film, and (d) low hold time defects.

[Brief explanation of drawings]

FIG. 1 is a cross-sectional view showing the structure of an embodiment of a high-density DRAM cell according to the present invention, FIG. 2 is an enlarged perspective view cut along line A- in FIG. 1, and FIG. A) to Figure 3 (
G) is a process explanatory diagram of the method for manufacturing a high-density DRAM cell of the present invention. DESCRIPTION OF SYMBOLS 1... P-type S1 substrate, 2... P-epitaxial layer, 3... Thick oxide film, 4... N-type diffusion layer, 5...
Capacitor oxide film, 6... polysilicon, 7. lO・
...N'' diffusion/i, 8...gate film, 9...transformer 7 agate.

Claims (1)

[Claims] A low concentration epitaxial layer is formed on a high concentration substrate and contains an impurity of the same conductivity type as that of the high concentration substrate, and the capacitor element is separated at the bottom of a trench formed to a thickness greater than the thickness of this epitaxial layer. A high-density DRAM cell comprising: a thick insulating film used as a capacitor; a capacitor portion formed in the trench; and a transfer gate and food drain region formed on the P^-epitaxial layer.