JPS6120362A - Ic case - Google Patents
Ic caseInfo
- Publication number
- JPS6120362A JPS6120362A JP59140642A JP14064284A JPS6120362A JP S6120362 A JPS6120362 A JP S6120362A JP 59140642 A JP59140642 A JP 59140642A JP 14064284 A JP14064284 A JP 14064284A JP S6120362 A JPS6120362 A JP S6120362A
- Authority
- JP
- Japan
- Prior art keywords
- power supply
- lsi chip
- power
- shape
- supplied
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01H—ELECTRIC SWITCHES; RELAYS; SELECTORS; EMERGENCY PROTECTIVE DEVICES
- H01H1/00—Contacts
- H01H1/0036—Switches making use of microelectromechanical systems [MEMS]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01H—ELECTRIC SWITCHES; RELAYS; SELECTORS; EMERGENCY PROTECTIVE DEVICES
- H01H37/00—Thermally-actuated switches
- H01H2037/008—Micromechanical switches operated thermally
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01H—ELECTRIC SWITCHES; RELAYS; SELECTORS; EMERGENCY PROTECTIVE DEVICES
- H01H37/00—Thermally-actuated switches
- H01H37/02—Details
- H01H37/32—Thermally-sensitive members
- H01H37/323—Thermally-sensitive members making use of shape memory materials
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15312—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a pin array, e.g. PGA
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/161—Cap
- H01L2924/1615—Shape
- H01L2924/16195—Flat cap [not enclosing an internal cavity]
Landscapes
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Semiconductor Integrated Circuits (AREA)
Abstract
Description
【発明の詳細な説明】
（発明の属する分野）
本発明は、集積回路が異常状態になったとき、集積回路
（ＬＳＩチップ）に供給する電源を自動的に断とする集
積回路用ケースに関するものである。[Detailed Description of the Invention] (Field to which the invention pertains) The present invention relates to an integrated circuit case that automatically cuts off power supplied to an integrated circuit (LSI chip) when the integrated circuit is in an abnormal state. It is.
（従来の技術）
論理装置をＬＳＩ化する場合、低消費電力化をねらい（
１：Ｍｏ Ｓ論理を使用する。しかしながら、ＣＭＯＳ
論理回路によるＬＳＩチップは、電源あるいは入出力信
号端子に過大な雑音が印加されると、ラッチアップとい
う現象が発生する。ラッチアップが発生すると、電源が
短絡された状態となり、ＬＳＩチップが加熱される。こ
の現象は電源を一旦断としない限り持続するため、遂に
はＬＳＩチップは破壊する。(Conventional technology) When converting a logic device into an LSI, the aim is to reduce power consumption (
1: Use MoS logic. However, CMOS
In LSI chips based on logic circuits, a phenomenon called latch-up occurs when excessive noise is applied to the power supply or input/output signal terminals. When latch-up occurs, the power supply is short-circuited and the LSI chip is heated. This phenomenon persists until the power is turned off once, and the LSI chip will eventually be destroyed.
このため、ＬＳＩチップ側ではプロセスあるいはレイア
ウト設計において各種対策を施し、許容雑音電圧を高く
するとともに、装置側でもＬＳＩの入出力信号線をプリ
ント基板間にわたらない等の各種対策を施している。ま
た、万一ラッチアップが発生しＬＳＩチップが破壊され
ても、通常は保守者が故障ＬＳＩチップあるいはこれを
搭載しているプリント基板を取替えることが可能である
。For this reason, on the LSI chip side, various measures are taken in process or layout design to increase the allowable noise voltage, and on the device side, various measures are taken, such as not running LSI input/output signal lines between printed circuit boards. Furthermore, even if a latch-up occurs and the LSI chip is destroyed, a maintenance person can usually replace the failed LSI chip or the printed circuit board on which it is mounted.
しかしながら、例えば、人工衛星にＣＭＯＳ論理回路に
よるＬＳＩチップを実装する場合には、宇宙線等の影響
によりラッチアップの発生確率が増大するとともに、一
旦ラッチアップが発生しＬＳＩチップが破壊されるとこ
れを取替えることは不可能な問題がある。また、連続運
転が要求される交換機も現在無人保守体制がとられつつ
あり、特に遠隔制御交換機では完全に無人保守となって
いる。このような交換機にＣＭＯ８論理回路によるＬＳ
Ｉチップを使用し、例えば雷等の予期しえない過大な雑
音でラッチアップが発生し、ＬＳＩチップが破壊された
場合、修復は可能であるが、修復するまでの長時間社会
に与える影響は非常に大きく、さらに、今後益々影響の
度合いは大きくなる問題がある。However, for example, when mounting an LSI chip with a CMOS logic circuit on a satellite, the probability of latch-up occurring increases due to the influence of cosmic rays, etc., and once latch-up occurs and the LSI chip is destroyed, The problem is that it is impossible to replace. In addition, unmanned maintenance systems are currently being adopted for switchboards that require continuous operation, and in particular remote control switchboards are now completely unattended. LS using CMO8 logic circuit is installed in such a switch.
If an I-chip is used and a latch-up occurs due to unexpected excessive noise such as lightning, and the LSI chip is destroyed, it is possible to repair it, but the long-term impact on society until it is repaired is There is a problem that is very large and will have an even greater impact in the future.
（発明の目的）
本発明は上記問題を解決するため、ＬＳＩチップを搭載
するケースの電源供給線の途中に、ラッチアップにより
発生した熱に感知して電源供給線を自動的に断とし、そ
の後再び接とする電源信号断接部を設けた集積回路用ケ
ースを提供しようとするものであり、以下図面について
詳細に説明する。(Object of the Invention) In order to solve the above-mentioned problems, the present invention automatically disconnects the power supply line by sensing the heat generated due to latch-up in the middle of the power supply line of the case in which the LSI chip is mounted. The present invention is intended to provide an integrated circuit case that is provided with a power signal disconnection section that can be connected again, and will be described in detail below with reference to the drawings.
（発明の構成および作用）
第１図は本発明の一実施例であるＱＩＰケースの断面図
であって、１−１〜１−ｎはケースとプリント基板とを
接続するピン、２はセラミック等で構成されたケース本
体、３はキャップ、４はＬＳＩチップ、５はＬＳＩチッ
プとケースを接続する電源供給用ワイヤ線、６はピン１
に接続された電源供給経路、７は熱に感知して電源供給
経路６を断接する電源信号断接部である。(Structure and operation of the invention) FIG. 1 is a sectional view of a QIP case which is an embodiment of the present invention, in which 1-1 to 1-n are pins connecting the case and a printed circuit board, 2 is a ceramic etc. 3 is the cap, 4 is the LSI chip, 5 is the power supply wire that connects the LSI chip and the case, 6 is the pin 1
The power supply path 7 is connected to the power supply path 6, and 7 is a power signal connection/disconnection section that senses heat and disconnects or connects the power supply path 6.
第２図は、第１図の電源信号断接部７の部分を拡大した
断面図であって、第２図（ａ）は電源信号断接部が接状
態、第２図（ｂ）は断状態を示している。FIG. 2 is an enlarged sectional view of the power signal disconnection section 7 in FIG. 1, in which the power signal disconnection section 7 is in a connected state in FIG. It shows the condition.
図中、６−１．６−２は電源供給経路、？−１は電源供
給経路６−１に接続された接点用金属、７−２．７−３
は熱を感知して形状を変える形状記憶合金あるいはバイ
メタル等で構成された断接部で、図では形状記憶合金の
例を示している。通常電源信号断接部７は第２図（ａ）
の７−２の形状をしており、電源供給経路６−１．６−
２は接続され、ＬＳＩチップ４にワイヤ線５を経由して
電源が供給される。ここで、ＬＳＩチップ４がラッチア
ップをおこすと、ＬＳＩチップ４は発熱し、その熱はケ
ース本体２、電源供給経路６−２を通して断接部７−２
に供給され、断接部７−２は第２図（ｂ）の７−３のよ
うに形状をかえ電源供給経路が切断する。これによりＬ
ＳＩチップ４に供給していた電源は断となり、次第にＬ
ＳＩチップ４、ケース本体２、電源供給経路６−２、断
接部７−３が冷却され、断接部７−３は第２図（ａ）に
示す断接部７−２の形状に戻る。これにより再び電源供
給経路６−１．６−２が接続され、ＬＳＩチップ４に電
源が供給される。In the figure, 6-1.6-2 is the power supply path, ? -1 is a contact metal connected to the power supply path 6-1, 7-2.7-3
is a disconnection section made of a shape memory alloy or bimetal that changes shape by sensing heat; the figure shows an example of a shape memory alloy. The normal power supply signal disconnection section 7 is shown in Fig. 2(a).
It has the shape of 7-2, and the power supply path 6-1.6-
2 is connected, and power is supplied to the LSI chip 4 via the wire line 5. Here, when the LSI chip 4 causes latch-up, the LSI chip 4 generates heat, and the heat is transferred to the disconnection section 7-2 through the case body 2 and the power supply path 6-2.
The connecting/disconnecting portion 7-2 changes its shape as shown at 7-3 in FIG. 2(b) and the power supply path is disconnected. This results in L
The power supply that was being supplied to SI chip 4 was cut off, and the power level gradually decreased.
The SI chip 4, the case body 2, the power supply path 6-2, and the disconnection section 7-3 are cooled, and the disconnection section 7-3 returns to the shape of the disconnection section 7-2 shown in FIG. 2(a). . As a result, the power supply paths 6-1 and 6-2 are connected again, and power is supplied to the LSI chip 4.
・第３図は本発明の他の実施例である集積回路用ＱＩＰ
ケースの断面図であって、第１図の電源信号断接部７の
部分をケース本体２の外側に設置し、製造を容易化した
ものである。図において、１〜６は第１図と同一であり
、８は熱に感知して形状を変える金属、８−１ 、８−
２は接点および熔接点で、例えば８−１がピン１からの
線と８とを完全に接続している熔接点であれば、８−２
は形状を変える金属８の形状変化によって電源供給経路
６への電源供給を行なう接点となる。逆に８−２が熔接
点ならば８−１は接点となる。・Figure 3 shows a QIP for integrated circuits which is another embodiment of the present invention.
This is a cross-sectional view of the case, in which the power signal disconnection section 7 in FIG. 1 is installed outside the case body 2 to facilitate manufacturing. In the figure, 1 to 6 are the same as in Figure 1, 8 is a metal that changes shape by sensing heat, 8-1, 8-
2 is a contact point and a welded contact point. For example, if 8-1 is a welded contact point that completely connects the wire from pin 1 to 8, then 8-2
becomes a contact point that supplies power to the power supply path 6 by changing the shape of the metal 8 that changes shape. Conversely, if 8-2 is a welding contact, 8-1 is a contact.
本例でも同様にＬＳＩチップ４がラッチアップを起こす
と、その熱が形状を変える金属８に伝達され、その金属
８の形状が変化し、接点８−２カへ開き、ＬＳＩチップ
４に供給する電源が停止する。In this example as well, when the LSI chip 4 latch-up occurs, the heat is transferred to the shape-changing metal 8, the shape of the metal 8 changes, the contact 8-2 opens, and the heat is supplied to the LSI chip 4. Power stops.
電源停止によりＬＳＩチップ４、ケース本体２、形状を
変える金属８が冷えてくると、その金属８の形状が元の
状態に復帰し、電源をＬＳＩチップ４に供給する。When the LSI chip 4, the case body 2, and the shape-changing metal 8 cool down due to power shutdown, the shape of the metal 8 returns to its original state, and power is supplied to the LSI chip 4.
いままでは集積回路用ケースはＱＩＰにつ−Ａて説明し
たが、ＳＩＰ、ＤＩＰ、チップギヤ１ノアでもよいこと
は説明するまでもない。このよつｔ’ｌｌｌ造となって
いるため、万一、ＬＳＩチップ力へラッチアップを起こ
しても自動的に電源が断、その後入となり、ＬＳＩチッ
プを破壊することカへ防止される。Up to now, the case for integrated circuits has been explained in terms of QIP, but it goes without saying that SIP, DIP, and Chip Gear 1 Noah may also be used. Because of this structure, even if a latch-up occurs in the LSI chip, the power is automatically turned off and then turned on again, preventing damage to the LSI chip.
（効 果）
以上説明したように本発明は、ＬＳＩチップ番こラッチ
アップが発生しても、ＬＳＩチップカニ破壊されないた
め、
（ｉ） 人工衛星等保守が不可能な部分にＣＭＯ８論
理回路を各種対策を完全に施すことなく使用することが
可能となる。(Effects) As explained above, in the present invention, even if an LSI chip latch-up occurs, the LSI chip will not be destroyed. It is possible to use it without applying it completely.
（ｉｉ） 連続運転要求の厳しい論理装置にＣＭＯ８
論理回路を使用しても、予期しえない雑音に対して対策
が施され、無人保守とすることが可能となる。(ii) CMO8 for logic devices with strict continuous operation requirements
Even if logic circuits are used, countermeasures against unpredictable noise can be taken and unattended maintenance can be performed.
等の利点がある。There are advantages such as
第１図は本発明の一実施例であるＱＩＰケースの断面図
、第２図は第１図の電源信号断接部７の部分を拡大した
断面図、第３図は本発明の実施例である集積回路用ＱＩ
Ｐケースの断面図である。
１．１−１〜１−ｎ・・・ ビン、 ２・・・ケース本
体、３ ・・・キャップ、 ４ ・・・ ＬＳＩチップ
、５・・・電源供給用ワイヤ線、 ６ ・・・電源供給
経路、 ７ ・・・電源信号断接部、 ８・・・熱に感
知して形状を変える金属。FIG. 1 is a sectional view of a QIP case that is an embodiment of the present invention, FIG. 2 is an enlarged sectional view of the power signal disconnection section 7 in FIG. 1, and FIG. 3 is an embodiment of the present invention. QI for a certain integrated circuit
It is a sectional view of P case. 1.1-1 to 1-n... bottle, 2... case body, 3... cap, 4... LSI chip, 5... power supply wire line, 6... power supply Route, 7...Power signal disconnection section, 8...Metal that changes shape by sensing heat.
Claims (1)
る電源供給経路の途中に、熱により変形する部分を介し
て電源信号を断接する電源信号断接部を有することを特
徴とする集積回路用ケース。A case for mounting an integrated circuit, characterized in that the case has a power signal connection/disconnection part for connecting/disconnecting a power signal via a part deformed by heat, in the middle of a power supply path for supplying power to the integrated circuit.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP59140642A JPS6120362A (en) | 1984-07-09 | 1984-07-09 | Ic case |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP59140642A JPS6120362A (en) | 1984-07-09 | 1984-07-09 | Ic case |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS6120362A true JPS6120362A (en) | 1986-01-29 |
Family
ID=15273414
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP59140642A Pending JPS6120362A (en) | 1984-07-09 | 1984-07-09 | Ic case |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6120362A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5463233A (en) * | 1993-06-23 | 1995-10-31 | Alliedsignal Inc. | Micromachined thermal switch |
| EP1207553A1 (en) * | 2000-11-16 | 2002-05-22 | ABB Schweiz AG | Fixing device for pressure contacted high power semiconductor device |
-
1984
- 1984-07-09 JP JP59140642A patent/JPS6120362A/en active Pending
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5463233A (en) * | 1993-06-23 | 1995-10-31 | Alliedsignal Inc. | Micromachined thermal switch |
| EP1207553A1 (en) * | 2000-11-16 | 2002-05-22 | ABB Schweiz AG | Fixing device for pressure contacted high power semiconductor device |
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