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JPS6120334A - Manufacture of semiconductor device - Google Patents

Manufacture of semiconductor device

Info

Publication number
JPS6120334A
JPS6120334A JP14058084A JP14058084A JPS6120334A JP S6120334 A JPS6120334 A JP S6120334A JP 14058084 A JP14058084 A JP 14058084A JP 14058084 A JP14058084 A JP 14058084A JP S6120334 A JPS6120334 A JP S6120334A
Authority
JP
Japan
Prior art keywords
photoresist
positive
aperture
insulating film
aperture window
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP14058084A
Other languages
Japanese (ja)
Inventor
Kenji Anzai
賢二 安西
Fumio Otoi
音居 文雄
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Oki Electric Industry Co Ltd
Original Assignee
Oki Electric Industry Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Oki Electric Industry Co Ltd filed Critical Oki Electric Industry Co Ltd
Priority to JP14058084A priority Critical patent/JPS6120334A/en
Publication of JPS6120334A publication Critical patent/JPS6120334A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Drying Of Semiconductors (AREA)
  • Weting (AREA)

Abstract

PURPOSE:To process the aperture of the insulation film in taper form with photo resist left in the other part by a method wherein, even in a state of unexposure of a positive resist, the aperture window of the photo resist is enlarged by utilizing that it slightly melts in its developer. CONSTITUTION:An aperture window 26 is formed in part of the third positive photo resist 25 by the photolithography technique. An aperture window 28 is formed in the same shape at the position of the aperture window 26 in the second negative photo resist 24 and the first positive photo resist 23 by derective dry etching 27. A vertical aperture 30 is formed in the insulation film 22 by corresponding to the aperture window 28 by the directive dry etching 29 of the insulation film 22. The aperture window 28 at the part of the first positive photo resist 23 around the aperture window 28 is enlarged by dipping in a positive developer. Then, the aperture 30 is processed in taper form by removing the exposed rectangular part of the insulation film 22 by wet etching with a buffer solution of hydrofluoric acid or the like.

Description

【発明の詳細な説明】 (産業上の利用分野) この発明は半導体装置の製造方法に係り、特に絶縁膜の
開孔方法に関する。
DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to a method for manufacturing a semiconductor device, and more particularly to a method for opening holes in an insulating film.

(従来の技術) 半導体装置においては、導体層間の接続のために、絶縁
膜に開孔部を形成することが行われている。その開孔部
の形成方法の従来例を第2図を参照して説明する。第2
図(a)は、半導体基板上にMOS)ランジスタを形成
した後、層間絶縁膜を形成した図で、11は半導体基板
、12は拡散層、13はr−上電極、14は熱酸化膜、
15は層間絶縁膜である。この層間絶縁膜15に開孔部
を形成する場合は、まず、この層間絶縁膜15上に、所
望の位置において開孔窓16を有するホトレジストパタ
ーンエフを第2図(b)に示すように形成した後、同第
2図(b)に示すようにこのホトレジストパターン17
をマスクとして層間絶縁膜15をドライエツチングする
ことにより、この層間絶縁膜15に、開孔窓16の位置
でこれと同一寸法に取り敢えず垂直の開孔部18を形成
する。その後、ホトレジストパターン17を剥離する。
(Prior Art) In semiconductor devices, openings are formed in an insulating film for connection between conductor layers. A conventional method for forming the opening will be explained with reference to FIG. 2. Second
Figure (a) is a diagram in which an interlayer insulating film is formed after forming a MOS transistor on a semiconductor substrate, in which 11 is a semiconductor substrate, 12 is a diffusion layer, 13 is an r-upper electrode, 14 is a thermal oxide film,
15 is an interlayer insulating film. When forming an opening in this interlayer insulating film 15, first, a photoresist pattern F having an opening window 16 at a desired position is formed on this interlayer insulating film 15 as shown in FIG. 2(b). After that, as shown in FIG. 2(b), this photoresist pattern 17 is
By dry etching the interlayer insulating film 15 using as a mask, a vertical opening 18 is temporarily formed in the interlayer insulating film 15 at the position of the opening window 16 and having the same dimensions. Thereafter, the photoresist pattern 17 is peeled off.

そして、ホトレジストパターン17がない状態で全面ウ
ェットエツチング処理を施すことにより、第2図(e)
K示すように、開孔部18部分の熱酸化膜14を除去す
ると同時K、開孔部18をテーパ状とする。
Then, wet etching is performed on the entire surface without the photoresist pattern 17, as shown in FIG. 2(e).
As shown in FIG. 1, when the thermal oxide film 14 in the portion of the opening 18 is removed, the opening 18 is made into a tapered shape.

また、この全面ウェットエツチング処理によυ、層間絶
縁膜15の段走部は斜面19となる。しかる後、開孔部
18を含む層間絶縁膜15上には、第2図(d)に示す
ように配線金属層20が形成され、その後この配線金属
層20が図示しないがバターニングされる。
Further, by this whole-surface wet etching process, the stepped portion of the interlayer insulating film 15 becomes a slope 19. Thereafter, a wiring metal layer 20 is formed on the interlayer insulating film 15 including the opening 18, as shown in FIG. 2(d), and then this wiring metal layer 20 is patterned (not shown).

(発明が解決しようとする問題点) しかるに、このような従来の方法では、層間耐圧が低下
したりば化膜容量が増加する問題、さらには層間ショー
トを引き起こす欠点があった。すなわち、上記従来方法
では、層間絶縁膜15の角部のエツチングレートが速い
ことを利用して全面ウェットエツチング処理によシ開孔
部18にテーパをつけるのであるが、この全面ウェット
エツチング処理によシ層間絶m膜15の膜匣り、あるい
は局所的にピンホールが形成されることがあるので、層
間耐圧の低下および酸化膜容量の増大が生じたり、層間
ショートを引き起こす。なお、角部のエツチングレート
が速いことを利用するので、ホトレジストパターン17
をつけた一Eta(第2図(b)の状態)でエツチング
を行い熱酸化膜14を除去し、同時に開孔部18をテー
パ状にしようとしても、テーパなつけることは困難であ
る。
(Problems to be Solved by the Invention) However, such conventional methods have the disadvantages of lowering the interlayer breakdown voltage, increasing the film capacitance, and further causing interlayer short circuits. That is, in the conventional method described above, the opening 18 is tapered by wet etching the entire surface by taking advantage of the high etching rate at the corners of the interlayer insulating film 15. A film hole or a pinhole may be formed locally in the interlayer insulation film 15, resulting in a decrease in interlayer breakdown voltage, an increase in oxide film capacitance, and an interlayer short circuit. Note that since the etching rate of the corners is high, the photoresist pattern 17
Even if etching is performed to remove the thermal oxide film 14 and at the same time make the opening 18 tapered, it is difficult to make the opening 18 tapered.

(間組点を解決するための手段) そこで、この発明では、ポジ型ホトレジストが未感光状
態でも、その現像液にわずかに溶解する性質を利用して
、ホトレジストの開孔窓な広けることにより、他部にホ
トレジストを残した状態で絶縁膜の開孔部をテーパ状に
加工できるようにする。
(Means for solving the interpolation point problem) Therefore, in the present invention, by widening the aperture window of the photoresist by utilizing the property that the positive photoresist is slightly soluble in the developer even in an unexposed state, To process an opening in an insulating film into a tapered shape while leaving photoresist in other parts.

(作用) この方法によればq開孔部以外にホトレジストが残った
状態で、絶縁膜の開孔部のテーパ状加工が行われるので
、絶縁膜の膜減ル、あるいは絶縁膜に局所的にピンホー
ルが形成されることがなくなる。
(Function) According to this method, the openings in the insulating film are tapered with photoresist remaining in areas other than the q openings. Pinholes are no longer formed.

(実施例) 第1図はこの発明の一実施例を示す。以下、この一実施
例について説明する。
(Embodiment) FIG. 1 shows an embodiment of the present invention. This embodiment will be described below.

第1図(a) において、21は半導体基板、22はそ
の上の絶縁膜であ)、まずこの絶縁膜22上にポジ型の
第1のホトレジスト23.ネガ型の第2のホトレジスト
24およびポジ型の第3のホトレジスト25を順次菫布
する。そして、ポジ型の第3のホトレジスト25の一部
に、周知のホトリソ技術によシ所望の開孔窓26を形成
する。々お、第1および第2のホトレジスト2a、2+
はi厚3000λ程度、第3のホトレジスト25は膜厚
をaoooA程度とする。このようなホトレジスト族厚
にすることにより、以下の工程によって良好な開孔形状
を得ることができる。
In FIG. 1(a), 21 is a semiconductor substrate, 22 is an insulating film thereon), and first, a positive type first photoresist 23. is applied on this insulating film 22. A negative type second photoresist 24 and a positive type third photoresist 25 are sequentially applied. Then, a desired opening window 26 is formed in a part of the positive type third photoresist 25 by a well-known photolithography technique. First and second photoresists 2a, 2+
The thickness of i is about 3000λ, and the thickness of the third photoresist 25 is about aoooA. By using such a photoresist thickness, a good opening shape can be obtained through the following steps.

次に、第1図(b)に示すように、ホトレジストの方向
性ドライエツチング27を施すことにより、ネガ型の第
2のホトレジスト24およびポジ型ノ第1のホトレジス
ト23に、ポジ型の第3のホトレジスト25の開孔窓2
6の位置で同一形状に開孔窓28を形成する。この時、
ポジ型の第3のホトレジスト25#2除去されても問題
がない(この実施例ではすべて除去されている)が、残
存する第1のホトレジスト23の熱変化をできるだけ蒋
けるようにすることが望ましい。そのため、例えば少な
くとも第1のホトレジスト23に耐熱レノストを用ノい
るが、冷却しながらドライエツチングを行うもので、こ
れによりポジ型の第1のホトレジスト23の熱変化を防
ぐことによル、後のポジ型現像液による溶解性をもたせ
ておく。
Next, as shown in FIG. 1(b), by subjecting the photoresist to directional dry etching 27, the negative type second photoresist 24 and the positive type first photoresist 23 are coated with the positive type third photoresist. Opening window 2 of photoresist 25
An aperture window 28 is formed in the same shape at position 6. At this time,
There is no problem even if the positive type third photoresist 25#2 is removed (in this example, it is all removed), but it is desirable to reduce thermal changes in the remaining first photoresist 23 as much as possible. . For this reason, for example, a heat-resistant resin is used for at least the first photoresist 23, and dry etching is performed while cooling. It must be soluble in a positive developing solution.

次K、第1図(e)に示すように、残存するホトレジス
ト24.23をマスクとし゛C絶縁膜22の方向性ドラ
イエツチング29を施すことにょシ、この絶縁膜22に
前記開孔窓28に対応して垂直の開孔部30を形成する
Next, as shown in FIG. 1(e), using the remaining photoresist 24, 23 as a mask, directional dry etching 29 of the insulating film 22 is applied to the insulating film 22 in the opening window 28. Correspondingly, vertical apertures 30 are formed.

その後、ポジ型現像液に浸漬することで、あるいは基板
側を同転させなからポジ壓現像液を振シ掛ける(これを
スピン状像という)ことで、開孔窓28周囲のポジ型の
第1のホトレジスト23を若干i、溶解させることによ
り、この第1のホトレジスト23部分の前記開孔窓28
を第1図(d) K示すように広ける。すなわち、ポジ
屋ホトレジストは、通常、感光部が現像液により除去さ
れるのであるが、木感光状態でも、レヅストの熱誕化を
防いであると、現像液によって溶解される。そして、こ
の性質を々り用して、ポジ型の第1のホトレジスト23
hμ 孔部30上端VCおける絶縁膜22の角部が、他の上に
第1のホトレジスト23を残した状態で露出する。
Thereafter, by immersing the substrate in a positive developer, or by sprinkling a positive developer without rotating the substrate side (this is called a spin image), the positive developer around the aperture window 28 is formed. By slightly dissolving the first photoresist 23, the opening window 28 in the first photoresist 23 portion is formed.
Spread out as shown in Figure 1(d). That is, in a positive photoresist, the exposed area is usually removed by a developer, but even in a wood-exposed state, if the resist is prevented from becoming hot, it will be dissolved by the developer. By making full use of this property, a positive type first photoresist 23 is formed.
hμ A corner of the insulating film 22 at the upper end VC of the hole 30 is exposed with the first photoresist 23 remaining on the other side.

そこで、最後に、絶縁膜22の露出角部を弗酸緩衝液な
どKよるウェットエツチングで除去することにより、開
孔部30を第1図(6)に示すようにテーパ状に加工す
る。この後は図示しないが、公知の手段で配線等をして
半導体装置を完成させる。
Finally, the exposed corner portions of the insulating film 22 are removed by wet etching using K such as a hydrofluoric acid buffer, thereby forming the openings 30 into a tapered shape as shown in FIG. 1(6). After this, although not shown, wiring and the like are performed by known means to complete the semiconductor device.

(発明の効果) 以上詳述したように、この発明の方法Vこよれば、ボヅ
型ホトレジストが未感光状態でも、その現像液にわずか
に溶解する性質を利用して、ホトレジストの開孔窓を広
げることによシ、開孔部以外にホトレジストが残った状
態で、絶縁膜の開孔部のテーパ加工を行い得る。よって
、全面ウェットエツチング処理による併置、すなわち絶
縁膜の膜秋り、およびピンホールの発生を防止できるも
ので、これにより層間耐圧の低下、酸化膜容量の増大お
よび層間ショートの発生を防止できる。
(Effects of the Invention) As described in detail above, according to the method V of the present invention, the opening windows of the photoresist can be formed by utilizing the property that the pot-shaped photoresist is slightly dissolved in the developer even in an unexposed state. By widening the opening, the opening in the insulating film can be tapered with the photoresist remaining in areas other than the opening. Therefore, it is possible to prevent the juxtaposition caused by the whole-surface wet etching process, that is, the fall of the insulating film, and the generation of pinholes, thereby preventing a decrease in interlayer breakdown voltage, an increase in oxide film capacitance, and the occurrence of interlayer short circuits.

また、この発明によれば、絶縁膜に垂直の開孔部を形成
する際の小開孔窓と、前記開孔部をテーパ状とする際の
大開孔窓とを3層のホトレジストの組合わせで形成して
おり、このような開孔窓な形成するためにポリシリコン
や限化朕ゆるいはメタルなどを必要としないので、工程
が容易にな少工数も削減できる。
Further, according to the present invention, a combination of three layers of photoresist is used to form a small aperture window when forming a perpendicular aperture in the insulating film and a large aperture window when forming the aperture into a tapered shape. Since polysilicon or loose metal is not required to form such an aperture window, the process is easy and the number of man-hours can be reduced.

さらに、開孔窓の拡張(大開孔窓の形成)を、未感光状
態のホソ型ホトレジストかそ01m液に若干量溶解する
ことを利用して行っているので、開孔窓の拡張を高精度
に制御できる。
Furthermore, the expansion of the aperture window (formation of a large aperture window) is carried out by dissolving a small amount of photoresist in an unexposed state in the 01m solution, so the aperture window can be expanded with high precision. Can be controlled.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図はこの発明の半導体装置の装造方法の一実施例を
示す断面図、第2図は絶縁膜に開孔部を形成する従来の
方法を示す断面図である。 21・・・半導体基板、22・・・絶縁膜、23・・・
ポジ型の第1のホトレジスト、24・・・ネガ型の第2
のホトレジスト、25・・・ポジ型の第3のホトレジス
ト、26・・・開孔窓、27・・方向性ドライエツチン
グ、28・・開孔窓、29・・方向性ドライエツチング
、30・・・開孔部。
FIG. 1 is a sectional view showing an embodiment of the method for manufacturing a semiconductor device according to the present invention, and FIG. 2 is a sectional view showing a conventional method for forming an opening in an insulating film. 21... Semiconductor substrate, 22... Insulating film, 23...
positive type first photoresist, 24... negative type second photoresist;
photoresist, 25... positive type third photoresist, 26... aperture window, 27... directional dry etching, 28... aperture window, 29... directional dry etching, 30... Open hole.

Claims (1)

【特許請求の範囲】[Claims]  半導体基板上の絶縁膜上にポジ型の第1のホトレジス
ト、ネガ型の第2のホトレジストおよびポジ型の第3の
ホトレジストを順次塗布し、ポジ型の第3のホトレジス
トに所望の開孔窓を形成する工程と、この工程の後にホ
トレジストの方向性エッチングを施すことにより、ネガ
型の第2のホトレジストおよびポジ型の第1のホトレジ
ストに、ポジ型の第3のホトレジストの開孔窓位置で同
一形状に開孔窓を形成する工程と、その後、前記ホトレ
ジストをマスクとして前記絶縁膜を方向性ドライエッチ
ングすることにより、絶縁膜に前記開孔窓に対応して開
孔部を形成する工程と、その後、ポジ型現像液によつて
、開孔窓周囲の第1のホトレジストを溶解させることに
より、ポジ型の第1のホトレジストの開孔窓を広げる工
程と、この工程による開孔窓の広がりにより露出した絶
縁膜の角部をエッチング除去することにより、前記絶縁
膜の開孔部をテーパ状に形成する工程とを具備してなる
半導体装置の製造方法。
A positive type first photoresist, a negative type second photoresist, and a positive type third photoresist are sequentially applied onto the insulating film on the semiconductor substrate, and a desired opening window is formed in the positive type third photoresist. By performing a directional etching of the photoresist after this step, the negative-tone second photoresist and the positive-tone first photoresist are made to have the same aperture window position in the positive-tone third photoresist. a step of forming an aperture window in the shape, and then forming an aperture portion in the insulating film corresponding to the aperture window by directional dry etching the insulating film using the photoresist as a mask; Thereafter, a step of widening the aperture window of the positive first photoresist by dissolving the first photoresist around the aperture window with a positive developer, and a step of widening the aperture window by this step. A method of manufacturing a semiconductor device, comprising the step of forming an opening in the insulating film into a tapered shape by etching away the exposed corner of the insulating film.
JP14058084A 1984-07-09 1984-07-09 Manufacture of semiconductor device Pending JPS6120334A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP14058084A JPS6120334A (en) 1984-07-09 1984-07-09 Manufacture of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP14058084A JPS6120334A (en) 1984-07-09 1984-07-09 Manufacture of semiconductor device

Publications (1)

Publication Number Publication Date
JPS6120334A true JPS6120334A (en) 1986-01-29

Family

ID=15271995

Family Applications (1)

Application Number Title Priority Date Filing Date
JP14058084A Pending JPS6120334A (en) 1984-07-09 1984-07-09 Manufacture of semiconductor device

Country Status (1)

Country Link
JP (1) JPS6120334A (en)

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6366939A (en) * 1986-03-11 1988-03-25 テキサス インスツルメンツ インコ−ポレイテツド Manufacture of integrated circuit
JPH024450A (en) * 1988-06-21 1990-01-09 Nippon Shokubai Kagaku Kogyo Co Ltd Catalyst regeneration process
US5722162A (en) * 1995-10-12 1998-03-03 Fujitsu Limited Fabrication procedure for a stable post
US7134943B2 (en) 2003-09-11 2006-11-14 Disco Corporation Wafer processing method
DE102004012012B4 (en) * 2003-03-11 2013-06-13 Disco Corp. Method for dividing a semiconductor wafer

Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6366939A (en) * 1986-03-11 1988-03-25 テキサス インスツルメンツ インコ−ポレイテツド Manufacture of integrated circuit
JPH024450A (en) * 1988-06-21 1990-01-09 Nippon Shokubai Kagaku Kogyo Co Ltd Catalyst regeneration process
JPH0555186B2 (en) * 1988-06-21 1993-08-16 Nippon Catalytic Chem Ind
US5722162A (en) * 1995-10-12 1998-03-03 Fujitsu Limited Fabrication procedure for a stable post
US5930890A (en) * 1995-10-12 1999-08-03 Fujitsu Limited Structure and fabrication procedure for a stable post
DE102004012012B4 (en) * 2003-03-11 2013-06-13 Disco Corp. Method for dividing a semiconductor wafer
US7134943B2 (en) 2003-09-11 2006-11-14 Disco Corporation Wafer processing method

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