JPS6119163A - Semiconductor integrated circuit - Google Patents
Semiconductor integrated circuitInfo
- Publication number
- JPS6119163A JPS6119163A JP59139862A JP13986284A JPS6119163A JP S6119163 A JPS6119163 A JP S6119163A JP 59139862 A JP59139862 A JP 59139862A JP 13986284 A JP13986284 A JP 13986284A JP S6119163 A JPS6119163 A JP S6119163A
- Authority
- JP
- Japan
- Prior art keywords
- diffusion layer
- type diffusion
- bonding pad
- type
- integrated circuit
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 12
- 238000009792 diffusion process Methods 0.000 claims abstract description 56
- 239000010410 layer Substances 0.000 abstract description 55
- 239000000758 substrate Substances 0.000 abstract description 15
- 230000001681 protective effect Effects 0.000 abstract description 12
- 150000004767 nitrides Chemical class 0.000 abstract description 6
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 abstract description 4
- 229910052782 aluminium Inorganic materials 0.000 abstract description 4
- 239000011229 interlayer Substances 0.000 abstract description 4
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 abstract 4
- 229910052681 coesite Inorganic materials 0.000 abstract 2
- 229910052906 cristobalite Inorganic materials 0.000 abstract 2
- 239000000377 silicon dioxide Substances 0.000 abstract 2
- 235000012239 silicon dioxide Nutrition 0.000 abstract 2
- 229910052682 stishovite Inorganic materials 0.000 abstract 2
- 229910052905 tridymite Inorganic materials 0.000 abstract 2
- 238000007493 shaping process Methods 0.000 abstract 1
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 3
- 229910052710 silicon Inorganic materials 0.000 description 3
- 239000010703 silicon Substances 0.000 description 3
- 238000010586 diagram Methods 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 230000010354 integration Effects 0.000 description 2
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 1
- 239000006185 dispersion Substances 0.000 description 1
- 239000000428 dust Substances 0.000 description 1
- 239000012535 impurity Substances 0.000 description 1
- 238000000034 method Methods 0.000 description 1
- 238000004806 packaging method and process Methods 0.000 description 1
- 229910052698 phosphorus Inorganic materials 0.000 description 1
- 239000011574 phosphorus Substances 0.000 description 1
- 239000011347 resin Substances 0.000 description 1
- 229920005989 resin Polymers 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/0203—Particular design considerations for integrated circuits
- H01L27/0248—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
- H01L27/0251—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices
- H01L27/0255—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices using diodes as protective elements
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
- Semiconductor Integrated Circuits (AREA)
Abstract
Description
【発明の詳細な説明】
産業上の利用分野
本発明は高集積回路に用いることができる半導体集積回
路の構造に関するものである。DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to the structure of a semiconductor integrated circuit that can be used in highly integrated circuits.
従来例の構成とその問題点 近年、半導体集積回路は高集積化の方向に進んでいる。Conventional configuration and its problems In recent years, semiconductor integrated circuits have been moving toward higher integration.
すなわち、トランジスタ素子の小形化により、集積度が
向上している。しかしながら、外部回路と接続するだめ
のボンデングパッド、および、サージ電圧対策用の保護
回路の小形化は、その特性上、トランジスタ素子に比し
て大変困難である。In other words, the degree of integration has improved due to the miniaturization of transistor elements. However, it is much more difficult to downsize bonding pads for connection with external circuits and protective circuits for surge voltage countermeasures than transistor elements due to their characteristics.
以下図面を参照しながら従来の０ＭＯ５形の半導体集積
回路について説明する。第１図は従来の０ＭＯ８形の半
導体集積回路のサージ電圧保護回路であり、第２図はそ
の断面図を示すものである。A conventional 0MO5 type semiconductor integrated circuit will be described below with reference to the drawings. FIG. 1 shows a conventional surge voltage protection circuit for an 0MO8 type semiconductor integrated circuit, and FIG. 2 shows a cross-sectional view thereof.
第１図において１は保護抵抗、２は正のサージ電圧保護
ダイオード、３は負のサージ電圧保護ダイオードである
。第２図において、１は保護抵抗（Ｐ形拡散層）、２は
正のサージ電圧保護ダイオード、３は負のサージ電圧保
護ダイオード、４はＮ形のシリコン基板、５はフィール
ド酸化膜（ＳｉＯ２）、６は層間絶縁膜（ＳｉＯ，、）
、７は保護窒化膜（Ｓｉｎ） 、 ａはボンデングパッ
ド、９はアルミ配線、１ｏはＰウェル、１１はＰ形拡散
層、１２はＮ形拡散層、１３はＮ形拡散層であり、Ｎ形
基板４よシは不純物濃度がより高濃度となっている、１
４はガートバンド（Ｎ形拡散層）、１５はガートバンド
（Ｐ形拡散層）、１６の領域はスクライブレーンである
。ここに示した例は、いわゆるＰウェル構造で、Ｈ形基
板を使うものであり、ＣＭＯ８はＰウェル構造が一般的
である。ここでＮ形基板４およびＮ形拡散層１３はＶＤ
Ｄ（最高電位、たとえば−１−ｔｓ Ｖ ）電源に接続
される。またＮ形拡散層１３はチップの有効利用を図る
ために入れてあり、このＮ形拡散層１３’１ｉＶＤＤ電
源に接続することによりチップ周辺の素子やガートバン
ドはこのＮ形拡散層１３を介してＶＤＤ電源をとること
ができる。スクライプレーン上には酸化膜や窒化膜がな
いが、これは、もしスクライブレーン上にもあると、ウ
ェハからチップに分割する時、酸化膜、窒化膜にクラッ
クが入り、それがチップ内部までおよび、耐湿等信頼性
を低下させるからである。In FIG. 1, 1 is a protection resistor, 2 is a positive surge voltage protection diode, and 3 is a negative surge voltage protection diode. In Figure 2, 1 is a protective resistor (P-type diffusion layer), 2 is a positive surge voltage protection diode, 3 is a negative surge voltage protection diode, 4 is an N-type silicon substrate, and 5 is a field oxide film (SiO2). , 6 is an interlayer insulating film (SiO,,)
, 7 is a protective nitride film (Sin), a is a bonding pad, 9 is an aluminum wiring, 1o is a P well, 11 is a P-type diffusion layer, 12 is an N-type diffusion layer, 13 is an N-type diffusion layer, The impurity concentration of the shaped substrate 4 is higher, 1
4 is a guard band (N-type diffusion layer), 15 is a guard band (P-type diffusion layer), and 16 is a scribe lane. The example shown here has a so-called P-well structure and uses an H-type substrate, and CMO8 generally has a P-well structure. Here, the N type substrate 4 and the N type diffusion layer 13 are VD
D (highest potential, e.g. -1-ts V ) power supply. In addition, the N-type diffusion layer 13 is included to make effective use of the chip, and by connecting this N-type diffusion layer 13' to the 1iVDD power supply, the elements and guard bands around the chip can be connected via this N-type diffusion layer 13. Can take VDD power supply. There is no oxide film or nitride film on the scribe plane, but if there is one on the scribe plane, the oxide film or nitride film will crack when the wafer is divided into chips, and the cracks will penetrate into the inside of the chip. This is also because reliability such as moisture resistance is reduced.
以上のような構造の集積回路では、パッケージングや実
装時において、ポンディングパッド８に接続するボンデ
ィングワイヤやフィルムキャリアインナーリードが自重
、ゴミ、保護樹脂の圧力等の機械的外力によってたれ下
りチップ端つまりＮ形拡散層１３に接触しＮ形拡散層１
３の電位すなわちＶＤＤ電位とショートしてしまうとい
う問題点を有していた。In an integrated circuit having the structure described above, during packaging and mounting, the bonding wires and film carrier inner leads connected to the bonding pads 8 may sag due to external mechanical forces such as their own weight, dust, or the pressure of the protective resin, causing the edges of the chip to sag. In other words, the N-type diffusion layer 1 is in contact with the N-type diffusion layer 13.
However, there was a problem in that a short circuit occurred with the potential of No. 3, that is, the VDD potential.
発明の目的
本発明の目的はボンディングワイヤやフィルムキャリア
インナーリードがチップ端と接触しても基板の電位とシ
ョートしない半導体集積回路を提供するものである。OBJECTS OF THE INVENTION An object of the present invention is to provide a semiconductor integrated circuit that does not short-circuit with the potential of the substrate even if bonding wires or film carrier inner leads come into contact with chip ends.
発明の構成
本発明の半導体集積回路は、スクライブレーンからポン
ディングパッドの間において、Ｎ形拡散層の上にＰ形拡
散層を形成し前記Ｐ形拡散層の上にボンデングパッドを
接続されるごとく形成したことにより、ボンデングワイ
ヤやフィルムキャリアインナーリードがチップ端に接触
しても基板電位とショートしなくなるものである。Structure of the Invention In the semiconductor integrated circuit of the present invention, a P-type diffusion layer is formed on the N-type diffusion layer between the scribe lane and the bonding pad, and a bonding pad is connected on the P-type diffusion layer. By forming the bonding wire as shown in FIG.
実施例の説明
以下本発明の一実施例について、図面を参照しながら説
明する。DESCRIPTION OF EMBODIMENTS An embodiment of the present invention will be described below with reference to the drawings.
第３図は本発明の一実施例における半導体集積回路のサ
ージ電圧保護回路であり、第４図はその断面図を示すも
のである。第３図において１は保護抵抗、３は負のサー
ジ電圧保護ダイオード、１７は正のサージ電圧保護ダイ
オードである。第４図において１は保護抵抗（Ｐ形拡散
層）、３は負のサージ電圧保護回路、４はＮ形基板、５
はフィールド酸化膜（Ｓｉｎ２）、６は層間絶縁酸化膜
（Ｓｉｎ２）、７は保護窒化膜（５ｉＮ）、８はポンデ
ィングパッド、９はアルミ配線、１ｏｔ／′ｉＰウエル
、１２ｉｄＮ形拡散層、１３はＮ形拡散層、１６はガー
トバンド（Ｐ形拡散層）、１６の領域はスクライブレー
ン、１７は正のサージ電圧保護ダイオードである。Ｐ形
波散層１３は通常リン（Ｐ）をＮ形シリコン基板にドー
ピングして形成されるが、それぞれの拡散深さ、および
ひろがりはプロセス条件でコントロールできるので第４
図のようにＮ形基板４．Ｐ形拡散層１８．Ｎ形拡散層１
３の三層構造を作ることができる。ここでＨ形基板４お
よびＮ形拡散層１３は従来例同様にＶＤＤ電源に接続さ
れる。このＮ形拡散層１３は従来例のＮ形拡散層１３と
同じ役割をするものである。ただし、従来例のＲ形波散
層１３の機能が必要なければ、このＮ形拡散層はなくて
もかまわない。またＰ形拡散層１８には何も接続せずに
フローティングにしておく。FIG. 3 shows a surge voltage protection circuit for a semiconductor integrated circuit according to an embodiment of the present invention, and FIG. 4 shows a cross-sectional view thereof. In FIG. 3, 1 is a protection resistor, 3 is a negative surge voltage protection diode, and 17 is a positive surge voltage protection diode. In Figure 4, 1 is a protective resistor (P-type diffusion layer), 3 is a negative surge voltage protection circuit, 4 is an N-type substrate, and 5
is a field oxide film (Sin2), 6 is an interlayer insulating oxide film (Sin2), 7 is a protective nitride film (5iN), 8 is a bonding pad, 9 is an aluminum wiring, 1ot/'iP well, 12id N type diffusion layer, 13 is an N-type diffusion layer, 16 is a guard band (P-type diffusion layer), 16 is a scribe lane, and 17 is a positive surge voltage protection diode. The P-type wave dispersion layer 13 is usually formed by doping an N-type silicon substrate with phosphorus (P), but since the depth and spread of each diffusion can be controlled by process conditions,
As shown in the figure, N type board 4. P-type diffusion layer 18. N type diffusion layer 1
A three-layer structure can be created. Here, the H type substrate 4 and the N type diffusion layer 13 are connected to the VDD power supply as in the conventional example. This N type diffusion layer 13 plays the same role as the N type diffusion layer 13 of the conventional example. However, if the function of the conventional R-type diffusion layer 13 is not required, this N-type diffusion layer may be omitted. Further, the P-type diffusion layer 18 is left floating without being connected to anything.
以上のように構成された本実施例の半導体集積回路のポ
ンディングパッド８に接続するボンディングワイヤやフ
ィルムキャリアインナーリードが何らかの原因でチップ
端に接触したとしてもＮ形拡散層１３との間にはＰ形拡
散層１８があり、ＶＤＤ電源とショートすることはない
。Even if the bonding wire or film carrier inner lead connected to the bonding pad 8 of the semiconductor integrated circuit of this embodiment configured as described above comes into contact with the chip end for some reason, there will be no contact between the bonding wire and the N-type diffusion layer 13. There is a P-type diffusion layer 18, so there will be no short circuit with the VDD power supply.
以上のように本実施例によればＮ形拡散層およびＰ形拡
散層の２層構造を形成したことにより、ポンディングパ
ッドと基板のＶＤＤ電位とショートするのを防いでいる
。As described above, according to this embodiment, by forming the two-layer structure of the N-type diffusion layer and the P-type diffusion layer, short-circuiting between the bonding pad and the VDD potential of the substrate is prevented.
発明の効果
以上の説明から明らかなように、本発明はスクライブレ
ーンからポンディングパッドの間においてＮ形拡散層の
上にＰ形拡散層を形成しているので、ポンディングパッ
ドやフィルムキャリアインナーリードがチップ端に接触
しても基板の電位とショートすることはないという優れ
た効果が得られる。さらに、ポンディングパッドがＰ形
拡散層と接続されているのでサージ電圧が加わっても、
ＰＮ接合によって基板に吸収され、別にサージ電圧対策
用の保護回路を造る必要がなく、チップが小さくなると
いう効果が得られる。Effects of the Invention As is clear from the above explanation, the present invention forms a P-type diffusion layer on an N-type diffusion layer between the scribe lane and the bonding pad. An excellent effect can be obtained in that even if the electrode comes into contact with the chip end, there will be no short circuit with the potential of the substrate. Furthermore, since the bonding pad is connected to the P-type diffusion layer, even if a surge voltage is applied,
It is absorbed by the substrate through the PN junction, and there is no need to create a separate protection circuit to counter surge voltage, resulting in a smaller chip.
第１図は従来の集積回路のサージ電圧保護回路の回路図
、第２図は従来の集積回路のボンディンダパッド部分と
サージ電圧保護回路部の断面図、第３図は本発明の一実
施例における集積回路のサージ電圧保護回路の回路図、
第４図は本発明の一実施例における集積回路のパッド部
分とサージ電圧保護回路部の断面図である。
１・・・・・・保護抵抗（Ｐ形拡散層）、２・・・・・
・正のサージ電圧保護ダイオード、３・・・・・・負の
サージ電圧保護ダイオード、４・・・・・・Ｎ形シリコ
ン基板、６・・・・・・フィールド酸化膜、６・・・・
・・層間絶縁膜、７・・・・・パ 保護窒化膜、８・・
・・・・ポンディングパッド、９・・・・・・アルミ配
線、１０・・・・・・Ｐウェル、１１・・・・・・Ｐ形
拡散層、１２・・・・・・Ｎ形拡散層、１３・・・・・
・Ｎ形拡散層、１４・・・・・・ガートバンド（Ｎ形拡
散層）、１５・旧・・ガートバンド（Ｐ形拡散層）、１
６・旧・・スクライブレーン、１γ・・・・・・本発明
の正のサージ電圧保護回路、１８・・・・・・本発明の
Ｐ形拡散層。Fig. 1 is a circuit diagram of a conventional integrated circuit surge voltage protection circuit, Fig. 2 is a sectional view of a bonder pad portion and surge voltage protection circuit portion of a conventional integrated circuit, and Fig. 3 is an embodiment of the present invention. Circuit diagram of integrated circuit surge voltage protection circuit in
FIG. 4 is a sectional view of a pad portion and a surge voltage protection circuit portion of an integrated circuit in one embodiment of the present invention. 1...Protective resistance (P-type diffusion layer), 2...
・Positive surge voltage protection diode, 3...Negative surge voltage protection diode, 4...N-type silicon substrate, 6...Field oxide film, 6...
...Interlayer insulating film, 7...Paper protective nitride film, 8...
...Ponding pad, 9...Aluminum wiring, 10...P well, 11...P type diffusion layer, 12...N type diffusion Layer, 13...
・N-type diffusion layer, 14... Guard band (N-type diffusion layer), 15. Old... Guard band (P-type diffusion layer), 1
6. Old... Scribe lane, 1γ... Positive surge voltage protection circuit of the present invention, 18... P-type diffusion layer of the present invention.
Claims (1)
Ｎ形拡散層の上にＰ形拡散層を形成し、前記Ｐ形拡散層
の上にボンデングパッドを接続されるごとく形成するこ
とを特徴とする半導体集積回路。Between the scribe lane and the bonding pad,
A semiconductor integrated circuit characterized in that a P-type diffusion layer is formed on an N-type diffusion layer, and a bonding pad is formed on the P-type diffusion layer so as to be connected thereto.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP59139862A JPS6119163A (en) | 1984-07-05 | 1984-07-05 | Semiconductor integrated circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP59139862A JPS6119163A (en) | 1984-07-05 | 1984-07-05 | Semiconductor integrated circuit |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS6119163A true JPS6119163A (en) | 1986-01-28 |
Family
ID=15255270
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP59139862A Pending JPS6119163A (en) | 1984-07-05 | 1984-07-05 | Semiconductor integrated circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6119163A (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0391264A (en) * | 1989-09-01 | 1991-04-16 | Toshiba Micro Electron Kk | Semiconductor device equipped with input protective circuit |
| US5148249A (en) * | 1988-04-14 | 1992-09-15 | Kabushiki Kaisha Toshiba | Semiconductor protection device |
| US7233466B2 (en) | 2002-08-02 | 2007-06-19 | Nec Electronics Corporation | Input protection circuit |
-
1984
- 1984-07-05 JP JP59139862A patent/JPS6119163A/en active Pending
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5148249A (en) * | 1988-04-14 | 1992-09-15 | Kabushiki Kaisha Toshiba | Semiconductor protection device |
| JPH0391264A (en) * | 1989-09-01 | 1991-04-16 | Toshiba Micro Electron Kk | Semiconductor device equipped with input protective circuit |
| US7233466B2 (en) | 2002-08-02 | 2007-06-19 | Nec Electronics Corporation | Input protection circuit |
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