JPS61198865A - Picture image communication equipment - Google Patents

Abstract

PURPOSE:To attain compensation retransmission efficiently even with a delay of a line by providing a means storing prescribed amount of line information sent already so as to attain retransmission of missing picture image from the corresponding line information even when a transmission error takes place. CONSTITUTION:A network control section (NCU) 87 connects a telephone network to a terminal device of the line to use it for data communication to apply connection control of the telephone exchange network, switches data communication line to holds the loop. A transmission signal on a signal line 71a is sent to a telephone line 67a via a signal line 67a and a network control section 67 from a hybrid circuit 88 separating the signal of the transmission and reception system. Further, a signal sent from the opposite facsimile equipment is sent to the signal line 68a via the network control section 67. A binary signal sending circuit 89 inputs a data on the signal line 76a when a pulse is generated on the signal line 76b and outputs a data subject to V21 modulation to the signal line 69a.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field] The present invention relates to an image communication device that divides image information into multiple line information and transmits the divided information.

More specifically, the present invention relates to an image communication device configured to efficiently perform retransmission correction of image information.

(Hereinafter, in the margins) [Prior Art] A facsimile machine will be taken up as an example of this type of image communication device, and the prior art will be specifically explained according to the items shown below.

61) Explanation of IIILC frame structure (Using Figure 1) 92) Specific example of error retransmission using IDLG frame structure (Using Figure 2) ISA Problems caused by error retransmission using HDLC frame structure 3 , 1 Influence on line errors 93.2 Influence of bit position where error occurs (3rd
93.3 Effects based on the propagation delay characteristics of communication lines (see Figure 4) 3.4 Difficulty in encoding 94 Disadvantages of conventionally known error retransmission methods 94.1 Fall pack Regarding! 34.2 Processing when training signal reception fails (see Figures 5 to 7) 94.3 Processing when EOL cannot be detected 94.4 Processing when image signal transmission is completed 94 .5 Regarding processing after sending instruction signals such as retransmission start line 94.6 Regarding selection of error retransmission mode Winter I HD
Explanation of LC Frame Structure When data is transmitted via a communication line such as a telephone line, there is a certain probability that errors will occur in the data due to the effects of momentary interruptions, noise, distortion, etc. in the two communication lines. In order to detect errors in this data, predetermined calculations and the like are performed on the received data to determine whether certain rules are maintained. If an error is detected, a method is adopted in which the information data group containing the error data is sent out again according to a predetermined transmission control procedure.

This automatic retransmission request method (ARQ)
repeat request) is a method used when performing half-duplex transmission using telephone lines, etc., and is a method used when performing half-duplex transmission using a telephone line etc.
1 level data 1 ink control p
rocedure). )101.
C means a data terminal device (D
TE) It is a bit-transparent synchronous transmission control procedure that enables highly efficient data transmission between each other and can transmit any bit string without depending on any coding system.

In the HDLC procedure, arbitrary bit string information and link control information are transmitted using a frame, which is a transfer unit. The start and end of a frame are flag sequences (01
111110).

FIG. 1 shows the frame format of the HDLG procedure. The flag sequence shown in FIG. 6 is a signal for frame synchronization, and frame synchronization is achieved by transmitting and receiving one or more flag sequences. Also, if the same bit string as the flag sequence appears in the information transferred in a frame,
The receiving side considers this to be the end of the frame. To prevent this, if a pattern of 5 consecutive bits "1" appears in the frame information, the transmitting side considers it as the end of the frame.
A method in which one bit "0" is forcibly inserted and transmitted, and the receiving side removes one bit "0" received following a pattern of five consecutive bits "1" (zero bit insertion method)
is used to ensure transparency of transferred data.

The address field contains the address assigned to the station transmitting and receiving the frame in binary code (for example, 11111
111), which has the address of the station that receives the frame, is a command frame, and the frame that has the address of the station that transmits the frame is a response frame.

If the frame is a command, the control field indicates an instruction to the other station, and if the frame is a response, it indicates a response to the instruction of the command frame.

Frame check sequence (Fe2: framech
Ecking 5 sequence) is an 18-bit sequence for detecting frame transmission errors, and indicates the result of the operation using the generator polynomial XI6+X+X5+1.The object of the operation is from the beginning of the address field to the end of the information field of the frame.

The length of the information field is arbitrary (eg, 512 bytes or 512 x 8 bits).

62 H[lI, Specific Example of Error Retransmission Using IC Frame Structure FIG. 2 shows a specific example of error retransmission using the HDLC frame data shown in FIG.

That is, when the receiving side receives a certain frame, if no error has occurred, it sends out an ACKg signal, and if an error has occurred, it sends out a NACK signal.

On the other hand, on the transmitting side, in response to the ACK signal detected during frame N transmission, frame N+1 is transmitted after frame N is transmitted.

On the other hand, if a NACK signal is detected while transmitting a certain frame N, or if an ACK signal cannot be detected, frame N-1 is retransmitted after transmitting frame N, and for the same frame, When a NACK signal is detected a predetermined number of times or more, or when no signal is detected on the AC.

Control is performed to perform fallback.

In this way, when framed data is sent from the transmitting side and received by the receiving side, no error occurs on the receiving side regarding frame N, but an error occurs when receiving frame N+1, as shown in Figure 2. If this occurs, the following primary control is performed. That is, the receiving side sends an ACK signal after receiving frame N, and
After receiving +1, it sends out a NACK signal.

On the other hand, on the transmitting side, A
Since the CK signal will be received, frame N+2 will be sent after frame N+1 is sent.Furthermore, the sending side will receive the NACK signal while frame N+2 is being sent, so it will be sent again after frame N+2 is sent. Frame N+1 is sent.

After transmitting the NACK signal for frame N+1, the receiving side transmits a signal to AC after receiving frame N+2, regardless of whether an error occurs in frame N+2. Thus, the receiving side enters a state of waiting for reception of frame N+1. Then, if no error occurs in retransmitted frame N+1 that is sent following frame N+2, the receiving side performs AC control after receiving retransmitted frame N+1.
Send K signal.

On the other hand, the transmitting side receives ACK while sending retransmission frame N+1.
Since the signal will be received, frame N+2 is transmitted again after retransmission frame N+1 is transmitted, and in response to the ^CK@ signal received while frame N+2 is being transmitted, frame N+3 is transmitted after frame N+2 is transmitted. is sent.

Problems caused by performing error retransmission using 16OHDLC frames Since image communication devices using the conventionally known retransmission correction method ARQ adopt the HDLC frame structure as described above, they mainly suffer from the following problems. There was a point.

93.1 Effects on Line Errors Since signals to be transmitted are divided into blocks using HDLC frames, on the receiving side, there is a possibility that either a) no errors have occurred in that block, or 1) one bit or more. It can be determined whether an error has occurred.

Therefore, on the receiving side, it is possible to reproduce a good image without even a single bit error.

However, when a reception error occurs for a certain block, it is not possible to determine the extent of the error. (In other words, it is not possible to specify any of the bits from the 1st bit to the Xth bit (x varies depending on the block size and image information)).

Therefore, in situations where the line conditions are good, such as in Japan, HDL
Although it is effective to block signals using C frames (that is, if the line conditions are good, it is possible for the receiver to reproduce an image without even a single bit error).
If the line condition is poor, there is a high probability that several bits included in the HDLC frame will result in a reception error. For this reason, there was a drawback that the number of retransmissions increased.

93.2 Regarding the influence of the bit position where an error occurs Since the signal to be transmitted is divided into blocks using HDLC frames, it is necessary to retransmit from the beginning of the block even if an error occurs at any bit position of the block. For example, as shown in FIG. 3, even if an error occurs in the data in the part (a), it is necessary to retransmit the data from the beginning of the block, that is, the data in (b). For this reason, there is a drawback that transmission efficiency cannot be improved.

93.3 Effects Based on Propagation Delay Characteristics of Communication Lines On the transmitting side, during the transmission period of a certain frame N, it is determined whether or not the previously transmitted frame N-1 was correctly received by the receiving side. However, even in this case, due to the delay time inherent in the line.

A situation may occur in which the AGK signal cannot be received. A specific example will be explained with reference to FIG. Now, assuming that the time required to transmit one block of data is Tf, and the delay time that occurs when transmitting a signal from the transmitting side to the receiving side is Td, it is necessary that Tf>2Td. in this way,
There is a drawback that the allowable delay time on the line is determined according to the block size. Therefore, in order to allow a longer delay time on one line, a method of increasing the block size can be considered. However, when the block size is increased, the drawbacks mentioned in the above-mentioned section "r93.2 Regarding the influence of the bit position where an error occurs" become more apparent.

53.4 Difficulty in encoding A drawback was that the new design required additional time to create the encoding.

I: I4 Disadvantages of conventionally known error retransmission methods 64
．． 1 Regarding Fall Pack In the conventional error retransmission system, a retransmission request is made when a reception error occurs in the receiving side device. Furthermore, when a certain document is being transmitted and an erroneous retransmission is performed a certain number of times (for example, three times) or more, a fall pack (reducing the transmission speed) is performed.

Therefore, even if there is no change in the state (characteristics) of the line and reception is possible at a predetermined transmission speed (for example, 4800 bits/5ea), if impulse noise is superimposed on the line (for example, one If impulse noise occurs three times while transmitting the original document, the system will fall back.

Similarly, if reception is not possible at the specified transmission speed even though one line is in a steady state, erroneous retransmissions occur three times in a row.
A fallback occurs when this occurs twice.

In the latter case described above, fall packing is meaningful because there is a possibility of eliminating reception errors. However, in the former case, even if fall pack is performed, an error will occur again on the receiving side due to impulsive noise. Therefore, it is wasteful to perform a fall pack in the former case.

As described above, the conventional error retransmission system has the disadvantage that wasteful fall packs are performed, which unnecessarily lengthens the transmission time.

fi4.2) Processing when training signal reception fails In conventionally known image communication systems, when training signal reception fails, an error immediately occurs on the receiving side, and on the other hand, one image is sent on the transmitting side. The configuration was such that an error would occur after the transmission of the original was completed. In this way, even though image transmission is not being performed, the line remains occupied until the transmission of one original document is completed, resulting in a major drawback in that charges are wasted.

FIG. 5 shows an example of the operation when the receiving device fails to receive the training signal in the conventional error retransmission method.

Here, NSF is a non-standard device.

CSI is called station identification; 1] tS is a digital identification signal, NSS is a non-standard device setting, TSI is transmitting terminal identification, DOS is a digital command signal, TCF is training check, CFR confirms reception preparation, EOP has completed the procedure, DON is a disconnection order, (C: see CITT Recommendation T, 30).

The waveform diagrams shown in FIGS. 8(1) to 8(3) show the state when the receiving side device receives the training signal and succeeds in receiving the training signal.

In this figure, (1) indicates a signal on the line. This figure (B) shows the presence or absence of a signal on one line (SED: Signal Energy Detect).
), and exhibits a high level when a signal presence state is detected. This figure (C) shows the carrier detection (CD) that indicates whether or not valid data transmitted at a predetermined transmission speed is detected.When valid data is detected at a predetermined transmission speed, , exhibiting a high level.

As is clear from these Figures 8 (1) to (3), the SED
is at a high level and CD is at a low level (during the period when
) , ) This means that the laning signal is being received (Trml158mS at 2400bit/S)
.

Tr=923m5 at 4800bit/S).

The flowchart shown in FIG. 7 shows a control procedure for receiving a training signal/image signal in a conventional apparatus.

Here, step 5too represents the reception of the training signal/image signal.

In step 91002, a timer T2 for determining that the reception of the training signal has failed is set to 10 seconds.

In step 5IO04, 5ED is executed continuously for 20 milliseconds while determining whether T2 times out or not.
-1 or not. At this time, if the timer T2 times out, the process proceeds to step 51012, and if SE[+-1 continues for 20 milliseconds (that is, when the beginning of the training signal is received), the process proceeds to step 5100B.

In step 5iooe, the timer 〒2 times out for a milliseconds (2400b
It is determined whether or not C0-0 is maintained continuously for 700 milliseconds in the case of /S and 500 milliseconds in the case of 4800b/S. At this time, when the timer T2 times out, the process proceeds to step 51012, and when the CD-0 is continuously for a milliseconds (that is, when the training signal is received), the process proceeds to step 5tooa.

In step 8100B, it is determined whether co-i continues for 20 milliseconds while determining whether timer T2 times out. At this time, if the timer T2 times out, the process proceeds to step 51012. Also, if CD=1 for 20 milliseconds continuously (
That is, when the beginning of the image signal is received), the process proceeds to step 5IOIO.

Step 5IOIO represents receiving the image signal.

Step 51012 represents a reception error.

As shown in Fig. 7, when the training signal reception fails (i.e., when the SED and CD do not operate correctly), it takes about 10 seconds after entering the training signal/image signal reception mode. A drawback was that the process ended with an error.

64.3 Processing when EOL cannot be detected In conventional facsimile machines, when the training signal is successfully received and the image signal reception mode is entered, if the EOL (End of Line) signal cannot be received for 5 seconds or more, , it was immediately marked as an error. This also applies when error retransmission mode is used.

In this way, if the demodulated data is not correctly demodulated even though the training signal has been successfully received, it is immediately recognized as an error, so there is a drawback that error retransmissions are not effectively utilized.

94.4 Processing when transmission of image signals is completed In conventional facsimile machines, when transmission of image signals is completed, a procedure signal is immediately transmitted, so if the receiving device makes an error in the last block, an error occurs. The drawback was that retransmission was not possible.

64.5 Processing after sending an instruction signal such as a retransmission start line In conventional facsimile machines, when the receiving side detects an error, it sends a NACK signal, and then sends an instruction signal such as a retransmission start line. Next, the receiving device was on its way to receive the image signal sent from the transmitting device (that is, the image signal from the designated retransmission phase start line).

However, if the transmitting side cannot correctly receive an instruction signal such as a retransmission start line sent from the receiving side, an error may occur.

64.8 Regarding the selection of the error retransmission mode, in general, the error retransmission mode has the advantage of being able to reliably transmit image information, but it also takes more time than normal transmission when there are no errors. There is the inconvenience of putting it away. Therefore, it is desirable to leave it to the operator's choice whether or not to perform transmission in error retransmission mode.

However, conventional facsimile machines have a drawback in that the error retransmission mode cannot be arbitrarily selected by the operator.

(Hereinafter, blank space) [Object] In view of the above-mentioned points, a first object of the present invention is to provide an image communication device configured to efficiently and accurately retransmit error image data. be.

A second object of the present invention is to provide a configuration in which a part of the transmitted data is stored on the transmitting side in order to solve problems caused by image transmission according to the HDLC frame format. An object of the present invention is to provide an image communication device that achieves the following.

In order to achieve such an object, the present invention provides an image communication device that divides image information into a plurality of line information and transmits the information, and includes a means for storing a predetermined amount of the line information that has already been sent out. The device is configured to retransmit the already transmitted line information in response to a retransmission request obtained from the other party's device.

〔Example〕

A facsimile machine will be described as an example to which the present invention is applied.

First, an outline of this embodiment will be described.

(i) When transmitting image information (on the transmitting side), an encoded line number is attached to each line and transmitted together with the image information. Then, subsequent data can be retransmitted starting from the code corresponding to a certain line number.

On the receiver side, the line number is checked while image information is being received, thereby determining whether there is a reception error. When the data is received correctly, the line number is removed and the data is decoded.On the other hand, when the receiver side recognizes that a reception error has occurred, the receiving side device sends a control signal and displays the image of the sending side device. Interrupt information transmission. Thereafter, the receiving device notifies the transmitting device of the retransmission request start line number. As a result, the transmitting device resumes transmission from the retransmission request starting line number.

(ii) When transmitting image information, the line number inserted for each line has the following characteristics.

B) What is the line number? Increments each line.

The line number is a signal that indicates the end of the code on one line, such as "EOL" (End of Line).
:CO! (Used when Modified Huffman encoding or Modified Read encoding is performed based on Recommendation T4). This allows the receiving device to distinguish between the one-stroke information and the line number.

C) The length of the line number is constant.

Therefore, a line number representing a small number and a line number representing a large number have the same code length.

Thereby, the receiving device can recognize that a predetermined byte of the signal representing the end of one line of code is a line number. In this way, the image information and line number can be easily identified on the receiving side.

2) Line numbers are signals with special meanings, e.g.
A signal representing the end of a line and a signal having a different code structure. Therefore, when an error occurs on the receiving side, it is possible to search again for a signal with special meaning (representing the end of the l line) and establish line synchronization in response to the detection of this signal.

The facsimile apparatus according to this embodiment will be described in detail below in accordance with the following items.

91 Example of error retransmission procedure (used in Figure 8) 92 Explanation of line numbers (used in Figure 8) g3 Specific example of storing encoded data in FIFO memory (used in Figure 10) ii4 FIFO memory and FIFO memory Description of the pointer that controls the FJ5 Configuration for selecting the error retransmission mode from the transmitting device (used in FIGS. 11 and 12) 96 Management of FIFO memory in the transmitting device (FIGS. 13 to 15)
(Figure used) Cloud 7 Validity of memory capacity for storing retransmission start address 9th Control after all image information has been sent from the sending device 69 Conditions for making a retransmission request from the receiving device and conditions for making a fall pack request (No. (Use Figure 16) 61ONSF signal structure 1 (Use Figure 17) fill
The operation of the transmitting device when receiving the NACK signal (
18th rl! i) 912 Explanation of the block diagram of the transmitting device (using Figures 19 and 20) 1i) 13 Schematic explanation of the operation of the control circuit in the transmitting device (using Figure 21) 14 Description of the control circuit in the transmitting device Detailed operation explanation (using Figures 22 and 23)! S15 Block configuration of receiving side device (Used in Figure 24)
fill Explanation of the operation of the control circuit in the receiving side device (using Figures 25 and 28) 917 Other examples (hereinafter, blank space) 91 Example of error retransmission procedure (using Figure 8) Image transmission in error retransmission mode (i.e., the start button is pressed continuously for 2.5 seconds or more on the sending device, or the error retransmission mode is selected by a switch, etc. on the sending device) ) will be explained with reference to FIG.

In FIG. 8, a case is considered in which impulse noise occurs once while image information is being transmitted, and as a result, errors occur in three or more lines in the receiving device. When such an error occurs, the receiving device issues a NACK.
signal (PIS signal in this example; Procedure
Interrupt Signal (procedure interrupt signal) is sent. By detecting this PIS signal, the transmitting side device interrupts the transmission of image information.

The receiving device transmits information such as retransmission start line/fall pack to the transmitting device following the PIS signal.
In this embodiment, which uses a V21 modulated NSF signal, the NS
The F signal notifies the sending device of the last correctly received line number.

Based on such a signal, the transmitting side device retransmits the image information from the line next to the line specified by the receiving side.

Perform a fall pack if instructed to do so.
In addition, if fall pack cannot be performed beyond the current time (i.e., if image transmission is currently being performed at 2400 b/s and error retransmission is performed three times), the process will end with an error and one line will be disconnected (DON). shall be.

Note that the abbreviations such as N5F10SI/DIS shown in FIG. 8 are as described above with respect to FIG.

92 Explanation of Line Number (Using Figure 888) FIG. 9 is a bit configuration diagram showing a specific example of a line number.

This line number is inserted after the EOL (end of line code).

Note that in this embodiment, a modified Huffman code is used as the encoding method.

The line number is the 2 bytes (16 bits) following the line termination code EOL, and the line number can be distinguished from the EOL signal.

High byte LSB (Leas) in line number
tSignificant Bit) and the LSB of the low byte of the line number are each fixed to l. If the number of bits in one line is not 1728 bits when decoded by the receiving device (when receiving A4 size), the EOL search is executed again and line synchronization is established. For this reason, the line number needs to be a different signal from EOL.

For example, line number 〇 is 01H (line number high byte), OIH (line number low byte),
Line number l is 01H (line number high byte) 03H (line number low byte), line number 2 is 011 (line number high byte))
05H (line number low byte), line number 3 is OIH (line number high byte)) 07)!
(Low bite of line number), line number 10
is OIH (line number high/<a)) 15H (line number low byte), line number 100
is OIH (high byte of line number) and C9H (low byte of line number). These line numbers are specified to be incremented every three lines.

93 Specific example of storing encoded data in FIFO memory (Using Figure 1O) Figure 10 illustrates a state in which encoded data and retransmission start addresses corresponding to each line number are stored in memory. In a certain 0 diagram, TFIFS is
Consider, for example, 8400B to AFFFH as a memory area for storing encoded data in the transmitting device, which is the start address of the memory for storing encoded data (8400H in this embodiment). In addition, as a memory area for storing the retransmission start address, for example,
Consider from oon to C3FFH.

Now, as the conditions for the sending device, the minimum transmission time when one line is completely white is 10 seconds, the minimum transmission time when one line is black is 20 m See, and the transmission speed is 4 seconds.
A4 size original (all white) when set to 800b/S
The procedure for transmitting the data will be explained based on FIG. At this time, the minimum number of bytes for the ■ line is six. Furthermore, when transmitting the byte data stored in the memory, it is assumed that the LSB is transmitted first.

For example, when transmitting data at address 8401H, first 7 bits of 0 information are transmitted, and then 1 information is transmitted.

In FIG. 10, EOL is formed by data stored at addresses 8400H and 8401H (1
1 information is sent after 5 consecutive O information).

Address 84021 (high byte data of the line number is stored, and low byte data of the line number is stored in address 8403H. Address 8402)! .

The data stored in 8403H is OIH, OIH
and represents line number 〇.

Addresses 8404H to 8408)1 contain 172
When 8 bits are completely white, modified Huffman encoded data is stored. That is, 172
Modified Huffman encoded data with 8-bit margin is 010011011001101
0f (when the data is sent to the line in order starting from the left side), where 010011011 is the make-up code when the length is 1728 bits, and 00110101 is the terminal code when the length is O bits white run length. It is a lighting code. When the modified Huffman encoded data with this 1728-bit margin is stored in memory.

B2O, 59H, OIH.

When data is sent to the line, data from 82H LSB to MSH data, 59H LSH data to M
SH data, OIH LSH data, and then MSH data are sent out in this order. That is, 01001101
Data is sent to the line in the order of (B2O data) 10011010 (5θH data) 10000000 (OIH data) (when data is sent to the line sequentially starting from the left side). Thereafter, similarly, the encoded data is stored in the memory of the sending device.

On the other hand, a retransmission start address is stored in memory in correspondence with each line number. The memory area in which the retransmission start address is stored is from address COOOH to address 03FFH. The start address of the memory area where the retransmission start address is stored is called LINO. Two bytes of memory area are required to specify one retransmission start address. Since the memory area from address COOOH to address 03FF)I is 1024 bytes, it is possible to store 512 retransmission start addresses. In addition, as mentioned above, the line number is incremented for each line, so when the line number changes (that is, it is incremented by 1), the encoded Stores the start address of the line number of the memory where data is stored. A specific example thereof is shown in FIG.

Address GOOOH, COG IH has OOH, 84
H is stored. The data stored at address C000H is the low data at the retransmission start address of line number 0, and the data stored at address 0001H is the high data at the retransmission start address of line number 0. The start address (with respect to the memory where encoded data is stored) is 8400H.

Also, addresses COO2H and COO3H are 071 and 8.
4H is stored. The data stored at address C002H is the low data at the retransmission start address of line number l, and the data stored at address C003H is the high data at the retransmission start address of line number 1. The start address (with respect to the memory where encoded data is stored) is 8407m (hereinafter similarly,
Line number 2゜Line number 3. The starting address where line number 4 is stored (with respect to the memory where encoded data is stored) is 840E)1.
8415) 1°841CH.

Furthermore, as described above, since the memory area for storing retransmission start addresses is 1024/<ite, 512 retransmission start line numbers can be stored. The 513th line number is stored in LINO (address COOOH). In this way, 512 past line numbers are stored.

64 Description of FIFO memory and pointer controlling FIFO memory In the transmitting side device, data encoded according to this embodiment is stored in FIFO (First-In First-O
ut) stored in memory. The capacity of the FIFO memory is as described above (from 8400H to AFFF)I.

Here, the starting address of the FIFO memory of the sending device is TFIFS (8400H in this embodiment), and the high byte at the starting address of the FIFO memory of the sending device is TFIFSH (T
RI FIFO5TART) IIGH; 84H in this embodiment), the final address in the FIFO memory of the sending device is TFIFE (TRI FIFOEND;
In this embodiment, AFFF)I), FI of the sending device
The high byte at the final address of FO memory is TFI
FEH (TRNFIFOEND HIC)

In the sending device, the data read by the reading means is encoded and then stored in the FIFO memory of the sending device, and a pointer is used to control the FIFO memory. The pointer used for this is TNHPTR(TR)l MHPOINTER)
The data stored in the FIFO memory on the transmitter side is modulated by a modulator and then sequentially transmitted to one line, but a pointer is also required here to control the FIFO memory. The pointer used for this is D)IDPTR(TRNMO[]EM POINTER
).

On the other hand, the receiving device stores the data sent from the transmitting device in its memory. This memory, like the sending device, is a FIFO (First-In First
-Out) memory. The FIFO memory capacity of the receiving device is the same as that of the transmitting device, ranging from 840QH to AFF.
Up to FH.

Here, the starting address in the FIFO memory of the receiving device is RFIFS (RECFIFO5TART; in this example, 8400H), and the high byte of the starting address in the FIFO memory of the receiving device is RFIFS) I
(RECFIFO5TART old GH; 84H in this embodiment), the final address in the FIFO memory of the receiving device is RFIFE (RECFIFOEND: AFFFH in this embodiment), the FIFO of the receiving device
The /\ibyte of the final address in O memory is RFI
It is called FE)I (RECFIFOEMD HIGH; in this embodiment, AF)I).

In the receiving device, the data sent from the transmitting device is restored by a demodulator, and then stored in a FIFO memory. A pointer is used when storing demodulated data in the FIFO memory, but this pointer is
It is called PTR (RECMODEM POINTER).
Data stored in FIFO memory is sequentially read, decoded, and recorded.A pointer is also used when sequentially reading and decoding data stored in FIFO memory. (R
ECMI POINTER).

95 Configuration for Selecting Error Retransmission Mode from Sending Device (Used in FIGS. 11 and 12) Two methods are used to select the error retransmission mode from the sending device. The first method is to select an error retransmission mode using a switch or the like. That is, it is assumed that the error retransmission mode is selected when a certain specific switch is in the on state.

A second way to select the error retransmission mode is to press the start button on the sending device successively. That is, the error retransmission mode is selected by continuously pressing the start button for 2.5 seconds or more, and the operator knows that the error retransmission mode has been selected by the generation of a "beep" sound.

Also, if you press the start button on the sending device for more than 5 seconds continuously, G2 mode will be selected and the
The operator is informed by the beeping sound that G2 mode has been selected.

In this embodiment, image transmission in the error retransmission mode is performed at a transmission speed of 4800b/s. Therefore, when the error retransmission mode is selected by the transmitting device, the receiving device is equipped with the error retransmission mode function. If so, transmission is performed in error retransmission mode. However, if the receiving device does not have an error retransmission mode function,
Change the transmission speed to 9[4800b/s instead of 100b/s]
Set it to S and start transmission.

FIG. 11 is a block diagram showing the configuration of the sending side of the facsimile machine according to this embodiment. In this figure, 87
is the network control unit (NGIJ), and in order to use the telephone network for data communication, etc., it connects to the terminal of the line and controls the connection of the telephone exchange network, switches to the data communication path, and controls the loop. 87a is a telephone line.

G8 is a hybrid circuit that separates transmission system signals and reception system signals. Signal line? The transmitted signal on la is signal line 6? b and the telephone line 87 via the network control 1 section 67.
sent to a. Further, the signal sent from the other party's facsimile device is sent via the network control unit 87 to the signal line Ha.
will be sent to.

88 is a binary signal sending circuit, and the signal line? signal line when a pulse occurs on Bb? The data on Ba is input and the data modulated by V21 is sent to signal i! 189a.

70 is a tonal signal sending circuit, and when the data on the signal @7Bd is at the signal level "1", the signal line ? (Input the lc signal. Then, if the input data is "1", 4
82Hz tonal signal, "2" is 1080Hz
If it is ``3'', it will be a 1650Hz tonal signal, if it is ``4'', it will be a 1850Hz tonal signal, and if it is ``5'', it will be a 2100Hz tonal signal.
Output to 0a.

71 is an adder circuit, which connects the signal on the signal line 89a and the signal line 7.
Input the 0a signal and add the result to the signal line? Output to 1a.

72 is a tonal signal detection circuit, which inputs the signal of the signal line 88a and outputs a "1" signal to the signal line 72a when a 482Hz signal is detected, and a "2" signal to the signal line 72a when a 1080Hz signal is detected. signal.

When a 1850Hz signal is detected, a signal of "3" is sent to the signal line 72a, when a 1850Hz signal is detected, a signal of "4" is sent to the signal line 72a, and when a 2100Hz signal is detected, a signal of "5" is sent to the signal line 72a. Outputs the signal.

A binary signal detection circuit 73 generates a pulse on a signal line 73a when a binary signal is detected, and outputs demodulated binary data to a signal line 73b.

74 is a start button, and when this start button is pressed, a signal of signal level "1" is outputted from the signal line 74a.

Reference numeral 75 denotes an error retransmission mode selection switch, which outputs a signal of signal level rlJ to the signal line 75a when transmission in the error retransmission mode is selected.

7B is a control circuit.

77 is a mode change notification sound generation circuit, and a signal line 78e
When a pulse is generated, a "beep" sound is generated.

Figure 12 is the first! 7 is a flowchart showing a control procedure of the control circuit 76 shown in the figure.

In step 51014, it is determined whether the start button 74 has been pressed. This is the signal line 74a
This is determined by inputting the signal.

When the start button 74 is pressed, step 5tot
Proceed to e.

In step 3101B, it is determined whether the start button 74 has been pressed continuously for 2.5 seconds or more.

This is determined by inputting the signal on the signal line 74a. If the start button 74 is continuously pressed for 2.5 seconds or more, the process proceeds to step 51028. If the start button 74 is not continuously pressed for 2.5 seconds or more, the process proceeds to step 5O1B.

In step 51018, it is determined whether the error retransmission mode is selected. This is the signal line 75a
This is determined by inputting the signal. Then, when the error retransmission mode is selected, step 510
On the other hand, if the error retransmission mode is not selected, the process proceeds to step 51020.

Step 81020 indicates transmission of image information by 9600b/S.

In step 31022, it is determined whether the other party's facsimile device (receiving device) has an error retransmission function. Information indicating whether the receiving side device has an error retransmission function is communicated to the transmitting side by the FIF of the NSF signal. That is, by inputting the signals on the signal lines 73a and 73b, it is determined whether or not the receiving side device has an error retransmission function. If the receiving device has an error retransmission function, the process proceeds to step 5102B; on the other hand, if the receiving device does not have an error retransmission function, the process proceeds to step 51024.

In step 5IQ24, image information in 4800b/S is transmitted.

In step 5102B, image information is transmitted in error retransmission mode.

In step 51028, a "bleep" sound is generated (sending a pulse on signal line 78e) to inform the operator that the error retransmission mode is selected.

Step S! At 030, it is subsequently determined whether the start button 74 has been pressed continuously for 2.5 seconds or more. Is this a signal line? This is determined by inputting the signal 4a. If the start button is continuously pressed for 2.5 seconds or more, step 91032
On the other hand, press the start button twice in succession.
．． If the button is not pressed for 5 seconds or more, the process advances to step 51G22.

In step 51032, a "beep" sound is generated (a pulse is sent twice to the signal line 78e).

Inform the operator that G2 mode is selected.

In step 51034, transmission is performed in G2 mode.

9B Management of FIFO Memory in Sending Device (Used in FIGS. 13 to 15) Management of the FIFO memory included in the sending device will be described below.

The 13th ffi (1) and (2) are diagrams explaining the relationship between the F rFO memory and various pointers. Ding MHP
TR indicates up to which address in the FIFO memory space encoded data is stored.
TMDPTR indicates up to which address in the FIFO memory space the data was modulated and sent to the line.The encoder stores the encoded data from the FIFS address and stores the encoded data up to the TPIFE address. When stored, the next encoded data is stored at the TPI FS address. At this time, a flag called REVMS (reverse) is set to 1, and the encoded data is stored up to the final address of the FIFO and sent to the TMH.
Notifies that P-R has returned to the beginning of FIFO.

On the other hand, as processing on the modem side, the encoded data from the TFTFS address is sequentially read out, modulated, and then sent out to the line.Then, the data stored at the FIFE address is read out, modulated, and sent to the line. After sending to
Read the data stored at TFIFS address,
Modulate and send out on one line.

At this time, the REVMS (reverse) flag is set to 0 and the encoding side is informed that the data modulation and transmission to the line at the final address of the FIFO have been completed and TMDPTR has returned to the beginning of the FIFO. Let me know.

The main effects of FIFO management in the sending device are as follows.

(2) When the line number changes, the address where the encoded data corresponding to that line number is stored is stored in the memory that stores the retransmission start line number.

- Prevent the modem pointer, ie TMDPTR, from overtaking the encoder pointer T)IHPTR.

■ Encoder pointer T) IHPTR goes around the FIFO memory so that it does not get too close to the modem pointer TNDPTR (Retransmission is performed when a reception error occurs on the receiving side, but the data for this retransmission is
(to leave it in FO memory).

Regarding the above-mentioned item (2), since it has already been explained using FIG. 10, the explanation will be omitted here.

Next, the modem pointer T will be explained regarding the above ■.
To prevent MDPTR from overtaking the encoder pointer TMHPTR, the modem pointer TMDP
When TR approaches the encoder pointer TMHPTR, a fill is sent. Here, when encoding the read data, EOL consists of 2 bytes, 001,
The following example can be considered as an example of control of such item (2), which is set as data of llOH (see FIG. 10).

If the modem pointer TNDPTR detects OOH, 8GH data while transmitting data from the FIFO memory, the REVMS (reverse) flag is checked.

When the REVRS (reverse) flag is O, it is determined whether (high address in encoder pointer TMHPTR) - (high address in modem pointer MDPTR) < 2, and if the above conditions are satisfied, the filter is When the above conditions are not met,
That is, when (encoder pointer T)address in IHPTR) - (high address in modem pointer TMDPTR)≧2, modem pointer TMDPTR
is sequentially incremented to send out the data stored in the FIFO memory.

On the other hand, when the REVHS (reverse) flag is 1, it is first determined whether the high address in the modem's pointer TMDP-R is equal to TFIFEH (the byte at the final address of the FIFO). Modem pointer: High address in NIIPTR is TFIF
If it is not equal to EH, the modem pointer is sequentially incremented and the data stored in the FIFO memory is sent out.

When the modem pointer TMDPTR is equal to DIFER.

(High address in encoder pointer TMHP-R) - TFIFJ) Determine whether I < 1, and if the above conditions are met, send out the fill; if the above conditions are not met, that is, ( If the encoder pointer (high address in NHPTH) -TPIFSH≧1, the modem pointer TNDPTR is sequentially incremented to send out the data stored in the FIFO memory.

In the above case, even in the case of transmitting a fill, all encoding is completed (actually, when encoding is completed on the encoding side, the flag MHENO is set to 1, so the modem side sets this flag to 1. You can check whether all encoding has been completed by checking), the modem's pointer T
) Sequentially increments IDPTR and sends out the data stored in the FIFO memory.

Furthermore, when all encoded data has been sent out, an RTC (Return To Control) signal is sent out. This RTC also includes the last transmitted line number after EOL. The number of EOLs is 103.

Next, the above item (2) will be explained. FIG. 14 shows the number of bits and bytes transmitted in 3 seconds at each transmission speed. That is, in order to enable retransmission with a delay of up to 3 seconds in a round trip, the encoder's pointer MHPTR must match the modem's pointer NDPT.
Must be more than 3600 bytes away from H.

FIG. 15 shows the relationship between the FIFO memory and various pointers. In this embodiment, when the high address in the encoder's pointer MHPTR is incremented, it is compared with the modem's pointer IDPTR.

Control is performed so that the encoder pointer TMHPTR is separated by 4088 bytes or more from the modem pointer 〈MDPTH. A specific example of this control is shown below.

When incrementing the high address in the encoder pointer TMHPTR, REVHS(su/<-
When the REVHS (reverse) flag is O.

(DINGFIFEH-(Encoder pointer TIIHPT
High address in R)) + ((modem pointer T
High address in NDPTR) - TFIFS) I
) It is determined whether or not <18, and if the above condition is satisfied, encoding is interrupted and a wait state is entered. In addition, when the above conditions are not satisfied, that is, (TPIFEH-(encoder pointer TMHPTR
)) + ((modem pointer TM
High address in DPTR)-TPIFS)i)
When ≧16, perform encoding and convert the encoded data to F
Store in IFQ memory.

On the other hand, when the REVHS (reverse) flag is 1, it is determined whether (modem pointer TIII [high address in 1PTR) - (high address in encoder pointer TNHPTR) < 16, and the above condition is satisfied. When the condition is satisfied, encoding is interrupted and a wait state is entered.

When the above conditions are not met, that is, (high address in modem pointer T) IDPTR) - (high address in encoder pointer TMHPTR) ≧16, encoding is performed and the encoded data is transferred to the FIF
Store in O memory.

97 Validity of memory capacity for storing retransmission start address The memory area for storing retransmission start address is considered to be 1024 bytes in this embodiment. Therefore, 512 retransmission start addresses can be stored. That is, it is possible to retransmit one minute of the past 512 line numbers.

Here, when one line is encoded, the shortest data is when one line is completely white. As described above, the number of bytes when encoding an all-white line is 7 bytes.

Since one line number is incremented every l line, the minimum number of bytes for one line number is seven.

Then, considering the retransmission of one minute for the 512 line number,
A minimum of 3584 bytes is required. At this time, if the transmission speed is 480Qb/S, 3584 (bytes)
÷600 (bytes 7 seconds) string l (seconds), and as mentioned earlier, 3 seconds is considered as the time to allow for delay on the line, so the retransmission start address is stored in a memory with a capacity of 512 pieces. It is sufficient to store it.

98 Control After All Image Information Is Sent from the Sending Device When all encoding of the transmission document is completed, a control return signal (RTG; Return to Cantral) signal is written to the FIFO memory. This RTG is E
OL 103 pieces. And following EOL,
Add the last sent line number. EO here
L consists of <12 bits, with "1" following control of 11 rQJs.

The above RTG transmission time is 0 at 4800b/s.
．． 6 seconds, and 1.2 seconds at 2400b/S.

Generally, when error retransmission is performed, the quality of one line is often poor, so the RTC signal is
If the number is set to 8, it is expected that RTC detection will not be possible. Therefore, the EOL of the RTC signal was set to 103 so that the receiving device could always detect the RTC signal.

In fact, even when the modem finishes transmitting the RTC signal, it does not immediately start transmitting the procedure signal. ) is considered to be 1 second as the detection time. Then, after 1.5 seconds have passed after the sending of the RTC signal, if it is 5ED-0, the receiving side sends PIS.
It determines that the signal is not being sent and proceeds to send the 1-procedure signal, specifically as the 1-procedure signal, EOM/)
IPS/EOP/PRI-EON/PRI-MPS/P
Use RI-EOP.

Furthermore, after 1.5 seconds have elapsed after the sending of the RTC signal ends, if it is 5ED-1, the process proceeds to search for the PIS signal.

If a PIS signal is detected within 2 seconds, error retransmission is performed, and if a PIS signal is not detected even after 2 seconds, the process proceeds to transmit a procedure signal.

9. Conditions for making a retransmission request from the receiving device and conditions for making a fall pack request (used in FIG. 16) There are three cases in which the receiving device makes a retransmission request, as described below.

■ When an image error occurs for 3 or more consecutive lines.

■ When the training signal reception fails, ■ After entering the image reception mode, the EOL signal is not received for a certain period of time (for example, 4.5 seconds for 240Qb/S, 3.5 seconds for 4800b/S). When it cannot be detected.

Also, "While one document is being transmitted, it is retransmitted three times."
However, if error-free data is received over a certain number of bytes (for example, 127 bytes), the counter that counts the number of retransmissions is reset.

The flowchart shown in FIG. 16 represents the image reception control procedure focusing on the case of making a retransmission request and the case of making a fall pack request. The above retransmission request/fall pack operation will be explained in detail with reference to this figure.

Step 5103B is 0 representing the image reception state.
Before image reception, a counter that counts the number of times the NSF signal is sent and a retransmission counter that indicates how many times one document was retransmitted during reception are cleared.

In step 51038, it is determined whether training reception was successful. Successful training reception means that confirmation of SE[l-1, GO-0 (about half the length of training time), and CD-1 were successfully confirmed. If training reception is successful within 3.5 seconds, proceed to step 51040; on the other hand, if training reception is not successful within 3.5 seconds, proceed to step 81078.

Normally, training reception ends within 3.5 seconds.

Therefore, if training is not completed within 3.5 seconds after starting training reception, it is determined that training reception has failed. In this way, in this embodiment, it is possible to immediately determine that training reception has failed. Therefore, then erroneous retransmission or? It becomes possible to send the ISF@ signal (which may also be an IICM signal).

The selection of whether to perform error retransmission or to send the NSF signal (when the NSF signal has been sent three times, the DON signal is sent) will be described later.

In step 51G40, since the training reception was successful, the counter that counts the number of times the NSF signal is sent is cleared. When performing error retransmission, the receiving device transmits the NSF i number following the PIS signal. This NSF signal includes information such as the retransmission start line and the presence or absence of a fall pack. When the transmitting side device correctly receives this NSF signal, it performs control such as fall pack and then retransmits from the retransmission start line.

(b)) When the transmitting device cannot correctly receive the NSF signal, it goes back to receiving the NSF signal.On the other hand, after transmitting the NSF signal, the receiving device goes to receive the training signal.However, the transmitting device Since no training signal is sent, training reception will be unsuccessful. At this time, the receiving device receives 5ED- within 3.5 seconds.
1 is detected (step 91078).
), in this case, the training signal is not sent out, so the SED is "0", and the receiving device goes back to sending out the NSF signal, and the above counter is for counting this number of times.

If the training signal is not sent from the sending side even after sending the NSF signal three times, a DON signal is sent to disconnect the line.

Steps 51042 to 510413 represent the image reception state.

In the stave 7 IQ 42, it is determined whether or not consecutive errors have occurred in three or more lines. These three lines are just one example, and can be set to any other value. Also, depending on the detail of the received image,
It is also possible to automatically change the number of lines.

If a continuous error of 3 or more lines occurs, the process proceeds to step 51052 to retransmit the error. On the other hand, if a continuous error of 3 or more lines does not occur, the process proceeds to step 51052.
Proceed to 1044.

In step 31044, 3 minutes (2400b/S
(7), it is determined whether or not the EOL signal is detected over a period of a=4.5 seconds, and when 480Qb/S, a=3.5 seconds). Then, for 6 seconds, E
If no OL signal is detected, step 5105
Proceed to step B and retransmit the error, and EO within 6 seconds.
If the L signal is detected, the process advances to step 5104B.

The six seconds are determined based on the longest transmission time of one line at each transmission speed. This makes it possible to perform error retransmission even when training reception is successful but correct data is not demodulated.

In step 5104B, RTC (Return)
t.

Control) signal is detected.

When the RτG signal is detected, the process proceeds to step 51048.

On the other hand, if no RTG signal is detected, the process advances to step 51042.

Step 51048 represents a post-procedure.

Step 91050 occurs when a time-out occurs (by IB minutes) while receiving one document, and represents an error.

In step 51052, it is determined whether or not correct data of a certain number of bytes or more has been received.When the characteristics of the six lines are in a steady state, image reception is good, but an error occurs due to impulsive noise that occurs infrequently. If this occurs, it means that more than a certain number of bytes of correct data have already been received.

In such a line situation, even if fall pack is performed on the transmitting side, an error will occur again.

Therefore, in such cases, it is better not to use unnecessary fall packs. In other words, if correct data of a certain number of bytes or more has been received first, step 5
Proceeding to 1054, the retransmission counter is cleared. If correct data of a certain number of bytes or more has not yet been received, the process advances to step 9105B and the retransmission counter is not cleared.

In step 9105B, a PIS signal is sent to interrupt transmission on the transmitting side.

In step 91058, the retransmission counter is incremented by one.

In step 5IOEIO, it is determined whether the signal has arrived (that is, whether it is 5ED-1). When it is 5ED-1, the process advances to step 31082.

In this case, the PISt sent in step 9105B
This is a case where the transmitting device is not receiving the signal correctly. On the other hand, when it is 5ED-0, the process advances to step 51084.

In step 910B2, the PIS signal is sent again.

In step 510B4, it is determined whether the count value of the retransmission counter is 3 or more (that is, whether fall pack is to be performed). When the count value of the retransmission counter is 3 or more (i.e., when performing fall pack)
If the count value of the retransmission counter is less than 3 (that is, if fall pack is not performed), the process proceeds to step 510813. Proceed to step 4.

In step 5108B, it is determined whether the current transmission speed is 2400 b/s. When the current transmission speed is 2400b/S, no further fall pack can be performed, so after sending the DON signal (step 5toes), the error ends (step 9107G).On the other hand, when the current transmission speed is 240Q
If it is not b/S, proceed to step 51072 and specify fall pack.

In step 51074, an NSF signal containing information on the presence or absence of a retransmission start line/fall pack is sent.

In step 5107B, the counter for counting the number of times the NSF signal is sent is incremented by 1, and then the process proceeds to receive the image signal.

Step 51078 is a block that branches when training reception fails. If the training signal reception after sending the CFR signal fails,
If an error retransmission is performed, but after the error retransmission is performed once and the NSF signal is sent, the training signal reception fails, there are two cases: an error retransmission and a case where an NSF/DON signal is sent.

That is, if the transmitting side device does not correctly receive the NSF signal (when the transmitting side device does not send out a training signal; YES in step 51078, YES in step 51080), the NSF signal is retransmitted. On the other hand, if the reception is unsuccessful in the receiving side device (NO in step 91078), error retransmission is performed.Here, step 5107B
In step 51, 5ED-1 indicates that it is determined that the training signal has arrived.
If SE[]-1 is detected in step 51078 (i.e., the training signal has arrived), the process proceeds to step 5105B. On the other hand, if SE[l-1 cannot be detected in step 51078 (i.e., the training signal has arrived) has not been reached), step 510
Proceed to 80.

In step 51080, it is determined whether an NSF signal for retransmission was sent immediately before. If the NSF signal for retransmission was sent immediately before, step 5108
If the NSF signal for retransmission has not been sent immediately before, the process proceeds to step 5105B.

In step 51082, it is determined whether the NSF signal has already been retransmitted three times. If the NSF signal is retransferred three times, the DCM signal is sent (step 51084) and then the process ends with an error (step 51).
08B), if the NSF signal has not been retransmitted three times, the process advances to step 5101114 and the NSF signal is retransmitted.

10 Structure of NSF signal (Used in Figure 17) The receiving side device is provided with a memory area to store the latest received line number. At the time of initialization, data of 0IOLH is stored.

Each time the decoder detects EOL, it checks the next two bytes of data, ie, the line number. If the line number received this time is incremented by less than 3 compared to the line number correctly received last time, it is determined that the received image is "good". In other words, if the image error is less than 3 lines, it is determined that the reception is "good". This line number is stored in memory and updated each time it is detected.

On the other hand, if the line number received this time is incremented by three or more from the line number correctly received last time, a signal is sent to the NAC. In other words, if an image error occurs on three or more lines, it is determined that the received image is defective and a request is made to retransmit the error.Therefore, after sending the PIS signal, 300b/S This signal is used to notify the sending device of the retransmission start line number and the presence or absence of a fall pack.

Figure 17 shows an example of a 300b/s signal sent from the receiving device to the transmitting device. In this figure, the preamble is a roll 1110 J pattern that is continuously sent for about 1 second, FFH is address data, and 13H is Control data (sent to the line in order from LSB data to MSH data), 201 (is the NSF FGF (Facsimile Control Field), and
The line numbers to be transmitted thereafter are data focused on the last nine digits of the line numbers, from line number 0 to line number 511. Regarding the line number to be sent next, the LSB of each byte data is
Do not set 1 to 0. For example, line number 0 is 00H, OOH.

The next byte data indicates the presence or absence of a fall pack. Specifically, when QQI (FF), the fall pack is not specified, and when it is FF, the fall pack is specified.

Fl, J are frame check sequences, and FLAG is roll 1110J.

When decoding when receiving images, 2 following EOL
Byte data (ie, line number) is ignored.

11 Operation of the transmitting device when receiving a NACK signal (see Figure 18) The transmitting device reads the information on the document using the reading means, encodes the data using the encoder, and transmits the encoded data using the modem. It is modulated and sent to the line. At this time, the NAGK signal (PIS signal in this embodiment) is monitored. Then, if the NACK signal is not detected, the image information is transmitted, and if the NACK signal is detected, the image information transmission is interrupted. And 300b
As described above, the line number (lower 9 digits) for starting retransmission and information on the presence or absence of a fall pack are stored in this 300b/S heading for reception of the /S signal.

When the sending device detects the retransmission start line number, the address in the encoder pointer TMHPTH in the sending device and the modem pointer T in the sending device
MDPTR17) 7 dos L/S, REVRS (IJ
The following three cases can be considered as examples of this control, in which the retransmission start address is checked and the retransmission start address is checked, and various controls are performed based on the results.

In the first case, the REVRS flag is 0.

Encoder pointer TMHPTR in the sending device
is greater than the modem pointer TMDP of the transmitting device when
This is the case when TR is larger than the retransmission start address. 18th
Figures (1) to (3) illustrate three cases in which a retransmission start address is recognized and retransmission is performed. The first case described here is illustrated in FIG. 18(1). In this case, the pointer T) ID of the modem in the sending device
A retransmission start address is set in the PTH, and retransmission is performed from that line number.

The second case is illustrated in FIG. 18(2).

That is, the REVRS (reverse) flag is 1 and the modem pointer TMDPTR in the sending device
is the encoder pointer in the device 〒MHPTR
This is the case if it is larger. In this case, the retransmission start address is set in the modem pointer TMHPTH in the transmitting device, and retransmission is performed from that line number.Here, the encoder pointer TMHP in the transmitting device is
If TR is larger than the retransmission start address, it is determined that an error has occurred, and the line is released by sending out, for example, a DCN signal (based on 300b/S) without transmitting image information.

The third case is illustrated in FIG. 18(3).

That is, the REVRS (reverse) flag is 0, and the encoder pointer TMHPT in the transmitting side device
R is the modem pointer in the device T) IDPTR
This is the case when the retransmission start address pointer is larger than the modem pointer 〒)IDPTR in the sending device. In this case, set the retransmission start address to the modem pointer 〒DPTR in the sending device, and retransmit from that line number.
Set the EVERS flag to 1. Here, if the encoder pointer TM)IPTR in the transmitting side device is larger than the retransmission start address, it is determined that it is an error, and the image information is not transmitted.
/S) to open the line.

When instructed to perform fall pack, perform fall pack and transmit image information.

Furthermore, if a DON signal is detected following the P■S signal, the line is released and the process is terminated with an error.

912 Description of Block Diagram of Sending Device (Used in FIGS. 18 and 20) FIG. 18 is a block diagram showing the configuration of the sending side of a facsimile device to which the present invention is applied.

In FIG. 19, reference numeral 2 denotes a network control unit NCU (Network Control l1nit) that maintains the loop.
) In order to use the telephone network for data communication, etc., it connects to the terminal of the line and controls the connection of the telephone exchange network, or switches to the data communication path.

2a is a telephone line.

4 is a hybrid circuit that separates a transmission system signal and a reception system signal. The transmission signal of signal 1128a is signal line 2
b, and is sent to the telephone line 2a via the network control device 2. Further, the signal sent from the other party's facsimile machine is output to the signal line 4a after passing through the network control device 2.

6 is a circuit that detects a retransmission request signal (in this embodiment, a PIS signal is used) sent from the receiver. In other words, a signal on the signal line axis is introduced, and a retransmission request signal (
In this embodiment, when detecting the PIS signal, a signal with a signal level of "1" is output to the signal line 6a. On the other hand, when the signal on the signal line 4a is introduced and a retransmission request signal (PIS signal in this embodiment) is not detected, a signal of signal level "0" is output to the signal line 8a.

8 is a 300b/S signal (in this embodiment, an NSF signal is used; the 17th (see figure) and a disconnection command (D
CN) signal (300b/S signal). When the binary signal receiving circuit 8 detects the NSF signal, it generates a pulse on the signal line 8a and outputs a retransmission start line number on the signal line 8b. and,
Information on the presence or absence of fallback (O→no fallback, 1→fallback) is output to the signal line 8d. Moreover, this binary signal receiving circuit 8 has Dll:N
When a signal is detected, a pulse is generated on the signal line 8c.

Reference numeral 10 denotes a reading device which reads image signals for one line in the main scanning line direction from the transmitted original and creates a signal string representing a binary value of white or black. This reading device 10 is composed of an imaging device such as a ccn (charge coupled device) and an optical system. When a pulse is generated on the signal line 12a, that is, when there is a request to read the l-line image signal, the one-line image signal is read and the binarized data is output to the signal line 10a.

Reference numeral 12 denotes a double buffer circuit so that while the image signal in one buffer memory is being encoded, the image signal of the next line is written into the other buffer memory. The 2-tree buffer is BUFO (buffer 0)
, BUFI (buffer l), when the buffer of B[IFO is full of image data, the signal line 12
A signal of signal level rlJ is output to b (buffer full). When the BUFO buffer is not full of image data, the signal line! A signal of signal level "o" is output to 2b (z<sofa 0 full). Also, BUFI
When the buffer is full of image data, a signal of signal level "1" is output to the signal line 12c (buffer l full). When the BUFI buffer is not full of image data, a signal of signal level rQJ is output to the signal line 12c (buffer 1 full).

After confirming that the buffer is full, the control circuit 30 (described later) selects the buffer to be read next by connecting it to the signal line 3θ.
When the signal level of the signal line 30b is "0" as specified by the signal output to the signal line 30b, the data of the buffer O is read;
When the signal level of the signal line 30b is "1", the buffer 1
data is read out), and then a pulse (read pulse) is generated on the signal line 30a.

This double buffer circuit 12 outputs the data of the designated buffer to the signal line 12d. When the data of the specified buffer is output to the signal line 12d, the buffer full state of the specified buffer is dropped, that is, the signal level output from signal line 3ob# is "0" (buffer O designation). As a result, a (read) pulse is generated on the signal line 30a.

When all the data in the buffer is output, the buffer full 0 is dropped (that is, a signal with signal level "0" is output to the signal ji12b), and the signal level output to the signal line 30b becomes rlJ (buffer l specification) and a (read) pulse is generated on the signal line 30a and all the data in the buffer is output, the buffer is full.
(In other words, the signal level “o” is applied to the signal line 12c.
signal).

Furthermore, when the buffer becomes empty, the double buffer circuit 12 generates a pulse on the signal line 12a, and inputs data for one line in the main scanning direction from the reading device 1G. In this case, the data is stored in an empty buffer, but at the same time, the buffer full in which the data was stored is set to 1. The read data is stored alternately in buffer O, buffer I, buffer Q, /<buffer 1.

14 is a counter that counts the line number inserted after the end-of-line code (EOL).

When a pulse occurs on signal 1130c, the line number is set to 0 (OIOIH). And signal line 3
The line number value is incremented every time a pulse force is generated at 0d. In other words, the line number is 0 (O
When a pulse is generated in the signal 30d in the state (IOIH), the line number becomes 1 (01031).

The same applies below. Further, 2-byte data indicating the line number is output to the signal line 14a.

1B inputs one line of binarized data output to the signal line 30e, and sends the encoded data (modified Huffman encoding in this embodiment) to the signal line 1B.
This is a circuit that outputs to 8c. When one line of binary data is input and the number of encoded bits reaches 8, that is, when one byte of encoded data is complete, a pulse is generated on the signal line lea. . On the other hand, 1
When all lines have been encoded, a (end) pulse is generated on the signal line 18b. When the encoding of one line is completed, if the last data is less than 8 bits, the remaining data is set to 0 and processing is performed as if the data is 8 bits.

18 is a FIFO memory used to read line data and store encoded data. On the other hand, the modem side reads the data stored in this FIFO memory, modulates it, and sends it out to the line. Encoded data is written to the FIFO memory using the three signal lines from the signal line 30f to the signal line 30h. When a (write) pulse is generated on the signal line 30f, the data is written to the address output on the signal line 30g. , stores the byte data output to the signal line 30h. Also, 30 layers of signal lines, 30 layers of signal lines
The signal 1i3 reads the data stored in the FIFO memory using the three signal lines j and signal line 18a.
When a (read) pulse occurs on 0i, the signal line 30j
In this embodiment, the FIFO memory has 8400
It has addresses from H to AFFFH.

Reference numeral 20 denotes a retransmission start address storage memory, whereby when a reception error occurs on the receiving side, the transmitting side device retransmits from the line number where the error occurred. In this case, it is necessary to recognize from which address in the FIFO memory the data of the line number is stored, and this data is stored in this memory. The signal line 30IL is connected to the signal line 30.

The signal line 30m is used to write information such as "from which address in the FIFO memory the data of a certain line number is stored" into the main memory 20.
When a write pulse is generated, the byte data of the signal line 30 is stored at the address output to the signal line 30k. In addition, by using the signal line 30, the signal line 30n, and the signal line 20a, "data from a certain line number is
Information such as "from which address in the memory the data is stored" is read from the main memory 20.

When a (read) pulse is generated on the signal line 30n, the data at the address being output on the signal line 30k is output on the signal line 20a. The retransmission start address storage memory is
It has an address from cooou to C3FFH. The memory configuration for storing the retransmission start address is as shown in FIG.

As shown in FIG. 20, the address COOOH, C00
The address of line number 0.512... is stored in IH, the address of line number <1,513... is stored in address 00G2)1.00031(,
Address COO4H and COO5H have line number 2.
, 514...

The address C3FC is stored, and similarly, the address C3FC is stored.
H,03FDH has line number 510.1022.
The address of ... is stored, and the address 03FEH, (:
Addresses of line numbers 511.1023, . . . are stored in 3FFH.

22C. This P/S conversion circuit 22, which is a parallel-to-serial conversion circuit (hereinafter abbreviated as P/S conversion circuit) that converts parallel data into serial data, is connected to the signal line 22a when the parallel data becomes empty. Generates byte data request pulse. The control circuit 30 is.

When a pulse is generated on the signal line 22a, byte data is outputted on the signal line 300. On the other hand, the P/S conversion circuit 22
The byte data output to the signal line 300 is input, and after performing parallel-to-serial conversion, the serial data is output to the signal line 22b.

24 is a modulator that performs modulation based on the well-known GGIT recommendation V27ter (differential phase modulation). This modulator 24 inputs the signal of the signal line 22b and performs modulation,
The modulated data is output to the signal line 24a.

2B is a circuit that sends a DCN signal (300b/S (7) signal) to the signal line 28a when a pulse is generated on the signal line 30P. This DON signal sending circuit 2B is
When the sending of the DON signal is completed, a pulse is generated on the signal line 28b.

Reference numeral 28 denotes an adder circuit that inputs the signal on the signal line 24a and the signal on the signal line 28a, and outputs the added result to the signal line 28a.

Reference numeral 30 denotes a control circuit, which will be explained in detail in item 912 and fort 13 described below.

913 General operation explanation of the control circuit in the transmitting side device (
(Used in FIG. 21) The control circuit 30 shown in FIG. 18 performs the control described below. However, encoding is processed according to the main routine, and signal transmission is processed using an interwoven routine.

The encoding by the control circuit 30, ie, the control process in the main routine, is as shown in FIG. First, set the modem pointer TMDPTR and the encoder pointer TNHPTR to the start address of the FIFO memory that stores the encoded data (step 5too), and check whether reading of the image information of one main scanning line has been completed. That is, it is determined whether the line buffer is full (step 8102).

When reading the image information of the main scanning line for one line is completed (that is, when the line buffer becomes full),
Proceed to step 5104, and.

Read the l line data (step 5IQ4
), where, as mentioned above, the buffer is buffer O,
It has a double buffer configuration with Baaf 1, and these 2
Data is read out alternately from two buffers.

After data is read from each buffer, it is encoded, and the encoded data is written to the FIFO memory (step 910B).The main controls during encoding are listed below.

1. Write encoded data to F IFO memory.

2. Write the line end code (!OL signal) (the data to be written to the FIFO memory is OOH, 80H) and the line number to the FIFO memory.

3. If a reception error occurs in the receiving device, the transmitting device retransmits the data from the line number where the error occurred. The following control is performed to enable this retransmission.

That is, when incrementing the byte in the encoder pointer TNHPTH, the encoder pointer TMHPTR changes to the modem pointer TNDPTR FI
It goes around the FO memory and controls it so that it does not get too close. Specifically, the encoder pointer TN)tPTR
When TM[]PTH approaches the modem pointer TM[]PTH, encoding is interrupted and the modem enters a wait state. And when you're doing weights.

It is checked whether a PIS signal is detected, and if a PIS signal is detected, an NSF signal is received.

Then, the pointer of the modem is set to the retransmission start address and retransmission is performed from that data. When performing this retransmission, training is performed again. This is the same control as from step 910B to step Sl 12 described later.

4. When retransmitting data from a certain line number, it is necessary to recognize from which address in the FIFO memory the data of that line number is stored. This information is stored in the retransmission start address storage memory.

Then, when the encoding of a certain line is completed, it is determined whether or not a retransmission request signal, that is, a PIS signal is detected (step 910B).
When an IS signal is detected, the transmission of one-picture information is interrupted, and the NSF
A signal is received (step 5ilo). If there is a fallback instruction here, the modem transmission speed is reduced and fallback is performed. Furthermore, if a DON signal is received, the process ends with an error.

Next, the modem's pointer TNDP-R is set to the retransmission start address (this information is included in the NSF signal), and the data is retransmitted starting from that address (step 5112).
.

After that, it is determined whether the encoding of one page of the manuscript is completed (
Step 5114) If the encoding of one document has not yet been completed, the process returns to step 5102. In addition, when encoding of one document is completed, step 9
Proceed to 11B.

When the encoding of one document is completed, it is determined whether there is any unencoded data remaining in the double buffer memory (step 5llllll).

If unencoded data remains in the double buffer memory, the process returns to step 5102. Also,
If there is no unencoded data remaining in the double buffer memory, the process advances to step 5118 and the control return signal RTC (Return↑0Control) is set to F.
Write to IFO memory.

Thereafter, it waits for the data stored in the FIFO memory to be sent out by the modem. And FIFO
After the data stored in the memory has been sent out, 1.
Wait for only 5 seconds. At that time, if it is 5ED-0, proceed to the post-procedure (step 5122). On the other hand, if it is 5ED-1, it means that a PIS signal is being sent from the receiving side device, so the process goes to detect the PIS signal and correct the error retransmission. (step 5120).

On the other hand, the transmission processing (that is, interwoven processing) includes (a) modulating the data stored in the modem pointer TMDPTH and sending it to the line, (b) sequentially incrementing the modem pointer TMDPTR, and (c) The main content is to control the modem pointer MDPTR so that it does not overtake the encoder pointer TM) IPTH.

914 Detailed operation explanation of the control circuit in the transmitting side device (using FIGS. 22 and 23) The control procedure performed by the control circuit 30 (main processing, i.e., Encoding processing procedure) will be explained.

First, various initialization processes are performed in steps 5128 to 5144.

In step 5128, a flag TRNEND indicating whether all encoded data stored in the FIFO memory has been sent out is set to O.

In step 8130, GOOO is set to the pointer AGAPTH that controls the memory that stores the retransmission start address.
Set H.

In step 5132, the encoder pointer
) I) Set 8400H to IPTH.

In step 5134, the modem pointer TMD
Set 8400H to PTR.

The line number is incremented every certain number of lines (1 line in this embodiment), and this control is controlled by a counter called LINCNT. In step 5136, this counter LINC:IT is set to 1.
Set.

In step 9138, the aforementioned REVRS flag is set to 0.

In step 5140, O is set to a flag M)IE)10 indicating whether or not encoding has been completed.

In step 5142, a flag BAF indicating which buffer is currently reading data is set.
Set. When flag BAF is 0, buffer 0
Reading data from. Also, flag BAF is 1
At this time, data is being read from buffer 1.

In step 5144, the line number is initialized.

In steps 514B to 5154, it is determined whether the buffer is full, that is, whether reading of l lines has been completed, and if the buffer is full, the process proceeds to step 515B, where the data in the buffer is
Buffer 0. Read alternately with buffer l.

In steps 5158 to 3160, 1
Read the line data from the double buffer and output it to the encoder.

In steps 51B2 to 5182 shown in FIG. 22(2), data of a specific line number is
The starting address of the IFO memory is stored in the retransmission start address storage memory.

Here, when the line number changes, the retransmission start address is stored in the retransmission start address storage memory.

In step S1θ2, control is performed to increment the line number for each line, step 816
4 to step S18, the low byte data at the retransmission start address is stored in the retransmission start address storage memory.

In step 5170, the retransmission start address pointer AGAPTH is incremented.
In steps 72 to 5178, the high byte data at the retransmission start address is stored in the retransmission start address storage memory. In step 5178,
In step 9180, the retransmission start address pointer AGAP-R is incremented.

It is determined whether the retransmission pointer AGAPTR has advanced to the end of the retransmission start address storage memory. When the retransmission pointer AGAPTR has advanced to the end of the retransmission start address storage memory, the retransmission pointer AGAPTR is set to COO.
OH is set (step 5182).

In steps 8184 to 518B shown in FIG. 22(3), OOH is stored in the FIFO memory.

In step 5190, the encoder pointer T
Increment MHPTR. This increment of TMHPTH will be described later.

In steps 5182 to 5186, F
Store 800H in IFO memory.

In step 5198, the encoder pointer T
) Increment IHPTR.

In steps 5200 to 521B.

Input the line number and store the line number in FIFO memory. That is, in step 5200, a line number is input. In steps 5202 to 5206, high byte data of the line number is stored in the FIFO memory. In step 5208, the encoder pointer TMH
Increment PTR.

In steps 5210 to 5214 shown in FIG. 22(4), the low byte data of the line number is stored in the FIFO memory. In step 521B, the encoder pointer TMHPTR is incremented.

In steps 5218 to 5230,
Store encoded data in FIFO memory.

First, in step 5218, it is determined whether 1 byte of data has been encoded. Once one byte of data has been encoded, the data is input (step 5220).
) l,, l bytes of encoded data are stored in the FIFO memory (step 5222 to step S2
2 [i).

In step 5228, the encoder pointer T
) Increment IHPTR. Step 5230
In this step, it is determined whether encoding of one line is completed,
If the encoding of one line is not completed, the process advances to step 5218, and when the encoding of one line is completed, the process advances to step 5232.

In steps 5232 to 5238 shown in FIG. 22 (5), it is checked whether or not the line number should be incremented, and if it is necessary to increment, the line number is incremented. Increments the line number.

In steps 5240 to 5248.

It is determined whether a retransmission request signal, that is, a PIS signal has been received. When a PIS signal is received.

Receive the NSF signal and input the retransmission start line number. Then, a retransmission start address is set in the modem pointer TMI)PTR, and data is transmitted starting from the data at that address.If there is a fall pack instruction here, the transmission speed is reduced.

Also, if a DON signal is received, the line will be disconnected.

Furthermore, even after a certain period of time (for example, 30 seconds), the NS
If the F signal cannot be detected, the line is also considered disconnected.

In step 5250, it is determined whether encoding of one document sheet has been completed. When the encoding of one document is completed, the process advances to step 5252.

If the encoding of one document sheet has not yet been completed, the process advances to step 8146.

In step 5252 and step 5254,
Determine whether either buffer is full. If either buffer O1 or buffer I is full, the process proceeds to step 514B. If neither buffer O nor buffer 1 is full, the process proceeds to step 525B.

Step 525 shown in FIG. 22 (6) and FIG. 22 (7)
8 to step 5300, a control return signal RTC (Return To Cont) is sent to the FIFO memory.
rol) signal.

First, in steps 525B to 5280, OOH data is stored in the FIFO memory.

In step 92B2, the encoder pointer MHPTR is incremented.

In steps 9284 to 5268,
80H17) Store data in FIFO memory.

In step 5270, the encoder pointer T
Increment MHPTR.

In steps 5274 to 5304 (see FIG. 22 (7)) and steps 5toee to 91128 (see FIG. 22 (8) and (9)), only 103 signals with line numbers added to the EOL are stored in the FIFO memory. The EOL in this embodiment is a signal consisting of 11 consecutive 0's and 1 1.

In step 91130, since encoding has been completed, the flag MHEND is set to 1.

In steps 91132 to 51170 shown in FIG. 22 (10), all data stored in the memory is waited for to be sent out by the modem.

When the PrS signal is detected, the NSF signal is received and the retransmission start line number is input. Then, the retransmission start address is set in the modem pointer TMDPTR, and data is transmitted from that address. If there is a fallback instruction, the transmission speed is reduced, and the D(:N signal is If the NSF signal is received, the process is considered to have ended with an error. Furthermore, if the NSF signal cannot be detected even after 30 seconds have elapsed, the process has also ended with an error.

If it is 5ED-0 after 1.5 seconds have elapsed after RTC is sent from the modem, that is, after RNEND becomes 1.

It is judged that the image transmission has been completed and the process proceeds to transmitting the 1-procedure value number.On the contrary, if the SEI is +-1 after 1.5 seconds have elapsed, the process proceeds to search for the PrS signal, and within 2 seconds When a PrS signal is detected, error retransmission is performed.
Furthermore, when the PrS signal is not detected even after 2 seconds have elapsed, it is determined that the image transmission has ended, and the process proceeds to transmit the procedure signal.

Steps 530G to 8328 shown in FIG.
This is a subroutine when detecting a signal) and setting the modem pointer MHPTR to the retransmission start address (
Step 5248, Step 5348. Step 81
18B).

The set of retransmission start addresses is 1) R as described above.
EVRJ7 When lag is 0 1-1) When TMHPTR>TM[1PTR and retransmission address < TMOPTH! -2) MHP R) TMOPTH1 and retransmission address > MHPTR1 and retransmission address > TMHPTH
(In this case, set REVH9 to 1.) 2) If the REVMS flag is 1, if TMDPTR > MHPTR and the retransmission address > TN) IPTH, set the retransmission address to the modem pointer TMDPTR. 9318), return (
Step 5320), otherwise it is treated as an error.

From step 5328 to step 5354 shown in FIG. 22 (12), the encoder pointer TMHPTR
is incremented.

Here, in step 5330, the encoder pointer TMHPTR is incremented. And T
M) If the high byte of IPTH is not incremented, return immediately, but if the no byte of TMHPTR is incremented, proceed to step 5334.

In steps 5334 to 5338,
The encoder pointer TMHPTR goes around once and is controlled so that it does not get too close to the modem pointer ↑MDPTR. That is, the encoder's pointer TM) IP
If TR is 4036 or more away from the modem pointer TMDPTH, return. At this time, it is checked whether the encoder pointer TM)IPTR has reached the end of the F rFo memory, and if it has reached the end of the F\IFO memory, the encoder pointer T
Set MHPTH to 84001.

If the encoder pointer TMHPTR is not 4096 or more away from the modem pointer TM[1PTR, encoding is interrupted and a wait state is entered. During this waiting period, it is determined whether a retransmission request signal (ie, P■S signal) is detected (step 9340).

If a PIS signal is detected, the transmission is interrupted (Step 5342), the NSF signal is received (Step 5344), and the retransmission start line number is input (Step 934B), and the retransmission address is set in the modem's pointer TMHPTR. Set.

Here, if there is a fall pack instruction, the transmission speed will be reduced, and if a DON signal is received,
The line will be disconnected. Furthermore, if the NSF signal cannot be detected even after a certain period of time (for example, 30 seconds) has elapsed,
The line will be disconnected.

The flowchart shown in FIG. 23 shows a detailed control process regarding encoded data transmission processing (i.e., interwoven processing). In this embodiment, a pulse (i.e., byte data request pulse) is generated on the signal line 22a. Then, this interwoven processing is executed.

The main control here is to sequentially read data stored in the FIFO memory from step 5370 to step 5.
37B), output to the P/S conversion circuit 22 (steps 8380 to 3388, step 539)
0 to step 539B), at this time,
Control the modem pointer T)IDPTR so that it does not overtake the encoder pointer. That is, when OOH, 8QH data is detected while transmitting encoded data, the encoder pointer TM) IPTR is detected as described above.
If it is not a certain amount of light compared to the modem pointer, it sends out a fill and waits for the encoding to progress (steps 5380 to 5392, step 54).
04 to step 5410), where MHEND
This is not the case when is 1 (that is, when encoding of one sheet of original is completed).

When the modem pointer reaches the end of the FIFO memory, the modem pointer MDPTR is set to the first address 8400H of the FIFO memory (step 53).
98.

5400).

Also, all encoding is completed (MHEND=l) L
, the modem sends out all encoded data (Ding MHPTR
= dingMDPTR) (step 5380 is T
RNEND is set to 1 (step 93BB) to notify the main processing routine (encoding processing routine) that the transmission of all encoded data has been completed.

915 Block Configuration of Receiving Side Apparatus (Used in FIG. 24) FIG. 24 is a block diagram showing the configuration of the receiving side of a facsimile apparatus to which the present invention is applied.

The conditions for performing error retransmission and the conditions for performing fall pack have already been described in detail, so we will not discuss them here; only the processing after actual image signal reception will be described below. .

In FIG. 24, 40 is the same network control device (NO■) as 2 shown in FIG. 19, and 40a represents a telephone line.

42 is a hybrid circuit similar to 4 shown in FIG. The signal sent to signal line 54a is transmitted to signal line 40b.
is sent to the telephone line 40a via the network control device 40. Further, the signal sent from the other party's facsimile device is transmitted via the network control device 40 and then sent to the signal line 42a.
is output to.

44 is a circuit that inputs the signal of the signal line 42a and detects whether or not the signal is present. When receiving a signal of -43dBm or higher, signal level "1" is applied to signal line 44a.
When a signal of less than -43 dBm is received, a signal of signal level rOJ is output to the signal line 44a.

4B is a demodulator that performs demodulation based on the well-known CGITT recommendation V27ter (differential phase modulation). Demodulator 4
8 inputs the signal of the signal line 42a, performs demodulation, and outputs the demodulated data to the signal line 48a.

48 is a serial-to-parallel conversion circuit that converts serial data into parallel data (hereinafter abbreviated as SIP conversion circuit). When 8-bit parallel data is ready, this S/P conversion circuit 48 sends a pulse to the signal line 48a. occurs,
The received data is output to the signal line 48b. The control circuit 88 recognizes that one byte of data has been received by detecting that a pulse is generated on the signal line 48a.

50 indicates the signal line 5 when a pulse is generated on the signal line B8b.
This is a circuit that sends an NSF signal (see FIG. 17) to 0a. The NSF signal includes a line number.

This line number is set to the value output to the signal line 88a. The NSF signal includes fall pack information. This fall pack information is output to the signal m8flh. When the signal line B6h is at the "0" level, a fall pack is not instructed, and when the signal fi88h is at the rlJ level, a fall pack is instructed. The NSF signal sending circuit 50 has N
When the transmission of the SF signal is completed, a pulse is generated on the signal line 50b.

52 is a circuit that sends out a retransmission request signal (that is, a PIS signal in this embodiment). In other words, when a pulse is generated on the signal line 88c, the pr
This is a circuit that sends out an s signal (4B2Hzc7) signal for 3 seconds. When the transmission of the PIS signal is completed, the signal line 5
2b generates a pulse.

Reference numeral 54 denotes an adder circuit that inputs the signal on the signal line 50a and the signal on the signal line 52a, and outputs the added result to the signal line 54a.

5B is an F used to demodulate data sent from the other party's facsimile machine and store the demodulated data.
This is IFO memory. This FIFO memory is the F
It is the same as the IFO memory (see 18 in FIG. 19).

On the other hand, the decoder reads the data stored in this FIFO memory, decodes it, records it through the double buffer circuit 62, and writes the demodulated data to the FIFO memory using the signal line 88c or signal line He. When a (write) pulse is generated on the signal line 88c, the signal line 88
The byte data output to the signal line Bee is stored at the address output to d.

In addition, when a (read) pulse is generated on the signal line fl18f, which reads the data stored in the FIFO memory using the three signal lines 88f, 11B8g, and 58a, it is output to the signal line 86g. In this embodiment, the address of the FIFO memory is 8400H to A.
It's FFFH.

58 is a line number storage memory that stores the latest correctly received line number. When writing a line number to this line number storage memory 58, output the line number to the signal line 68h, and
Generate a (write) pulse at i. On the other hand, if you want to read the latest correctly received line number, use the signal line 88.
When a (read) pulse is generated on j, the latest correctly received line number is output to the signal line 88h.

BO is a decoder that reads demodulated data from the FIFO memory and outputs the decoded data to the signal line 80c. When preparations for decoding the demodulated 1-byte data are completed, a byte data request pulse is generated on the signal line 80a. When the pulse is generated, the time control circuit 8B
reads 1 byte of demodulated data from the FIFO memory and outputs it to the signal line 86k. When the decoding of the l line is completed, the decoder 60 generates a pulse on the signal line 60b. Then, one line of decoded data is output to the signal line 80c.

62 is a double buffer circuit for writing the next line of image signals into the other buffer memory while the image signals in one buffer are being recorded. This buffer is the same as the transmitter's double buffer (see 12 in FIG. 12). 2 bars / 77 is BU
FO (bar/7 y O), BUFI (buffer 1
), when this buffer BUFO is full of image data, a signal of signal level "1" is output to the signal line 62a (buffer all full). When the BUFO buffer is not full of image data, the signal line 6
A signal of signal level "0" is output to 2a (buffer all full).

Furthermore, when the buffer of BUFI is full of image data, a signal of signal level "1" is output to the signal line 62b (buffer 1 full). When the BUFI buffer is not full of image data, the signal 182b (
A signal of signal level "0" is output to the buffer l full).

A control circuit 8B, which will be described later, recognizes that the buffer is empty and specifies which buffer to write data into. That is, when the signal line 88m is at the signal level "0",
Write data to bar 27aO; when signal line Hm has signal level “1”, write data to buffer 1)
After that, the recording data is output to the signal line 88n, and a (write) pulse is generated to the signal line 8Bi.

The double buffer circuit 62 sets the buffer full value of the designated buffer to 1.

On the other hand, when the recording device 64 finishes recording the line data stored in a certain buffer, it generates a recording request pulse on the signal line 84a.

Furthermore, when the double buffer circuit 62 detects the recording request pulse, if the buffer is full of data,
Record data is output to the signal line 82c. When all the data in the buffer is output to the recording device 84, the buffer full corresponding to that buffer is dropped. Here, the buffers used are buffer O, buffer 1 . Buffer 0. Alternating with buffer l.

A recording device 64 generates a recording request pulse on a signal line 84a when preparation for recording is completed. Then, the recording data outputted to the signal line 82c is input, and recording is performed.

6B is a control circuit, and its operation will be explained in detail in item 91B described next.

filB Explanation of operation of control circuit in receiving side device (used in FIGS. 25 and 26) The control circuit 86 shown in FIG. 24 performs the following control.

Reception of transmission data is processed by the previously described interwoven routine, and decoding is processed by the main routine.

In order to receive data, one byte of data is input every time a pulse is generated on the signal line 48a and stored in the FIFO memory. At this time, the modem pointer RNflPT
Increment R sequentially. On the other hand, when the modem pointer RN[1PTR reaches the end of the FIFO memory,
Set the modem pointer to the beginning of FIFO memory. At this time, the REVHS flag is set to 1.

FIG. 25 is a flowchart showing detailed control procedures regarding reception of demodulated data (ie, interwoven processing).

When a pulse is generated on the signal line 48a, interwoven processing starts (step 9600), step 58
In steps 02 to 5608, demodulated data is input and stored in the FIFO memory.

In step 8608, the modem pointer RMD
Increment PTR.

In step 5810, the modem's pointer is
Determine whether it has reached the end of the FO memory, and if it has reached the end of the FIFO, pointer RNDP of the modem
Set TR 8400H, SOLE REVRS 7
Set lag to 1.

The main processing content of the main processing (decoding processing) process is first to search for the line end code EOL. E
The two bytes following OL indicate the line number. If the line number is incremented by less than 3 compared to the previous time, it is determined that image reception is good. At this time, the line number is updated every time a new line number is received. Therefore, if the line number is three or more higher than the previous one, it is determined that the image reception is not good. Then, the PIS signal and the NSF signal in which the retransmission start line number is stored are sent to the transmitting device. At this time, as described above, control such as fall pack is performed, and the receiving device receives from that line number.

When image data is being received correctly, each line of image data is output to the double buffer and recorded. Output to the double buffer is performed alternately with buffer O and buffer 1.

When the encoder pointer reaches the end of the FIFO, the encoder pointer is set to the beginning of the FIFO.

At this time, the REVRS flag is set to O.

Figure 28 (1) to (4) are the decryption process (main process)
2 is a flowchart showing details.

Steps 5620 to 5630 shown in FIG. 26(1) represent various initializations.

In step 5820, the modem's pointer RNI
] Set 8400H to PTH.

In step 5622, the encoder pointer R
Set 8400H to MHP-R.

In step 5B24, a flag BAF (a flag indicating which buffer the recording data is to be stored in now) is set to 1.

In step 5626, the modem pointer is set to F.
Flag REV indicating returning from the end of IFO to the beginning
Set RS to 0.

In steps 5f128 to 9830.

Initialize the line number (set it to 0101)1).

In steps 5832 to 5640, E
Determine whether or not the office lady has been found. If EOL is found, proceed to step 8842.

In steps 5834 to 3838,
Input 1 byte of demodulated data from FIFO memory.

In step 5640, the emboard pointer is incremented. This will be discussed later (see steps 5720 to 5734).

In steps 5642 to 5854,
It is determined whether the control delayer signal RTC signal is detected.

In step 5642, it is determined whether there is a possibility of an R-C signal, that is, whether the data after ignoring the 2-byte data following EOL is EOL. If there is a possibility that it is an RTC signal, it is determined in steps 5644 to 5852 whether an RTC signal is detected. When the RTC signal is detected, image reception ends (step 5584).

Here, as the detection of the RTC signal, for example.

After rEOL J and 11 rQJs, "l"
is detected twice. In this case as well, each time EOL is detected, the following 2 bytes of data are ignored.

In steps 5644 to 5648,
Input 1 byte of demodulated data from FIFO memory.

In step 9850, the encoder pointer R
) Increment IHPTR. Here, R C
If there is no possibility of detecting a signal, that is, if data that is not EOL after ignoring the 2-byte data following EOL is detected, the process advances to step 585B.

In step 3858, the 2-byte data following the EOL signal, ie, the line number received this time, is input. In steps 5858 and 5880, the latest correctly received line number is input.

In step 5862, it is determined whether the currently received line number is 3 or more larger than the latest correctly received line number, that is, whether an image reception error has occurred. If the line number received this time is 3 or more larger than the latest correctly received line number, that is, if an image reception error has occurred, step 5e
Proceed to ss.

If the currently received line number is less than 3 greater than the most recently correctly received line number, ie, if the image reception is good, proceed to step 5664.

In step 98B4 and step 5886,
The line number received this time is stored in the line number storage memory 58.

In steps 5668 to 5ll180 shown in FIG. 28(2), demodulated data is input and decoded to create one line of recording data.

In steps 8688 to 5872,
Input 1 byte of demodulated data from FIFO memory.

In step 5874, the encoder pointer R
Increment MHPTR.

When the decoder requests byte data (step Sf!7
B) , l bytes of data are sent to the decoder (
Step 8878) Then, in step 8880, it is determined whether one line of decoding has been completed. If the decoding of one line has not yet been completed, the process proceeds to step 51388. On the other hand, if the decoding of one line has been completed, the process proceeds to step 9882.

In step 5882, one line of decoded data is input, the corresponding buffer is selected, and output is performed to that buffer (steps 5884 to 5898).
), when writing one line of data to the buffer,
Buffer 0. Buffer 1 is selected alternately. Then, the process advances to step 5632 to decode the next line.

If the image reception is not good, the process proceeds to step 569B shown in FIG. 26(3). First, a PIS signal is transmitted (steps 3898 to 5700), and transmission by the transmitting device is interrupted. After that, add 1 to the latest correctly received line number and send it to NS.
F signal and transmits the NSF signal (Step 2 5702 to Step 57013) At this time, as mentioned above, control such as fallback is also performed, and 8400 is set to the modem pointer RMDPTR.
H, encoder pointer RM) 8400H to IPTR
, 1 to BAF. Set REVRS to 0, perform various initializations, and receive images again.

Steps 5720 to 5734 shown in FIG. 2B (4) are a subroutine for incrementing the encoder pointer RMHPTH. When incrementing the encoder pointer RMHPTR, it is necessary to control it so that it does not overtake the modem pointer RMDPTR (steps 5722 to 5724).
.

In step 572B, the encoder pointer R
Increment NHP DingR. When the encoder pointer reaches the end of the FIFO memory, set the start address of the FIFO memory in the encoder pointer and set the REVRS flag to 0 (step 5).
72 days or step 5732).

In addition, various timers are running even while control is being performed, and for example, if the timer is over,
The line will be disconnected.

Fortress 17 Other Embodiments When configuring a facsimile machine with an automatic dialing function When one image transmission fails, it is also possible to select another line and perform automatic dialing.

[Effect] As explained above, according to the present invention, the conventional HDLC
Since a block transmission method according to a procedure is not adopted, even if a transmission error occurs, it is possible to retransmit the erroneous image from the corresponding line. This makes it possible to arbitrarily set the allowable error frequency, and it becomes possible to efficiently retransmit errors even when there is a delay on the line.

Since the present invention does not provide a method that fundamentally changes the conventional encoding method, it is easy to implement.

Furthermore, according to the present invention, when the encoded data is sequentially transmitted by the modem on the transmitting side, it is possible to always store already transmitted data for a certain number of bytes or more, which is acceptable. The delay on the line can be determined according to this number of bytes. In other words, by increasing the number of bytes, ili! f
Error retransmission is possible even if the length is longer.

From this point of view, the present invention is particularly effective for solving the problems related to item "133.3 Effects based on propagation delay characteristics of communication lines" mentioned in relation to "Prior art".

(Margin below)

[Brief explanation of drawings]

FIG. 1 is a diagram showing an HDLC frame format, and FIG. 2 is a diagram showing a specific example of error retransmission using the HDLC frame data shown in FIG. FIG. 3 is a diagram showing two (2) IDLC frames, and FIG. 4 is a diagram showing an example of HDLC frame transmission when there is a delay in the line. Fig. 5 is a schematic diagram showing the state when the receiving device fails to receive the training signal in the conventional error retransmission method, and Figs. 6 (1) to (3) explain the reception of the training signal and image signal. FIG. 7 is a flowchart showing a conventionally known control procedure for training reception/image signal reception; FIG. 8 is a schematic diagram explaining a control procedure according to an embodiment of the present invention. Figures 9 (1) to (7) are bit configuration diagrams showing specific examples of line numbers. Figure 10 shows an example in which encoded data and retransmission start addresses corresponding to each line number are stored in a memo for one month. 11 is a block diagram showing the transmitting side configuration of the facsimile apparatus according to the present embodiment, FIG. 12 is a flowchart showing the control procedure to be executed by the control circuit 7 shown in FIG. 11, and FIG. ) and (2) are diagrams explaining the relationship between FIFO memory and various pointers, Figure 14 is a diagram showing the number of bits and bytes sent in 3 seconds at each transmission speed, and Figure 15 (1) and ( 2) is a diagram showing the relationship between the FIF (I) and various pointers, Figure 16 is a flowchart showing an example of image reception control focusing on the case of error retransmission with fall pack, and Figure 17 is a diagram showing the relationship between the FIF (I) and various pointers. 30 to notify the sender of the retransmission start address and information on the presence or absence of fall pack.
A diagram showing an example of the 0b/S signal, Fig. 18 (1) to (3)
) is a diagram illustrating a method of setting a retransmission start address, FIG. 19 is a block diagram showing an embodiment of the sending side of a facsimile apparatus to which the present invention is applied, and FIG. 20 is a configuration diagram showing a retransmission start address storage memory. FIG. 21 is a flowchart showing a general encoding process (ie, main process) of the control circuit 30 shown in FIG. 19. 22 (1) to (12) are detailed encoding processing (i.e. details of main processing) of the control circuit 30 shown in FIG. 19.
23 is a flowchart showing the encoded data transmission procedure (i.e., interwoven processing) controlled by the control circuit 30 shown in FIG. 19.
Flowchart showing. FIG. 24 is a block diagram showing an embodiment of the receiving side of a facsimile machine to which the present invention is applied. 25 is a flowchart showing demodulated data reception processing (that is, interwoven processing) controlled by the control circuit 6B shown in FIG. 24, and FIG. 26 (1) to (4) are the control circuits shown in FIG. 24. B
8 is a flowchart showing the decoding process (i.e., main process) controlled by 8. 2... NCU, 4... Hybrid circuit, 6... Retransmission request signal detection circuit, 8... Binary signal receiving circuit, 10... Reading device, 12... Double buffer circuit, 14. ...Line number counter circuit, 1B...
Encoding circuit, 18... FIFO memory. 20...Retransmission start address storage memory, 22...P
/S conversion circuit, 24...Modulator, 2B...DON signal sending circuit, 28...Addition circuit. 30...control circuit. 40...NCU, 42...Hybrid circuit, 44...Signal presence/absence detection circuit, 4B...Demodulator, 48...S/P conversion circuit, 50...NSF signal sending circuit. 52...Retransmission request signal sending port i! 8154... Addition circuit, 56... FIFO memory, 58... Line number storage memory, 60... Decoder, 62... Double buff circuit, 64... Recording device, 66... Control circuit , 67...NCU, 68...Hybrid circuit, B9...Binary signal sending circuit. 70... Tonal signal sending circuit. 71...Addition circuit. 72... Tonal signal detection circuit 73... Binary signal detection circuit 74... Start button 75... Error retransmission mode selection switch. 7B...Control circuit. 77...Mode conversion notification sound generation circuit. Fig. 1 Fig. 2 Fig. 3 Section l Tf 1 V v Fig. 7 Fig. 8 Fig. 9 Line number -2 (4) ooooooo + ooooo + o + line number -3 (5) ooooooo + oooooox + line number 10θ (7) ooooooo + xoo1oo + 1st O
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Claims (1)

[Scope of Claims] An image communication device that divides image information into a plurality of line information and transmits the divided line information, comprising means for storing a predetermined amount of the already sent line information, and transmitting the line information from the communication partner device. An image communication device characterized in that the transmitted line information is retransmitted in response to a retransmission request.