JPS61182254A - Manufacture of semiconductor integrated circuit device - Google Patents
Manufacture of semiconductor integrated circuit deviceInfo
- Publication number
- JPS61182254A JPS61182254A JP60021673A JP2167385A JPS61182254A JP S61182254 A JPS61182254 A JP S61182254A JP 60021673 A JP60021673 A JP 60021673A JP 2167385 A JP2167385 A JP 2167385A JP S61182254 A JPS61182254 A JP S61182254A
- Authority
- JP
- Japan
- Prior art keywords
- semiconductor region
- semiconductor
- forming
- diffusion
- film
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 101
- 238000004519 manufacturing process Methods 0.000 title claims description 12
- 238000009792 diffusion process Methods 0.000 claims abstract description 38
- 239000012535 impurity Substances 0.000 claims abstract description 30
- 239000000758 substrate Substances 0.000 claims abstract description 9
- 230000002265 prevention Effects 0.000 claims description 22
- 238000000034 method Methods 0.000 claims description 6
- 230000006378 damage Effects 0.000 abstract description 5
- 230000003449 preventive effect Effects 0.000 abstract 2
- 230000003416 augmentation Effects 0.000 abstract 1
- 230000002401 inhibitory effect Effects 0.000 abstract 1
- 150000002500 ions Chemical class 0.000 abstract 1
- 239000010410 layer Substances 0.000 description 21
- 238000005516 engineering process Methods 0.000 description 11
- 229910052782 aluminium Inorganic materials 0.000 description 9
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 9
- 108091006146 Channels Proteins 0.000 description 3
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 3
- 230000015572 biosynthetic process Effects 0.000 description 3
- 230000003647 oxidation Effects 0.000 description 3
- 238000007254 oxidation reaction Methods 0.000 description 3
- 229910052814 silicon oxide Inorganic materials 0.000 description 3
- 230000000295 complement effect Effects 0.000 description 2
- 230000007423 decrease Effects 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 238000005530 etching Methods 0.000 description 2
- 238000005468 ion implantation Methods 0.000 description 2
- 229910000838 Al alloy Inorganic materials 0.000 description 1
- 229910020968 MoSi2 Inorganic materials 0.000 description 1
- 102000004129 N-Type Calcium Channels Human genes 0.000 description 1
- 108090000699 N-Type Calcium Channels Proteins 0.000 description 1
- 229910052581 Si3N4 Inorganic materials 0.000 description 1
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- CSDREXVUYHZDNP-UHFFFAOYSA-N alumanylidynesilicon Chemical compound [Al].[Si] CSDREXVUYHZDNP-UHFFFAOYSA-N 0.000 description 1
- 230000006866 deterioration Effects 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 239000011229 interlayer Substances 0.000 description 1
- 238000002844 melting Methods 0.000 description 1
- 230000008018 melting Effects 0.000 description 1
- 229910052751 metal Inorganic materials 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 229910021421 monocrystalline silicon Inorganic materials 0.000 description 1
- 229910052698 phosphorus Inorganic materials 0.000 description 1
- 239000011574 phosphorus Substances 0.000 description 1
- -1 phosphorus ions Chemical class 0.000 description 1
- 229920002120 photoresistant polymer Polymers 0.000 description 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 1
- 229910021332 silicide Inorganic materials 0.000 description 1
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 1
- 238000004544 sputter deposition Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/8238—Complementary field-effect transistors, e.g. CMOS
- H01L21/823814—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the source or drain structures, e.g. specific source or drain implants or silicided source or drain structures or raised source or drain structures
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
- H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
- H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
- H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
- H01L27/092—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors
- H01L27/0928—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors comprising both N- and P- wells in the substrate, e.g. twin-tub
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
Abstract
Description
【発明の詳細な説明】
［技術分野］
本発明は、半導体集積回路装置に関するものであり、特
に、半導体領域と導電層との電気的な接続部を有する半
導体集積回路装置に適用して有効な技術に関するもので
ある。Detailed Description of the Invention [Technical Field] The present invention relates to a semiconductor integrated circuit device, and in particular, to a semiconductor integrated circuit device having an electrical connection between a semiconductor region and a conductive layer. It's about technology.
［背景技術］
ＭＩＳＦＥＴのソース領域又はトレイン領域として使用
される半導体領域は、チャネル形成領域側への拡散を抑
制し、短チヤネル化を図るために、接合深さを残くする
傾向にある。この半導体領域には、半導体集積回路装置
の動作速度の高速化を図るために、低抵抗値のアルミニ
ウム膜が接続されている。[Background Art] A semiconductor region used as a source region or a train region of a MISFET tends to have a junction depth left in order to suppress diffusion toward the channel formation region and shorten the channel. An aluminum film having a low resistance value is connected to this semiconductor region in order to increase the operating speed of the semiconductor integrated circuit device.
しかしながら、接合深さの浅い半導体領域は、オーミッ
ク性を良くする熱処理工程のために、シリコン−アルミ
ニウム合金の形成、所謂、アルミスパイクでｐｎ接合部
が破壊され易い。However, in a semiconductor region with a shallow junction depth, the pn junction is likely to be destroyed by the formation of a silicon-aluminum alloy, a so-called aluminum spike, due to the heat treatment process that improves ohmic properties.
そこで５前記半導体領域は、アルミニウム膜との接続部
分の接合深さを深くし、ｐ ＩＩ接合部にアルミスパイ
クが到達しないように構成されている。Therefore, the semiconductor region 5 is configured to have a deep junction depth at the connection portion with the aluminum film so that the aluminum spike does not reach the p II junction.
ｎ型の半導体領域は、その不純物の拡散速度がｒ１型の
不純物に比へて速いので、アルミスパイクによるｐ ｒ
ｌ接合部の破壊が極めて少ない。このため、接合深さの
深い部分を有する半導体領域は、ｒｌ型の半導体領域に
適用されている。Since the diffusion rate of impurities in the n-type semiconductor region is faster than that of r1-type impurities, the p r
1. Breakage of the joint is extremely rare. Therefore, a semiconductor region having a deep junction depth is applied to an rl type semiconductor region.
接合深さの深い部分を有するｎ型の半導体領域は、半導
体領域の上部の層間絶縁膜に形成される接続孔を通して
１１型の不純物が導入され、該不純物に引き伸し拡散を
施して形成されている。An n-type semiconductor region having a deep junction depth is formed by introducing an 11-type impurity through a connection hole formed in an interlayer insulating film above the semiconductor region, and stretching and diffusing the impurity. ing.
しかしながら、相補型のＭＴＳＦＥＴを構成する場合に
、ｎ型の不純物がその引き伸し拡散工程中に外部雰囲気
中に拡散し、該不純物が接続孔を通してｎ型の半導体領
域の主面部に拡散される。However, when configuring a complementary MTSFET, n-type impurities are diffused into the external atmosphere during the extension diffusion process, and the impurities are diffused into the main surface of the n-type semiconductor region through the connection hole. .
これによって、その不純物濃度が低下するので、ｎ型の
半導体領域とアルミニウム膜との接続部分における抵抗
値が４００〜５００［０７μｍ２］程度に増大してしま
う。このため、本発明者は、半導体集積回路装置の動作
速度の高速化を図ることができないという問題点を見出
した。As a result, the impurity concentration decreases, so that the resistance value at the connection portion between the n-type semiconductor region and the aluminum film increases to about 400 to 500 [07 μm 2 ]. For this reason, the inventors of the present invention have discovered a problem in that it is not possible to increase the operating speed of the semiconductor integrated circuit device.
なお、アルミスパイクを防止する技術は、例えば、日経
マグロウヒル社発行「日経エレクトロニクス別冊マイク
ロデバ、イセズＪ １９８３年８月２；３日号、Ｐ１２
２に記載されている。The technology to prevent aluminum spikes is described, for example, in "Nikkei Electronics Special Issue Microdevice, Isezu J, August 2nd, 3rd, 1983 issue, P12, published by Nikkei McGraw-Hill.
It is described in 2.
［発明の目的コ
３一
本発明の目的は、半導体領域と導電層との接続部におけ
る抵抗値を低減し、半導体集積口！８装置の動作速度の
高速化を図ることが可能な技術に提供することにある。[Objective of the Invention 31 An object of the present invention is to reduce the resistance value at the connection portion between the semiconductor region and the conductive layer, and to reduce the resistance value at the connection portion between the semiconductor region and the conductive layer. The purpose of this invention is to provide a technology that can increase the operating speed of 8 devices.
本発明の前記ならびにその他の目的と新規な特徴は、本
町絹書の記述及び添付図面によって明らかになるであろ
う。The above and other objects and novel features of the present invention will become clear from the description of Honcho Kinusho and the accompanying drawings.
［発明の概要］
本願において開示される発明のうち、代表的なものの概
要を簡単に説明すれば、下記のとおりである。[Summary of the Invention] A brief overview of typical inventions disclosed in this application is as follows.
すなわち、接合深さの深い部分に有する半導体領域と導
電層との接続部を有する半導体装積回路装置において、
前記接続部に拡散防１Ｆ膜を形成し、接合深さの深い部
分を形成する不純物の拡散に防ｔ［ｚする・
これによって、前記不純物が反対導電型の半導体領域の
主面部に拡散することを防１にし、接続部における抵抗
値の増加を抑制することができるので、半導体集積回路
装置の動作速度の高速化に図−４＝
ることかできる。That is, in a semiconductor integrated circuit device having a connection portion between a semiconductor region and a conductive layer in a deep junction depth portion,
A diffusion-preventing 1F film is formed on the connection portion to prevent diffusion of impurities forming a deep junction portion. This prevents the impurities from diffusing into the main surface of the semiconductor region of the opposite conductivity type. Since it is possible to prevent 1 and suppress the increase in resistance value at the connection portion, it is possible to increase the operating speed of the semiconductor integrated circuit device.
以下、本発明の構成について、本発明ｋ、相補型のＭ）
ＳＦＥＴを備えた半導体集積回路装置に適用した一実施
例とともに説明する。Hereinafter, regarding the configuration of the present invention, the present invention k, the complementary type M)
The present invention will be described along with an embodiment applied to a semiconductor integrated circuit device including an SFET.
［実施例］
第１図乃至第７図は、本発明の一実施例の製造方法を説
明するための各製造工程における半導体集積回路装置の
要部断面図である。[Embodiment] FIGS. 1 to 7 are sectional views of main parts of a semiconductor integrated circuit device in each manufacturing process for explaining a manufacturing method according to an embodiment of the present invention.
なお、実施例の全図において、同一機能を有するものは
同一符号を付け、そのくり返しの説明は省略する。In addition, in all the figures of the embodiment, parts having the same functions are given the same reference numerals, and repeated explanations thereof will be omitted.
ます、単結晶シリコンからなるｌ〕−型の半導体基板１
を用意する。この半導体基板ｌの所定の主面部にｎ−型
のウェル領域２を形成する。1]-type semiconductor substrate 1 made of single crystal silicon
Prepare. An n-type well region 2 is formed in a predetermined main surface portion of this semiconductor substrate l.
そして、半導体素子形成領域以外の半導体基板１及びウ
ェル領域２の主面上部に、シリコンの選択的な熱酸化技
術によって、フィールド絶縁膜３を形成する。該フィー
ルド絶縁膜３の形成と略同−製造工程によって、その下
部の半導体基板１の主面部に、ｎ型のチャネルストッパ
領域４を形成する。前記フ、イールド絶縁膜３及びチャ
ネルストッパ領域４は、半導体素子間な電気的に分離す
るように構成される。Then, a field insulating film 3 is formed on the main surface of the semiconductor substrate 1 and the well region 2 other than the semiconductor element formation region by selective thermal oxidation of silicon. By using substantially the same manufacturing process as that for forming the field insulating film 3, an n-type channel stopper region 4 is formed on the main surface of the semiconductor substrate 1 under the field insulating film 3. The yield insulating film 3 and the channel stopper region 4 are configured to electrically isolate the semiconductor elements.
この後、第１図に示すように、半導体素子形成領域の半
導体基板１及びウェル領域２の主面」一部に、絶縁膜５
を形成する。該絶縁膜５は、主として、ＭＴＳＦＥＴの
ケート絶縁膜を構成するようになっており、例えは、熱
酸化技術によって形成される酸化シリコン膜を用いる。After this, as shown in FIG.
form. The insulating film 5 mainly constitutes a gate insulating film of the MTSFET, and uses, for example, a silicon oxide film formed by thermal oxidation technology.
第１図に示す絶縁膜５を形成する工程の後に、絶縁膜５
の所定の上部に導電層６を形成する。該導電層６は、主
として、ＭＩＳＦＥＴのケート電極に構成するようにな
っており、例えば、ＣＶＤ技術によって形成される多結
晶シリコン膜を用いる。該導電層６は、製造工程におけ
る第１層目の導電層形成工程によって形成される。After the step of forming the insulating film 5 shown in FIG.
A conductive layer 6 is formed on a predetermined upper part of. The conductive layer 6 is mainly configured as a gate electrode of a MISFET, and is made of, for example, a polycrystalline silicon film formed by CVD technology. The conductive layer 6 is formed by a first conductive layer forming step in the manufacturing process.
また、導電層６は、高融点金属膜（Ｍｏ、Ｔａ、Ｔｊ。Further, the conductive layer 6 is a high melting point metal film (Mo, Ta, Tj, etc.).
Ｗ）、シリサイド膜（ＭｏＳｉ２．Ｔａ５ｊ２．Ｔｉ５
ｉ２ｒＷＳ、ｉ２）又はその組合せ膜によって形成して
もよい。W), silicide film (MoSi2.Ta5j2.Ti5
It may be formed by i2rWS, i2) or a combination thereof.
そして、第２図に示すように、導電層６の両側部の半導
体基板ｌの主面部に丁１゛型の半導体領域７を形成し、
導電層６の両側部のウェル領域２の主面部に、Ｐ＋型の
半導体領域８を形成する。半導体領域７，８は、主とし
て、ＭＴＳＦＥＴのソース領域又はトレイン領域を構成
するようになっている。Then, as shown in FIG. 2, a diagonal-shaped semiconductor region 7 is formed on the main surface of the semiconductor substrate l on both sides of the conductive layer 6,
P+ type semiconductor regions 8 are formed on the main surface of the well region 2 on both sides of the conductive layer 6. The semiconductor regions 7 and 8 mainly constitute the source region or train region of the MTSFET.
半導体領域７，８は、例えば、イオン打込み技術によっ
て所定の不純物を導入し、該導入された不純物に引き伸
し拡散を施して形成する。半導体領域７は、例えば、
０．２ ［μｒｎ］μｍ］程度深さで形成し、半導体領
域８は、例えば、０．４［μｍ］程度の接合深さで形成
する。The semiconductor regions 7 and 8 are formed, for example, by introducing predetermined impurities using an ion implantation technique and by stretching and diffusing the introduced impurities. The semiconductor region 7 is, for example,
The semiconductor region 8 is formed to have a junction depth of, for example, about 0.4 [μm].
ｎチャネルＭＴ ５ＦＥＴＱｎは、主として、半導体基
板１、絶縁膜５、導電層６及び一対の半導体領域７によ
って略構成されている。The n-channel MT 5FETQn is mainly composed of a semiconductor substrate 1, an insulating film 5, a conductive layer 6, and a pair of semiconductor regions 7.
ＰチャネルＭＩＳＦＥＴＱｐは、主として、ウェル領域
２、絶縁膜５、導電層６及び一対の半導体領域８によっ
て構成されている。P-channel MISFET Qp is mainly composed of a well region 2, an insulating film 5, a conductive layer 6, and a pair of semiconductor regions 8.
第２図に示す半導体領域７，８を形成する工程の後に、
第３図に示すように、ＭＩＳＦＥＴＱｎ。After the step of forming semiconductor regions 7 and 8 shown in FIG.
As shown in FIG. 3, MISFETQn.
ＱＰ等の半導体素子を覆うように絶縁膜９を形成する。An insulating film 9 is formed to cover a semiconductor element such as a QP.
絶縁膜９は、主として、半導体素子とその上部に形成さ
れる導電層との電気的な分離をするように構成されてい
る。絶縁膜９は、例えば、ＣＶＤ技術で形成した酸化シ
リコン膜を用い、その膜厚を６００［ｎｒｎｌ程度に形
成する。The insulating film 9 is mainly configured to electrically isolate the semiconductor element and the conductive layer formed thereon. The insulating film 9 is formed using, for example, a silicon oxide film formed by CVD technology, and has a thickness of about 600 [nrnl].
第３図に示す絶縁膜９を形成する工程の後に、半導体領
域７，８の所定の上部の絶縁膜５，９を除去し、第４図
に示すように、接続孔１０ｔｉ−形成する。接続孔１０
は、フォトレジスト膜等のエツチング用マスクを用い、
例えば、異方性エツチング技術で形成する。After the step of forming the insulating film 9 shown in FIG. 3, the insulating films 5 and 9 on predetermined upper portions of the semiconductor regions 7 and 8 are removed, and connection holes 10ti are formed as shown in FIG. Connection hole 10
Using an etching mask such as a photoresist film,
For example, it is formed using an anisotropic etching technique.
第４図に示す接続孔ＩＯを形成する工程の後に、第５図
に示すように、接続孔１０部分の半導体領域７，８の主
面上部に、拡散防止膜１１を形成する。また、拡散防止
膜１１は、接続孔１０を形成する工程において、絶縁膜
５，９を除去する際にその一部を残すことにより形成し
てもよい。After the step of forming the connection hole IO shown in FIG. 4, a diffusion prevention film 11 is formed on the main surfaces of the semiconductor regions 7 and 8 in the connection hole 10 portion, as shown in FIG. Further, the diffusion prevention film 11 may be formed by leaving a portion of the insulating films 5 and 9 when removing them in the step of forming the connection hole 10.
拡散防止膜ｌｌは、半導体領域７に接合深さの深い部分
を形成するために導入される不純物が。The diffusion prevention film 11 contains impurities introduced into the semiconductor region 7 to form a deep junction portion.
その引き伸し拡散工程中に外部雰囲気中に拡散しないよ
うにするためのものである。また、拡散防Ｉト膜１１は
、外部雰囲気中に拡散する不純物が半導体領域８の主面
部に拡散しないようにするためのものである。This is to prevent diffusion into the external atmosphere during the stretching diffusion process. Further, the diffusion prevention film 11 is provided to prevent impurities that diffuse into the external atmosphere from diffusing into the main surface of the semiconductor region 8 .
また、拡散防止膜１１は、前記不純物の導入による半導
体領域７の主面部のダメージを抑制するようになってい
る。Furthermore, the diffusion prevention film 11 is designed to suppress damage to the main surface portion of the semiconductor region 7 due to the introduction of the impurity.
拡散防止膜１１は、例えば、９００［’Ｃ］程度のの温
度と２０ ［ｍ１ｎｌ程度の時間の熱酸化技術登用い、
その膜厚を１０［ｎｍ］程度で形成する。The diffusion prevention film 11 is formed using thermal oxidation technology at a temperature of about 900 ['C] and a time of about 20 [m1nl], for example.
The film thickness is formed to be about 10 [nm].
また、拡散防止膜１１は、例えば、ＣＶＤ技術で形成し
た酸化シリコン膜、窒化シリコン膜等で形成してもよい
。Furthermore, the diffusion prevention film 11 may be formed of, for example, a silicon oxide film, a silicon nitride film, or the like formed by CVD technology.
第５図に示す拡散防止膜１１を形成する工程の後に、接
合深さの深い部分を形成するために、拡散防止膜１１を
通して半導体領域７の主面部のみにｎ型の不純物を導入
する。該不純物は、例えば、５ ＸＩＯ” ［ａｔｏ
ｍｓ／ｃｍ” １程度の不純物濃度のリンイオンを５０
［ＫｅＶ］程度のエネルギのイオン打込み技術で導入す
ればよい。After the step of forming the diffusion prevention film 11 shown in FIG. 5, n-type impurities are introduced only into the main surface of the semiconductor region 7 through the diffusion prevention film 11 in order to form a deep junction. The impurity is, for example, 5XIO” [ato
50 ms/cm" of phosphorus ions with an impurity concentration of about 1
It may be introduced by ion implantation technology with an energy of about [KeV].
この不純物は、拡散防止膜１１を通して導入しているの
で、導入による半導体領域７の主面部のダメージを抑制
することができる。Since this impurity is introduced through the diffusion prevention film 11, damage to the main surface of the semiconductor region 7 due to the introduction can be suppressed.
この後、前記導入された不純物に引き伸し拡散を施し、
第６図に示すように、半導体領域７と同一導電型で電気
的に接続され、それよりも接合深さの深いｒｌ”型の半
導体領域１２を形成する。半導体領域１２は、ＭＩ ５
ＦＥＴＱｎのソース領域又はドレイン領域の一部として
使用されるもので、アルミスパイクによるｐｎ接合部の
破壊を抑制するためのものである。半導体領域１２は、
例えば、０．４〜０．５［μｍｌ程度の接合深さで形成
する。After this, the introduced impurity is subjected to stretching diffusion,
As shown in FIG. 6, an rl'' type semiconductor region 12 is formed which is of the same conductivity type as the semiconductor region 7, is electrically connected, and has a deeper junction depth than the semiconductor region 7.
It is used as part of the source region or drain region of FETQn, and is intended to suppress destruction of the pn junction due to aluminum spikes. The semiconductor region 12 is
For example, it is formed with a junction depth of about 0.4 to 0.5 μml.
前記半導体領域１２は、例えば、９５０［℃ｌ程度の温
度と２０ ［ｍ１ｎ１程度の時間の引き伸し拡散によっ
て形成する。The semiconductor region 12 is formed, for example, by stretching diffusion at a temperature of about 950° C.l and for a time of about 20 m1n1.
° そして、半導体領域１２を形成する【１型の不純
物は、拡散防止膜１１が設けられているので、引き伸し
拡散工程中に半導体領域７部分から外部雰囲気中に拡散
することを防止できる。さらに、たとえ外部雰囲気中に
ｎ型の不純物が拡散しても、拡散防止膜１１が設けられ
ているので、接続孔１０を通して半導体領域８の主面部
にそれが拡散することを防止できる。すなわち、接続孔
１０部分における半導体領域８の主面部の不純物濃度の
低下を抑制し、アルミニウム膜との接続部の抵抗値を例
えば３０［０７μｍ２］程度の小さな値にすることがで
きる。これによって、半導体集積回路装置の全体の配線
抵抗値を低減することができるので、動作速度の高速化
を図ることができる。Since the diffusion prevention film 11 is provided, the type 1 impurity forming the semiconductor region 12 can be prevented from diffusing from the semiconductor region 7 portion into the external atmosphere during the stretching diffusion process. Furthermore, even if n-type impurities diffuse into the external atmosphere, the diffusion prevention film 11 prevents them from diffusing into the main surface of the semiconductor region 8 through the connection hole 10. That is, it is possible to suppress a decrease in the impurity concentration of the main surface of the semiconductor region 8 in the connection hole 10 portion, and to reduce the resistance value of the connection portion with the aluminum film to a small value of, for example, about 30 [07 μm 2 ]. As a result, the overall wiring resistance value of the semiconductor integrated circuit device can be reduced, so that the operating speed can be increased.
第６図に示す半導体領域１２を形成する工程の後に、拡
散防止膜１１を除去する。After the step of forming the semiconductor region 12 shown in FIG. 6, the diffusion prevention film 11 is removed.
この後、第７図に示すように、接続孔１０を通して半導
体領域７，８と電気的に接続するように、絶縁膜９の上
部に導電層１３を形成する。導電層１３は、例えば、ス
パッタ技術により形成したアルミラム膜を用いる。この
導電層１３は、製造工程における第２層目の導電層形成
工程によって形成される。Thereafter, as shown in FIG. 7, a conductive layer 13 is formed on the insulating film 9 so as to be electrically connected to the semiconductor regions 7 and 8 through the connection hole 10. For the conductive layer 13, for example, an aluminum film formed by sputtering technology is used. This conductive layer 13 is formed by a second conductive layer forming step in the manufacturing process.
前述したように、拡散防止膜１１を形成したことにより
、接続孔１０部分における半導体領域８の主面部は、半
導体領域１２を形成する不純物の拡散がなくなるので、
半導体領域８と導電層１３との接続部における抵抗値を
低減することができる。As described above, by forming the diffusion prevention film 11, the main surface of the semiconductor region 8 in the connection hole 10 part is free from diffusion of impurities forming the semiconductor region 12.
The resistance value at the connection between semiconductor region 8 and conductive layer 13 can be reduced.
なお、前記実施例は、本発明を、ｎ型の半導体領域７に
接合深さが深い半導体領域１２を設けた例に適用したが
、ｐ型の半導体領域８に接合深さの深い半導体領域を設
けた例に適用してもよい。In the above embodiment, the present invention is applied to an example in which the semiconductor region 12 with a deep junction depth is provided in the n-type semiconductor region 7, but the semiconductor region 12 with a deep junction depth is provided in the p-type semiconductor region 8. It may be applied to the examples provided.
［効果］
以上説明したように、本願において開示された新規な技
術によれば、以下に述べる効果を得ることができる。[Effects] As explained above, according to the novel technology disclosed in this application, the following effects can be obtained.
（１）接合深さの深い部分を有する半導体領域と導電層
との接続部を有する半導体集積回路装置において、前記
接続部に拡散防ＩＦ膜を形成し、接合深さの深い部分を
形成する不純物の拡散を防止することによって、前記不
純物が反対導電型の半導１２一
体領域の主面部に拡散することを防止できるので、接続
部における抵抗値の増加を抑制することができる。(1) In a semiconductor integrated circuit device having a connection portion between a semiconductor region and a conductive layer having a deep junction depth, a diffusion-prevention IF film is formed in the connection portion, and an impurity forming the deep junction portion is formed. By preventing the diffusion of the impurity, it is possible to prevent the impurity from diffusing into the main surface portion of the integral region of the semiconductor 12 of the opposite conductivity type, so that an increase in the resistance value at the connection portion can be suppressed.
（２）前記（１）により、半導体集積回路装置の動作速
度の高速化を図ることができる。(2) According to (1) above, the operating speed of the semiconductor integrated circuit device can be increased.
（３）前記（１）により、拡散防止膜を通して前記不純
物髭導入するので、半導体基板又はウェル領域の主面部
のダメージを抑制することができる。(3) According to (1) above, since the impurity whiskers are introduced through the diffusion prevention film, damage to the semiconductor substrate or the main surface of the well region can be suppressed.
（４）前記（３）により、半導体集積回路装置の電気的
特性の劣化を抑制することができる。(4) According to (3) above, deterioration of the electrical characteristics of the semiconductor integrated circuit device can be suppressed.
以上、本発明者によってなされた発明を、前記実施例に
もとすき具体的に説明したが１本発明は、前記実施例に
限定されるものではなく、その要旨を逸脱しない範囲に
おいて、種々変形し得ることは勿論である。As above, the invention made by the present inventor has been specifically explained in the above-mentioned embodiments. However, the present invention is not limited to the above-mentioned embodiments, and various modifications may be made without departing from the gist thereof. Of course it is possible.
第１図乃至第７図は、本発明の一実施例の製造方法を説
明するための各製造工程における半導体集積回路装置の
要部断面図である。
図中、７，８．１２・・・半導体領域、９・・・絶縁膜
、１０・・・接続孔、１１・・・拡散防１１−膜、１３
・・・導電層である。1 to 7 are sectional views of essential parts of a semiconductor integrated circuit device in each manufacturing process for explaining a manufacturing method according to an embodiment of the present invention. In the figure, 7, 8. 12... Semiconductor region, 9... Insulating film, 10... Connection hole, 11... Diffusion prevention 11-film, 13
...A conductive layer.
Claims (1)
電型の第１の半導体領域と第２導電型の第２の半導体領
域を形成する工程と、該第１の半導体領域及び第２の半
導体領域の上部に絶縁膜を形成する工程と、前記第１の
半導体領域及び第２の半導体領域の上部の前記絶縁膜を
除去して接続孔を形成する工程と、該接続孔部の第１の
半導体領域及び第２の半導体領域の上部に、不純物の拡
散を防止する拡散防止膜を形成する工程と、該拡散防止
膜を通して第１の半導体領域の主面部に第１導電型の不
純物を導入し、第１の半導体領域と電気的に接続し、か
つ、それよりも接合深さの深い第３の半導体領域を形成
する工程と、前記拡散防止膜を除去する工程と、前記接
続孔を通して、前記第１の半導体領域と第２の半導体領
域のそれぞれと電気的に接続するように、前記絶縁膜の
上部に導電層を形成する工程とを具備したことを特徴と
する半導体集積回路装置の製造方法。 ２、前記第１の半導体領域及び第３の半導体領域は、ｎ
型の半導体領域であり、前記第２の半導体領域は、ｐ型
の半導体領域であることを特徴とする特許請求の範囲第
１項に記載の半導体集積回路装置の製造方法。 ３、前記拡散防止膜は、前記絶縁膜に比べて薄く構成さ
れてなることを特徴とする特許請求の範囲第１項に記載
の半導体集積回路装置の製造方法。 ４、前記拡散防止膜は、前記絶縁膜を除去して接続孔を
形成する工程において、前記絶縁膜の一部を残すことに
より形成することを特徴とする特許請求の範囲第１項に
記載の半導体集積回路装置の製造方法。[Claims] 1. A step of forming a first semiconductor region of a first conductivity type and a second semiconductor region of a second conductivity type in a semiconductor substrate or well region of a predetermined conductivity type; forming an insulating film over the semiconductor region and the second semiconductor region; removing the insulating film over the first semiconductor region and the second semiconductor region to form a contact hole; forming a diffusion prevention film for preventing diffusion of impurities over the first semiconductor region and the second semiconductor region in the connection hole; and forming a first diffusion prevention film on the main surface of the first semiconductor region through the diffusion prevention film. a step of introducing a conductivity type impurity to form a third semiconductor region that is electrically connected to the first semiconductor region and has a deeper junction depth; and a step of removing the diffusion prevention film. , forming a conductive layer on the insulating film so as to be electrically connected to each of the first semiconductor region and the second semiconductor region through the connection hole. A method for manufacturing a semiconductor integrated circuit device. 2. The first semiconductor region and the third semiconductor region are n
2. The method of manufacturing a semiconductor integrated circuit device according to claim 1, wherein the second semiconductor region is a p-type semiconductor region. 3. The method of manufacturing a semiconductor integrated circuit device according to claim 1, wherein the diffusion prevention film is thinner than the insulating film. 4. The diffusion prevention film is formed by leaving a part of the insulating film in the process of removing the insulating film and forming the connection hole. A method for manufacturing a semiconductor integrated circuit device.
Priority Applications (6)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP60021673A JP2509173B2 (en) | 1985-02-08 | 1985-02-08 | Method of manufacturing semiconductor integrated circuit device having complementary MISFET |
| KR1019850008576A KR940006668B1 (en) | 1984-11-22 | 1985-11-16 | Manufacturing method of semiconductor ic device |
| CN85109742A CN85109742B (en) | 1984-11-22 | 1985-11-22 | Method for manufacturing semiconductor integrated circuit device |
| US06/800,954 US4734383A (en) | 1984-11-22 | 1985-11-22 | Fabricating semiconductor devices to prevent alloy spiking |
| EP85114857A EP0183204A3 (en) | 1984-11-22 | 1985-11-22 | Process for fabricating semiconductor integrated circuit devices |
| US07/351,323 US5055420A (en) | 1984-11-22 | 1989-05-09 | Process for fabricating semiconductor integrated circuit devices |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP60021673A JP2509173B2 (en) | 1985-02-08 | 1985-02-08 | Method of manufacturing semiconductor integrated circuit device having complementary MISFET |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS61182254A true JPS61182254A (en) | 1986-08-14 |
| JP2509173B2 JP2509173B2 (en) | 1996-06-19 |
Family
ID=12061565
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP60021673A Expired - Lifetime JP2509173B2 (en) | 1984-11-22 | 1985-02-08 | Method of manufacturing semiconductor integrated circuit device having complementary MISFET |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2509173B2 (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100320436B1 (en) * | 1999-12-03 | 2002-01-16 | 박종섭 | Method for manufacturing mosfet |
| JP4876193B1 (en) * | 2011-08-08 | 2012-02-15 | 渡 高橋 | Pollen mating machine |
Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS53115173A (en) * | 1977-03-18 | 1978-10-07 | Hitachi Ltd | Production of semiconductor device |
| JPS5424269A (en) * | 1977-07-26 | 1979-02-23 | Hitachi Ltd | Catalytic reactor |
| JPS5825258A (en) * | 1981-08-07 | 1983-02-15 | Mitsubishi Electric Corp | Complementary mos ic |
| JPS5972759A (en) * | 1982-10-20 | 1984-04-24 | Toshiba Corp | Semiconductor device and manufacture thereof |
| JPS59197161A (en) * | 1983-04-22 | 1984-11-08 | Toshiba Corp | Manufacture of semiconductor device |
-
1985
- 1985-02-08 JP JP60021673A patent/JP2509173B2/en not_active Expired - Lifetime
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS53115173A (en) * | 1977-03-18 | 1978-10-07 | Hitachi Ltd | Production of semiconductor device |
| JPS5424269A (en) * | 1977-07-26 | 1979-02-23 | Hitachi Ltd | Catalytic reactor |
| JPS5825258A (en) * | 1981-08-07 | 1983-02-15 | Mitsubishi Electric Corp | Complementary mos ic |
| JPS5972759A (en) * | 1982-10-20 | 1984-04-24 | Toshiba Corp | Semiconductor device and manufacture thereof |
| JPS59197161A (en) * | 1983-04-22 | 1984-11-08 | Toshiba Corp | Manufacture of semiconductor device |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100320436B1 (en) * | 1999-12-03 | 2002-01-16 | 박종섭 | Method for manufacturing mosfet |
| JP4876193B1 (en) * | 2011-08-08 | 2012-02-15 | 渡 高橋 | Pollen mating machine |
Also Published As
| Publication number | Publication date |
|---|---|
| JP2509173B2 (en) | 1996-06-19 |
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