JPS61171168A - Nonvolatile semiconductor memory device - Google Patents

Abstract

PURPOSE:To increase the writing amount by a method wherein an element isolating region surrounding the element region and having unevenness in the top and a control gate formed via insulation film on a floating gate extending from the element region to the part of unevenness of the element-isolating region. CONSTITUTION:The element-isolating region 1a having unevenness by providing the top with recesses, the floating gate 2a spreading over this top until covering the recesses, and the control gate 4a formed thereon via insulation film 3a. This construction can increase the area of the floating gate and those of the floating gate and the control gate opposed via insulation film and sufficiently raise the floating gate potential by capacitive coupling with a large amount of injectable carriers.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to a method of manufacturing a nonvolatile semiconductor memory device.

[Technical background of the invention and its problems]

As a non-volatile semiconductor memory device, 't'' lPROM -?
In @BFROM, which has various E"P (capital) M, etc., the information content is determined and written by the magnitude of the current flowing in the channel formed on the opposing semiconductor surface depending on the band and solder state of the floating gate. For example, avalanche breakdown of the drain junction occurs on the semiconductor substrate surface,
This is done by injecting the high-energy carriers generated therein into the floating gate via the insulating film and the barrier on the semiconductor surface. Rewriting λ is performed by exciting and expelling carriers from the floating gate by irradiating the floating gate with ultraviolet rays, X-rays, or the like.

In addition, in the B''FROM, successive writing is performed by determining that the threshold voltage seen from the control gate provided through the insulating layer on the floating gate differs depending on the charging state of the floating gate. This is done by injecting carriers of opposite sign into the floating gate by tunnel or avalanche injection to neutralize its charge.

Here, the configuration of gpaOM will be explained as a nonvolatile semiconductor memory device.

FIG. 8 shows an element isolation region (l) that does not have an uneven top surface.
h) and a floating gate (1h) extending from the top surface of the floating gate insulating film to the top surface of the element isolation region (1h).
2h) and a control gate (4h) formed thereon via an insulating film (3h). FIG.

With such conventional techniques, it is difficult to increase the writing amount under the same size condition or to miniaturize the channel width direction under the same writing amount condition.

[Purpose of the invention]

An object of the present invention is to provide a non-volatile semiconductor memory that can write a large amount of data, has stable operation, and is miniaturized by increasing the area of the floating gate and increasing the area of the floating gate facing the control gate through an insulating film. The goal is to provide equipment.

[Summary of the invention]

The present invention provides an element region, an element isolation region surrounding the element isolation region having an uneven top surface, a floating gate extending from the element region to the uneven portion of the element isolation region, and an insulation film formed on the element region through an insulation film. This is a nonvolatile semiconductor memory device provided with a control gate.

[Embodiments of the invention]

DESCRIPTION OF THE PREFERRED EMBODIMENTS An EPROM t-ROM will be described as an embodiment of the present invention with reference to the drawings.

Figures 1 and 2 show an element isolation region (la, lb) that has an uneven shape by providing a depression on the upper surface, and a floating gate (2) that extends to cover the depression on the upper surface.
a, 2b) and an insulating film (3a * 3 b) on top of this
(4m, 4
FIG. 3B is a cross-sectional view of a nonvolatile semiconductor memory device provided with FIG.

FIG. 3 shows an element isolation region (1c) having an uneven shape by providing a depression on the upper surface, a floating gate (2c) extending to a part of the depression on this upper surface, and an insulating film (3C) on this region. The control gates (4c) and 2 formed therein are cross-sectional views of a non-volatile semiconductor memory device.

Figure 4 shows the top surface extending to the slope of the element isolation region.
An element isolation region (1d) having an uneven shape formed by providing a depression, a floating gate (2d) that extends to cover the depression on its upper surface, and a control group formed on this with an insulator d (3d) interposed therebetween. ) (4d) is a cross-sectional view of a nonvolatile semiconductor memory device provided with.

Figures 5 and 6 show element isolation regions (LE, IFL) that have an uneven shape by providing a projection on the upper surface, and a 7e+-teinggu that extends to cover the projection on the upper surface.
(2e, zfl and an insulating film on top (3e, 3f)
control group formed via) (4e, 4
f) is a cross-sectional view of a nonvolatile semiconductor memory device provided with.

Figure 7 shows an element isolation region (Ig) having an uneven shape by providing depressions and protrusions on the upper surface, and floating goo (Ig) that spreads to cover the depressions and protrusions on the upper surface.
FIG. 3 is a cross-sectional view of a nonvolatile semiconductor memory device including a control gate (4g) formed thereon with an insulating film (3g) interposed therebetween.

In the embodiment of the present invention, by providing a floating gate, an insulating film, and a control gate on the top surface of an element isolation region having an uneven top surface, the area of the floating gate and the area of the floating gate and the control gate facing each other through the insulating film can be improved. can be made wider than before. Due to the large area of the floating gate, many high-energy carriers are injected, and since the area where the floating gate and control gate face each other through the insulating film is large, the potential of the floating gate can be increased by capacitive coupling to make it sufficiently high. I can do it.

As described above, many high-energy carriers are generated due to the sufficiently high potential difference between the floating gate and the drain, and are injected into the wide-area floating gate across the barrier between the insulating film and the semiconductor surface. Therefore, the amount of writing increases and the potential difference during reading (generally called margin)
becomes larger, so the operation becomes more stable.

Furthermore, since the amount of writing is large, it is possible to miniaturize the memory semiconductor element in the channel direction.

Note that the shape of the cross section shown in the drawings does not need to extend entirely in the channel length direction. In other words, any cross-sectional structure that satisfies the conditions even if only partially is sufficient.

It goes without saying that the present invention can also be applied to other equidiscursive semiconductor memory devices such as E''FROM.

〔Effect of the invention〕

According to the present invention, since the area of the floating gate and the opposing area of the floating gate and the control gate can be increased through the insulating film, the amount of writing can be increased, the operation is stable, and the non-volatile semiconductor can be miniaturized. A storage device can be provided.

[Brief explanation of drawings]

FIGS. 1, 2, 3, and 4 show an embodiment of the present invention having an element isolation region with a recess provided on the upper surface.
PRc)M; FIGS. 5 and 6 are cross-sectional views of an EFROM showing an embodiment of the present invention having an element isolation region with a protrusion on the top surface; FIG. 8 is a cross-sectional view of an EFROM showing an example of a conventional EFR.
A cross-sectional view of OM. 1a, lh, lc, ld, le, If, I
g, lh = element isolation region. 2a, 2b, 2c,%2d,, 2e, 2f,
2&2h...Floating gate. 3m-=3% 3G%3d-=3es 3% 3
& 3h”・Insulating film. 4m, 4h, 4c, %4a, 41!, 4t,
4gX4h--control gate. Figure 2 Figure 3 @ No. 4111

Claims (1)

[Claims] an element region, an element isolation region surrounding the element region and having an uneven top surface, a floating gate extending from the element region to the uneven portion of the element isolation region, and an insulating film placed over the floating gate; What is claimed is: 1. A nonvolatile semiconductor memory device comprising: a control gate formed therein.