JPS61179680A - Solid-state image pickup device - Google Patents

Abstract

PURPOSE:To save power consumption and to simplify manufacture processes by using the 1-shift register drive or 2-shift register drive type 1E/B transfer technology for a buffer CCD of an FT area sensor. CONSTITUTION:Shift registers 2A, 2B are arranged at both sides of an image pickup region 1 in which plural vertical CCDs are used in common as a picture element array, output points are connected alternately to different vertical scanning lines 3 and connected to transfer electrodes constituting each row of the vertical CCDs. Similarly, shift registers 2D, 2E are arranged at both sides of a storage section 1D arranged between the vertical CCD and horizontal CCDs 5 (from A to D). Transfer pulse information is injected to the shift registers from input terminals 2C, 2C', 2F, 2F' shifted at each transfer stage and a signal obtained from the injected transfer pulse information subjected to a prescribed period of delay is outputted to the vertical scanning lines connected to the CCDs.

Description

DETAILED DESCRIPTION OF THE INVENTION TECHNICAL FIELD The present invention relates to solid-state image sensor technology, and more particularly to transfer technology for CCD area sensors.

BACKGROUND ART CCD area sensors include an incline transfer format, an FT area sensor format including the above-mentioned buffer γCCD, and a full-frame 14 transfer format in which the above-mentioned buffer CCD is omitted. A large number of applications or developments of CCD transfer techniques have been proposed for (1) transferring the signal charges of the vertical CCDs. JP 59-1F1i7186.59-188285 filed by the present inventor.
201588゜212082.218082, special mention 58
-207991.232134.24064/1.59
-15950.34839,49685,69835,
91/l I 7.95314. l 89970.2
+1797, P C'I' Showa 1986 Ga 1 Discloses a transfer technology named in-type E/B transfer technology (abbreviated as CIE/B transfer method).

For example, 1 shift register drive IE/B transfer, 2 noft register drive IE/B transfer, I shift register drive 2
E/B transfer, 2 shift register drive 2E/H transfer, 2 clock line drive IE/I3 transfer,! Clock line drive IE/
According to the above-mentioned CIE/B transfer method, which is divided into five B transfers, the number of transfer electrodes required for a vertical CCD can be halved compared to the conventional one. Among the CI E/B transfer methods, application of the 4-clock linear motion 2E/B transfer format to a still camera is disclosed in Japanese Patent Laid-Open No. 59-66277. Also,
IEDM84. Paper No. 2.6, Accordion Imager discloses a one-shift register-driven 2E/I3 transfer format. In addition, the above accordion image demon technology is:
ND V 1' of odd (even) rows to the buffer CCD shown below.
Discloses an independent accumulation of signal charges under G, and furthermore provides an l shift register drive type 2E/B from the above buffer CCD.
The legal output format will also be disclosed.

DISCLOSURE OF THE INVENTION Despite the above-mentioned prior art, there are strong demands for performance and cost of solid-state imaging devices. In order to meet the above requirements, the present invention aims to improve the C I E/B transfer type solid-state imaging device disclosed in the above prior art. In addition, the above C
Since it is believed that the I E/B transfer method itself will be easily understood by those skilled in the art by referring to the above-mentioned documents, a part of the explanation will be omitted. The basic features of the invention are disclosed below.

(1) A vertical CCD that also serves as the 0 pixel column, a horizontal CCD that outputs signal charges, and a signal type CI placed between the vertical CCD and horizontal CCD and transferred at high speed from the vertical CCD.
In a solid-state imaging device (hereinafter abbreviated as FT area sensor) equipped with a buffer CCD that temporarily accumulates , at least some of the transfer 1G poles of the buffer CCD are directional transfer electrodes. (abbreviated as DV'TG), and each buffer CCD is characterized in that when it outputs a signal 11X charge, it sequentially transfers signal charges from the potential well on its output side. Solid-state image sensor.

(2) The solid-state imaging device according to item 1, wherein the DVTGs of the buffer CCD are each driven by different output contacts of a shift register.

(3) The above-mentioned buffer CCD including at least D V T G is characterized in that signal charges are temporarily accumulated in all the potential wells substantially existing at least in the central portion of the channel region. The solid-state imaging device according to item 1.

(4) The solid-state image pickup device according to item 1, wherein the soft renostar for driving the DVTG is constituted by a ratioless dynamic shift register.

(5), the above buffer 7 CCD I) D V T
G (7), odd (even > Vt row DvTG and even (odd)
Several lines (1) The solid-state H image element according to item 1, characterized in that the D V T G is controlled by different shift registers.

(6), the transfer electrode of the buffer CCD includes a non-directional transfer electrode (abbreviated as NDVTG), and the buffer 7
In at least the central part of the channel area of the CCD, the ? :1 (even)/several lines of NDVTG
A potential well is created under which charge can be stored, and even (
In the FT area sensor, a potential barrier is created under several rows of NDV T G, and the voltages 61j of the potential well are outputted in order from the output side. An FT area sensor characterized in that several rows of N0VTG and even (odd) rows of N0VTG are driven by different shift registers.

(7) Equipped with 41 straight CCDs and horizontal CCDs that serve as one pixel column or are arranged between pixel columns, and between them, a signal type (::i) is temporarily transferred from the vertical CCD at high speed. It has a structure with or without an accumulating buffer CCD, and the above-mentioned vertical CCD and buffer CCD.
Odd (even) rows of clock transfer electrodes are placed above the central part of either or both channel regions (the clock transfer electrodes are DVs to which a clock voltage is applied)
Specify TG or NDV TG. ) are driven by even (odd) rows of clock transfer electrodes and different shift registers; The output inverter is a solid-state image sensor characterized by having a larger current driving capacity than the above-mentioned connected inverter.

(8) A vertical CCD that also serves as one pixel column and a horizontal CCD,
In a solid-state imaging device that includes a buffer CCD that is placed between the two and temporarily stores signal charges that are transferred at high speed from the vertical CCD, the vertical CCD stores signal charges that represent one frame image during the vertical retrace period. A solid-state image sensing device characterized in that the signal charges of two adjacent pixel rows are transferred independently to the buffer CCD, and the buffer CCD outputs signal charges of two adjacent pixel rows during one horizontal retrace period within the vertical scanning period.

(9) The solid-state imaging device according to item 8, wherein either or both of the vertical CCD and the buffer CCD sequentially output signal charges from their output sides.

The invention consists of three very closely related independent claims. The detailed features and effects of old claims are explained below.

Claim 1: Since the accordion imager disclosed in the above-mentioned prior art can reduce the number of transfer electrodes of the buffer CCD by half, it is possible to create a small FT area sensor. However, in the accordion imager described above, which uses the 1 knot drive 2E/11 transfer method, the shift register is configured to store one row of signal charges (IJff, 1
It is necessary to provide two inverters per charge group). As a result, in an F'r area sensor with a small image progression bias, each inverter must be made very small. However, each inverter of the shift register has a non-'r:'
Heavy negative A]: Since it is necessary to drive the f capacity, it is necessary to increase its 1+ current driving capability. Especially F1
'In the buffer γCCD of the area processor, the high speed In direct transfer 1 to 1 cannot exceed one vertical retrace period. A second problem with the prior art described above is the need to use CMOS soft registers to reduce the DC power consumption of the shift registers described above. This complicates the manufacturing process. And the third problem is the CMO mentioned above.
Despite the use of the S soft register, the load capacity Q of the shift register is large, so the transient current of the CMOS inverter is large. As a result, it is necessary to install a large power supply, which is expected to cause an increase in the temperature of the depth. The present invention solves the above-mentioned shortcomings by 7%, and solves the problem of the buffer CCD of the FT area sensor with one shift register drive type or two shift register drive type IE/B described in the prior art.
It is characterized by the use of transfer technology. By shifting in this way, especially by adopting a two-inf register drive type IE/B transfer system, +IK can be achieved without reducing the inverter density of the nf register. It is possible to reduce power consumption by

Of course, it is also possible to divide the shift register of the invention into a plurality of partial shift registers. Furthermore, the buffer CCD using the one shift register drive or two shift register drive IE/B transfer technology of the present invention has the advantage that the shift register can be operated dynamically. This results in the benefits of saving power consumption and simplifying the manufacturing process.

Claim 2 This claim discloses that the buffer CCD can be driven by a one-shift register drive method or a two-shift register drive method in claim (2).

Claim 3 This claim is based on the above-mentioned buffer t-
c Indicates that the signal is transferred at high speed to virtually all potential wells of the CD and temporarily stores the signal; 2. In the E/B transfer format, F
's D is applied to the potential well below T, and this signal type A:f storage operation is performed by Ji, which modifies the transfer pulse information injected into the shift register, as will be explained later. Ru.

Claim 4 In a preferred embodiment of claim I using a 1 or 2 shift register drive IE/[3 transfer, the shift register described above is provided with a ratioless output register. In this way, the DC power consumption of the shift register becomes almost zero, making it possible to drive the DVTG at high speed.

Claim 5 In a preferred embodiment of claim 1, a two soft register driven IE/B transfer technique is used.

In this way, the vertical density of the shift register inverters can be halved, as explained earlier.

The tally 11 in the claim is a 2 shift register drive US 2 E /
An F'I' area sensor including a buffer CCD driven by Bfi transmission is disclosed. , fS transfer electrode is N
Driving the DVrG buffer CCD with a 2-shift register drive 2E/B transfer technique provides significant advantages. That is, by driving the NDV TGs in odd (even) rows and the NDVTGs in even (odd) rows using different shift registers, each shift register
It can be configured by an output inverter that drives G and a connection inverter placed between the above output inverters.

The above connected inverter has an extremely small negative 6j capacitance compared to the output inverter, so it can operate quickly. As a result, the voltage change sent from this connected inverter to the output inverter at the next stage is rapid, and the CMO8 output inverter current can be significantly reduced. Another advantage of this claim is that the connected inverter can be made very small, so even if the voltage change (clock voltage waveform) applied to the connected inverter is degraded, the transient current of the connected inverter is small. .

Crane, 7 This claim applies to the above 2 soft reno star drive type 11':
/T (transfer technology or 2 shift register drive 2L
In the C/IJ transfer technology, it is disclosed that the output inverter constituting the two-phase shift register is made more easily than the connected inverter. In this way, the area of the output inverter disposed within a very limited vertical width can be increased, thereby improving its current driving capability. Since the load capacity of the connected inverter is very small, its output resistance should be large. This technique is particularly effective for F'v area sensors equipped with a buffer CC1) that requires high-speed vertical transfer.

Claim 8 This claim is based on the F'v area sensor (VA CCD).
), the signal charges of each pixel row of the vertical CCD constituting one frame image are transferred at high speed and independently to the above-mentioned buffer CCD during the vertical retrace period,
The buffer CCD is characterized in that it independently outputs the signal charges of two adjacent pixel rows during one horizontal retrace period of the next vertical scanning period. In this way, it is possible to output an image with high vertical resolution and good color.
'You can make an area sensor. In the conventional FT area processor, the signal types /if of two adjacent pixel rows of the vertical CCD are mixed and outputted because of the need to perform electrical incretion and the need to save the number of transfer electrodes. Further, no consideration was given to vertically transferring the signal charges of each pixel row of the vertical CCD independently.

Claim 9 In the preferred embodiment of claim 8, the vertical CCD or the buffer γCCD outputs a signal type (1) using the above-mentioned GIE/[3 transfer technique. , signal charges of all pixel rows representing a frame image can be output independently.

Other features and advantages of the invention are described below.

Note that the 1 shift register drive type connects each transfer electrode of the CCD to each output contact of one shift register, and the 2 shift register drive type connects the transfer electrodes of the odd (even) rows of the CCD and the even (odd) rows of the CCD. ), in which several rows of transfer electrodes are driven by substantially different shift registers, and IE/R transfer is a form in which the electric current G7 accumulated between each DvTG of the CCD is independently transferred; B transfer is odd (even) number line (7)
N D V T G f7) This is a format in which the charges accumulated under the N D V T G f7) are independently transferred. NDV i' G is a transfer electrode whose channel below has a constant potential, and DVT
G is a transfer electrode in which a potential well and a potential barrier are created in the channel below.

BEST MODE FOR CARRYING OUT THE INVENTION FIG. 1 is a block circuit diagram of an embodiment of a two-shift register driven color FT' area sensor according to the present invention. Shift registers 2Δ and 2B are arranged on both sides of the imaging area 10 where a plurality of vertical C0Ds (not shown in the figure) that also serve as pixel columns are arranged.
is placed. The output contacts of the shift registers 2Δ and 2I are alternately connected to the vertical scanning lines 3, and the vertical scanning lines 3 are connected to the transfer electrodes constituting each row of the vertical CCD. Similarly, shift registers 20.2E are arranged on both sides of the storage section ID, which is arranged between the vertical CCD and the horizontal CCD 5 (A to D).

The storage unit ID has a plurality of buffers CC that transfer signal charges (charge groups) received from the vertical CCD.
, D (omitted in FIG. 1).

The output contacts of the shift registers 2D and 2E are alternately connected to different vertical scanning lines 3', and the vertical scanning lines 3' are respectively connected to the transfer electrodes of each row of the buffer CCD. Transfer pulse information is injected into the above shift register from input terminals 2C12C', 2F, 2F',
The transferred information is shifted to each transfer stage of the shift register.

Therefore, each output contact of the shift register outputs a signal which is extended for a certain period of the transfer pulse information injected from the above-mentioned input terminal to the connected vertical scanning line.

Horizontal CCD 5 (A color D) u; ll+ row r
Knee array sales 4 (1Mj horizontal output means,
1st horizontal CCD 4Δ and 11 (is the odd (even) of the Nth pixel row)
The second horizontal CCD 513 transfers signal charges of even (odd) columns of the N-th pixel row, and the third horizontal CCD 5G transfers the signal charges of the even (odd) number columns of the N-th pixel row. gA)
The fourth horizontal CCD 5D transfers signal charges of several columns (or even (odd) columns), and the fourth horizontal CCD 5D transfers signal charges of even (odd) columns of the N-1th pixel row.
or odd (even) sequence) signal charges. Each horizontal C
between the CD and the first horizontal C0D5A and the buffer CC
A transfer gate 4 (A to D) is arranged between the output terminals of D. The four horizontal CCDs distribute the signals 7IX of two adjacent pixel rows received from the buffer C during one horizontal retrace period, and horizontally transfer them during the next horizontal scanning period. As a result, horizontal image loss can be increased. Details of the above-mentioned 4-horizontal CCD structure can be found in, for example, Japanese Patent Application Publication No. 59-18 filed by the present applicant.
See 4328. The F'i' area sensor in FIG. 1 transfers the signal charge h'i stored in the vertical CCD during the vertical scanning period to the buffer CCD at high speed during the next vertical retrace period.

The vertical CCD has pixel rows corresponding to 1 frame image (for example, r in the NTS C system, which is approximately 490 pixel rows), and the signal lines t and f of each pixel row are independently buffered. Transferred to the CCD at high speed and transferred to the buffer CCD above.
temporarily accumulates the transferred signal charges of the convex pixel rows in one t.

FIG. 2 shows a two-knot reinostor drive I, which is an embodiment of the nut 11.
E/l (This is a transfer state diagram of the transfer color F'r area sensor.j7j iμCCDIA and buffer CCD IC each have a DVTG.And each D of the vertical CCD
The signal charges independently accumulated under each D V T G are vertically transferred to the buffer CCD I C independently, and are independently accumulated under each D V T G of the buffer CcD. As a result, the required number of transfer electrodes for the vertical CCD and buffer CCD is halved compared to a format using a two-phase clock CCD. The period 0 to t9 is established within the vertical retrace period aIj. 0 to each DV'rG3 of the vertical CCDIA.
(7, to V) respectively accumulate signal charges Q (+ to 5). Note that in this specification, 0 represents an empty potential well having a deep potential VH, and a blank potential well region represents a potential well region having a shallow potential V[,. From period to to period t9, the vertical C0DIA sequentially outputs signal charges from its output terminal. This is described in detail in the two-shift Renosc driven IE/13 transfer method filed by the present applicant. During the period to to [5, the buffer CCD receives the signal 11 by substantially two-phase clock transfer.
i Transfer the cargo. This is easily done later on. Note that in this specification, a potential well with a deep potential VH is a potential well that is a product of Ii and a potential well with a shallow potential VL, and a potential well with a shallow potential VL is a potential well that transfers signal charges to the next stage potential well. It is a well. Therefore, the shallow potential v is N
In this specification using channel CCD, more E
The potential is in one direction (for example, Ov), and the deep potential Vll is a potential in a more positive direction (for example, +10V). Period [6
From [9, the buffer γCCD has a period of its output [9
In this case, all signal charges of vertical CCD IA are transferred to buffer C.
Transferred to CD IG. And vertical running period '1'
At the beginning of v, each D V TG of heavy 11χ CCD I A
Potential well 3 (Z to V) below also has a deep potential V H and stores signal charge for the next field.

A good way to reset each vertical scan line of a vertical CCD IA to a deep potential VH is to set its output contact to a shallow potential VI.
, by shifting the shift register that outputs , by I/2 transfer stage. Then, the signal charges Q (I to 5) accumulated under each potential well 3 (Zo to vo) of the above-mentioned vertical scanning period 17 old buffer CCD IG are transferred in order from the signal charge closest to the output end. Ru.

This transfer is performed by the same two-shift register drive IE/B transfer method as the vertical C0DIA signal charge transfer during the vertical retrace period. In addition, during one horizontal retrace period, signal charges of two pixel rows are output from the buffer CCD to the water 51i CCD,
distributed to each horizontal CCD.

Then, during horizontal scanning ART'S, each of the horizontal CCDs horizontally transfers signal charges of two adjacent pixel rows independently.

In the embodiment of FIG. 2, a two-phase ratioless dynamic shift resistor is used for signal charges.

Therefore, one transfer stage of the shift register has two inverters, and the perpendicular scanning line is connected to the output contact of the r:r (even-losing) or even (odd)-numbered inverter of one shift register. Figure 3 shows the period of 11 ccDIA in Figure 2 [0 to [].
FIG. 6 is a detailed transfer state diagram showing the transfer operation of No. 6; The shift register 2A1213 is, for example, a gold phase ratioless dynamic shift register as shown in FIG. 1O,
It consists of an output inverter and a connection inverter connected alternately. Then, the output contacts of the output inverter connected to the vertical scanning line are charged to a deep potential Vl+ when the output inverter performs the charging operation P, and the output inverter evaluates (
When performing operation E (logical discharge), the input gate information of the output inverter is used to discharge the voltage to the shallow potential VL 1u or maintain the deep potential V11.

During period 0, all 11 of soft registers 2A and 2B
I'm going to do it. For example, in Figure 1O, the output inverter I
This can be easily done by setting the IA to charging operation. ,
During the 11th period, the shift register 2A performs the evaluation (absent) operation E, and the vertical CCDIA potential well TV37. is the shallow potential V
It becomes L. And signal type n:i Ql is transfer gate IB
Transferred under. Note that the transfer gate IB is arranged at l) to ensure a distance between the shift registers 2Δ and 2D, and can of course be omitted. Note that in FIG. 2, the above-mentioned transfer gate IB is omitted due to drawing space constraints. As a result, in FIG. 3, the potential well 3V'l! of the buffer CCD IC! 3W'1 in Figure 2.
:Equivalent to m. Period [2 smell-ζ, 2Δ implements P, 2B implements 1>. And the potential well of the vertical CCD IA? '-i 3 Y becomes a shallow potential VL. Similarly, it is injected as shift transfer pulse information (logical information). Naturally, the above transfer pulse information is logical information that generates a shallow potential VL at the output contact of the output inverter.

An important advantage of this two-shift register drive 2E/[1 transfer method is that the deep potential VH output by each ratio-less output inverter of the soft register during the P period is used for transfer. As a result, the transfer operation is nti! Become I'. Its second advantage is that ratioless inverters have less power consumption because they have no transient currents. This is out)
J inverter fits heavy load field! Two things are important in the present invention. The third advantage is that the above ratioless shift register is simple? Having a J fi process,
The main advantage is that fewer transistors are required per transfer stage.

That is, each shift register has 3 or 4 transistors per pixel row pitch. In the 1 shift register drive 2 E/13 transfer F'r area sensor (accordion imager) described in the prior literature, the shift register is 1 pixel row (when electrical incretion is not considered).
It is necessary to have six or more transistors per pitch and use CMOS inverters. Furthermore, since the shift register of the present invention allows the connected inverter to be made smaller, the output inverter can be made relatively larger. Figure 4 shows buffer C
It is a detailed transfer state diagram of periods [2 to [5] of 0DIG. The shift registers 2D and 2E receive a shallow potential vL as logic information at each output contact at the beginning of the vertical retrace period. Each output inverter of the shift register 2D performs the E operation during the period to, and each output contact becomes a shallow potential VL.

And the output inverter of shift register 2E is! ) operation, and each output contact is all at deep potential VH.

During the t1 period, the output inverter of the shift register 2D performs a P operation, and each output contact becomes a deep potential VI-1.

The shift register 2E then performs the E operation, and each output contact becomes a shallow potential Vt.

During the t2 period, the shift register 2D performs the E operation, and each output contact becomes a shallow potential VL. Then, the shift register 2E performs the P operation, and each output contact becomes a deep potential ■■. Similarly, shift register 2D.

2E alternately performs P operation and E operation, and signal charges are transferred by substantially two-phase lock transfer operation. Figure 5
represents the detailed transfer status from period [6 to period t9. In the period t6 after the period t5 in which the first signal charge Q1 arrives at the final potential well 3Z' of the buffer CCD IG, the shift register 2D performs the E operation, and the potential well 3Z'
The output contact of the shift register 2D that controls the deep potential V
Output l+. The other output contacts of the shift register 2D operate to output the potential VL. This is implemented by inputting predetermined logic information from the input terminal 2F of the shift register 2D. Then, the shift register 2E performs the operation (2), and the external output contact becomes a deep potential Vl+. During period [7], the shift register 2D performs a P operation, and each output contact becomes a deep potential Vll. and shift register 2E
performs E operation, and vertically becomes Nftre which controls the electric potential of I C by σ11. Similarly to 1, E is set at the output contacts of shift registers 2D and 2E.
During the period, a deep potential Vl+ is generated, logic information is alternately input from the input terminals 2F' and 2F'', and the shift registers 2D and 2E alternately perform the P operation and the 1> operation.

In this way, the signal charges are independently IIh'1 under the potential well 3 (from Zo to 'I'') under each DVTG of the buffer CCD.
The vertical CC1) or buffer CCD has more potential wells than in Fig. 2, but their description is omitted from Fig. 2 due to drawing space constraints; the basic drawing and operation are the same. be. In Figure 2, buffer C
The transfer of signal charges from CD to horizontal CCD is
This is the same as the noft register drive IE/B transfer method. In addition, the two shift register drive I disclosed in FIGS. 2 to 5
Instead of the E/B transfer FT area sensor, it is possible to use the soft register drive I E/I (transfer 1/'i' area sensor), and the transfer operation is basically the same. Invention of 2 noft L/nosk drive 2 E/B transfer F
This is a transfer state diagram of the T area sensor, and is the same as the transfer state diagram of the 1 soft register drive 2 E/[(transfer F'r area sensor (accordion imager)) described in the above-mentioned prior literature.

■The block circuit diagram of the F'r area sensor shown in - is the same as in Fig. 1. From period In to period t14, the signal charge Q (from I to 4) vertically to CD + is Transferred to the Sofa CCr) IC. Vertical C(:I)I
The t-signal set A::j stored under the 4 (even) rows of A is independently transferred. Please refer to the above-mentioned earlier application for details. Figure 7 shows a detailed transfer state in which the signal charges Q (1 to 4) of each potential well 3Z, 3X, 3V, and 3T are transferred directly to CD l using the 2 shift register drive 2E/B transfer method described above. It is a diagram. Potential well 37. ．． 3
The potential of X, 3 V, 3 T is controlled by the h output contact of shift register 2A, and the potential wells 3Y, 3
The potentials of W and 3tJ are controlled by each output contact of the shift register 21S. However, 2 shift register drive 2F/+3 transfer F disclosed in Figure G, [472 Figure 83 Figure 9]
In the T area sensor, the retake CCD and buffer CCD
has NDVTG, so the above potential well has a deep potential V
It operates as a potential well only when H is applied, and operates as a potential barrier when a shallow potential VL is applied. In the transfer state diagram of FIGS. 73, 85, and 9, the vertical CC
l) The first shift register that controls the potential wells of the odd (even) rows of (or buffer ccD) and the second shift register that controls the potential wells of the even (odd) rows operate alternately. This fact can be clearly understood by referring to the figure.
During the 0 period, all output contacts of the shift register 2A output a deep potential VH, and all output contacts of the shift register 2B output a shallow potential V1. Shallow potential VL and deep potential V11, which are logic information (transfer pulse information), are alternately injected into shift registers 2A and 2B from their input terminals 2C and 2G', respectively. As a result, as can be understood from FIG. 7, the vertical CGDIΔ is a signal type in order from its output end? Output J Q (+ to 4). In addition, shift registers 2A, 2B, 2D, and 2E are two-phase CMO
This is S Scudipuk Shift Reno Star. Each transfer stage of each shift register is constructed by alternately arranging output inverters and connection inverters. However, in this specification, the output inverter is an inverter that controls its output contacts or vertical running lines, and the connection inverter is an inverter that is placed between two adjacent output inverters and inverts and sends logical information. . That is, this 2-shift registration drive 2
In the embodiment of the E/B transfer p'r area sensor, the charging operation P of the ratioless dynamic shift register is inhibited. 8 and 9 are detailed transfer state diagrams showing the operation of buffer C0DIG during period t (2 to t17). Potential well 3Z°, 3 of buffer CCD IG
The potentials of X', 3 V', and 3 T' are the shift register 2D.
The voltage R1 is controlled by well 3Y゛.

3 W' and 3 U' are controlled by the shift register 2E. Logic information is applied to each shift register 2D, 2E so that the output contacts of the shift register 2I) (or 2E) alternately output a shallow potential VL and a deep potential (ηV l-1), so that the buffer CCD IG undergoes substantially four-phase clock transfer, resulting in period t8
Then, the signal charge Ql is transferred to the final potential well 3Z' of the buffer CCDIC. Then, from period t9 after the first signal charge Q1 arrives at the final potential month ri3Z° of buffer 7CCD, the final set of buffer CCD I , logic information is injected into the input terminal of the shift register 21). Similarly, from the period LIO, the buffer CCD
Logic information is injected from the input end of the soft register 2E so that the output contact that controls the potential of the potential C 11 and the potential 3Y' outputs a shallow potential 1. If you do this,
Odd (even) NDV of buffer CCD IG
Potential well 37 created below i'G. ', 3 X'
, 3 V', and 3 To respectively store signal type 6:j. Then, during the 114 period, the signal charge Q (from + to 4) of the vertical CCD I A is by'7y CCD I C's il (
Even) vi number [1) Buffer CC between N D V T 0
Represents the transfer status of D. At the beginning of the vertical scanning period, the vertical CCD IA performs electrical ink tracing.
A deep potential V l-1 is applied to the potential well at a position different from the period to.
is applied. The above potential setting of the vertical C0DIA can be performed by further continuing the transfer operation performed until period t14, or by forcibly changing the potential of the output inverter or connected inverter's manual contact or output contact. can. Then, from the above period t15 to [19], the 2-ft register driving 2E/
By the B transfer method, signal charges are sequentially output to the horizontal CCD from the output end of the buffer CCD IC. This operation is basically the same as the vertical C0DIA signal charge transfer during the vertical retrace period (period [O to t14). That is, in the first period L14 of the vertical scanning period, each output contact of the shift register 2D outputs a deep potential V1.1, and each output contact of the shift register 2E outputs a shallow potential V1,
Output.

And the input terminals 2F, 2F of each shift register
” By injecting color logic information, the buffer CC
The DIC sequentially outputs signal charges from its output terminal.

P filed by the applicant on January 30, 1985
CT patent application or Japanese Patent Application No. 59-211797 is a two-phase CM
One embodiment of an OS shift register is disclosed. The 2-ft register drive 2 E/U transfer I? explained in FIGS. 6 to 9? Compared to the well-known 1-ft register drive 2-E/n transfer F'r area sensor, the connected inverter can be made smaller and the output inverter larger, so it has a larger current drive capability. ! +J is received. Furthermore, since the connected inverter has a small negative 6:i capacitance and can operate at high speed, the transient current of the next stage 0MO5 output inverter is significantly reduced. FIG. 10 is an equivalent circuit diagram of an embodiment of the shift register of the two shift register driven IE/11 transfer FT area sensor of FIG. This equivalent H path is the shift register 2Δ that drives the vertical CCDIA.
, 2B, but the shift registers 2D and 2E that drive the buffer CCD are also the same. This equivalent circuit is a well-known two-phase ratioless shift register, in which the output contacts +2Al of the output inverter IIA of the first shift register 2Δ: vertical scanning lines 3Z and 3X are connected, and the output inverter 11Δ of the second shift register 2B A vertical scanning line 3Y is connected to the output contact 12A° of the vertical scanning line 3Y. However, in this specification, for ease of understanding, vertical CCD
Alternatively, the potential well of the buffer CCD and the vertical scanning line connected to the transfer electrode installed above are represented by the same symbol. JIB is a connection inverter, 8A, 813 is a charging switch, 10Δ, lo[3 is a discharge switch, 7A, 7r3 is a connection switch between inverters. The operation of this equivalent circuit is explained using the clock voltage diagram in FIG. I+. P is a charging period, and the output contact of the inverter is charged to a deep potential ■H (VD). E is the evaluation period, and depending on the input logic information of the inverter,
Its output contact becomes shallow potential VL (VS) or deep potential ■1! will be maintained. For example, Figure 39, Figure 4, Figure 5
Please refer to QQ. The signal voltage Gt is always transferred under D V 1' G which is charged by the P operation. Therefore, the potential fluctuation of D V T G due to the accumulation of signal voltage (=: 1), the P operation of one shift register is always performed by the E operation 1u of the other shift register.

Therefore, the transfer operation is very stable.

Note that at the same time as the P operation of the connected inverters 12[3, 12B' ends, the l) operation of the output J inverters I2A, I2A' is started. However, considering that the capacitance -1 of the vertical scanning line is very large, the change in potential that the charging current of the output inverter gives to the manual contacts of the connected inverter is very small. Of course, it is possible to finish the P operation of the connected inverter earlier than the start of the P operation of the output inverter. In the embodiment of FIG. 10 as well, the small load capacitance of the connected inverter has a great effect on increasing the speed of the shift register, and is effective for the FT area sensor that requires high-speed transfer to the buffer CCD. Moreover, the IE/B transfer F of the present invention
Compared to the 2E/B transfer FT area sensor shown in FIG. 6, the T area sensor is very important because it has a simpler transfer lock operation and enables high-speed transfer. Also, IE
The transfer electrodes of the /R transfer FT area sensor are arranged vertically alternately, with transfer electrodes B having a thin film thickness and transfer electrodes B having a thick film thickness, and l D V T G to adjacent transfer electrodes. There is an advantage that the transfer electrode B can be connected. This has the advantage that the sensitivity can be greatly improved compared to 1. In the 2E/13 transfer F'r area sensor, the number of transfer electrodes is doubled, so it is very difficult to employ the above transfer electrode structure. Note that the above transfer electrode structure is described in the applicant's prior application described in the prior art. Further, it is very preferable to implement the IE/B transfer FT area sensor of claim I together with the frame image output technology of claim 8. That is, this is because it solves the drawback that in the IE/B transfer FT area sensor, it is difficult to electrically convert the position of the potential well of the 1R direct CCD to perform increment. That is,! 1 of claim 8 which outputs two adjacent pixel rows in the horizontal scanning period? In the T-area sensor, increment can be performed by changing the combination of two pixel rows that are output together every field period. Furthermore, instead of implementing claim 8, it is also possible to vibrate the relative spatial position of the signal light and the FT area sensor in the vertical direction every vertical retrace period. For example, F
The vertical CCD of the T area sensor has the number of transfer electrodes corresponding to the I field pixel row, and 172 transfer electrodes during the vertical retrace period.
Only the pixel rows vibrate in the vertical direction. In this way, 4' allows mechanical ink lace. Of course, the use of the IE/BFT area sensor is very effective in applications such as robot eyes because there is no need to perform ink tracing.

Margin below

[Brief explanation of drawings]

Figure 1 shows the 2-soft resist drive of the present invention! or 2E/B
FIG. 2 is a block circuit diagram of one embodiment of a transfer F'r area sensor. FIG. 2 is a transfer state diagram of the 2-shift registration drive I E/B transfer FT area sensor of the present invention. Figure 3 is Figure 2
FIG. 3 is a detailed transfer state diagram of the vertical CCDIA of FIG. 4 and 5 are detailed transfer state diagrams of the bubble 77cCDIG of FIG. 2. Figure 6 shows the 2-shift reno star drive 2E/ of the present invention.
FIG. 11 is a transfer state diagram of the No. 11 transfer FT area sensor. FIG. 7 is a detailed transfer state diagram of the vertical CCD IA of FIG. 8 and 9 are detailed transfer state diagrams of the buffer CCD IC of FIG. 6. FIG. 10 is an equivalent day diagram of one embodiment of the shift registers 2Δ and 2B that drive the flat CCD of FIG. FIG. 11 is a clock voltage diagram of the shift register of FIG. IO.

Claims (9)

[Claims] (1) A vertical CCD that also serves as a pixel column, a horizontal CCD that outputs signal charges, and a buffer that is placed between the vertical CCD and horizontal CCD and temporarily stores the signal charges transferred at high speed from the vertical CCD. In a solid-state imaging device (hereinafter abbreviated as FT area sensor) equipped with a CCD, at least some of the transfer electrodes of the buffer CCD are directional transfer electrodes (abbreviated as DVTG). A solid-state imaging device characterized in that, when each buffer CCD outputs a signal charge, the signal charge is sequentially transferred from the potential well on the output side. (2) The solid-state imaging device according to item 1, wherein the DVTGs of the buffer CCD are each driven by different output contacts of a shift register. (3) the above buffer C comprising at least DVTG;
2. The solid-state imaging device according to claim 1, wherein the CD temporarily stores signal charges in substantially all potential wells existing at least in the central portion of its channel region. (4) The solid-state imaging device according to item 1, wherein the shift register for driving the DVTG is constituted by a ratioless dynamic shift register. (5) Solid-state imaging according to item 1, wherein among the DVTGs of the buffer CCD, the DVTGs in odd (even) rows and the DVTGs in even (odd) rows are controlled by different shift registers. element. (6) The transfer electrode of the buffer CCD is provided with a non-directional transfer electrode (abbreviated as NDVTG), and odd (even) rows are arranged thereon in at least the central part of the channel region of the buffer CCD. A potential well capable of accumulating charges is created under the NDVTG of , and a potential barrier is created below the NDVTG of even (odd) rows, and the charges of the potential well are output in order from the output side. FT
In the area sensor, the above-mentioned NDVTG on odd (even) rows and ND on even (odd) rows
VTG is an FT area sensor characterized by being driven by different shift registers. (7) It is equipped with a vertical CCD and a horizontal CCD that serve as pixel columns or are arranged between pixel columns, and a buffer CCD that temporarily stores signal charges transferred from the vertical CCD at high speed between them. Odd (even) rows of clock transfer electrodes (the clock transfer electrodes are Specify the DVTG or Ni) VTG to which the clock voltage is applied. ) are driven by even (odd) rows of clock transfer electrodes and different shift registers, and each of the above shift registers has an output inverter that generates an output clock voltage and a connected inverter that does not generate it, and the above output inverter is a solid-state imaging device characterized by having a larger current driving capability than the above-mentioned connected inverter. (8), a vertical CCD that also serves as a pixel column, and a horizontal CCD;
In a solid-state imaging device that includes a buffer CCD that is placed between the two and temporarily stores signal charges that are transferred at high speed from the vertical CCD, the vertical CCD stores signal charges that represent one frame image during the vertical retrace period. A solid-state image sensing device characterized in that the signal charges of two adjacent pixel rows are transferred independently to the buffer CCD, and the buffer CCD outputs signal charges of two adjacent pixel rows during an I horizontal retrace period within a vertical scanning period. (9) The solid-state imaging device according to item 8, wherein either or both of the vertical CCD and the buffer CCD sequentially output signal charges from their output sides.