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JPS61174775U - - Google Patents

Info

Publication number
JPS61174775U
JPS61174775U JP5741485U JP5741485U JPS61174775U JP S61174775 U JPS61174775 U JP S61174775U JP 5741485 U JP5741485 U JP 5741485U JP 5741485 U JP5741485 U JP 5741485U JP S61174775 U JPS61174775 U JP S61174775U
Authority
JP
Japan
Prior art keywords
semiconductor element
circuit board
printed circuit
hole
fixed
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP5741485U
Other languages
Japanese (ja)
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP5741485U priority Critical patent/JPS61174775U/ja
Publication of JPS61174775U publication Critical patent/JPS61174775U/ja
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
    • H01L2224/92—Specific sequence of method steps
    • H01L2224/922—Connecting different surfaces of the semiconductor or solid-state body with connectors of different types
    • H01L2224/9222—Sequential connecting processes
    • H01L2224/92242—Sequential connecting processes the first connecting process involving a layer connector
    • H01L2224/92247—Sequential connecting processes the first connecting process involving a layer connector the second connecting process involving a wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/1515—Shape
    • H01L2924/15153—Shape the die mounting substrate comprising a recess for hosting the device
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/1517—Multilayer substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/191—Disposition
    • H01L2924/19101—Disposition of discrete passive components
    • H01L2924/19105—Disposition of discrete passive components in a side-by-side arrangement on a common die mounting substrate

Landscapes

  • Wire Bonding (AREA)
  • Die Bonding (AREA)
  • Structures For Mounting Electric Components On Printed Circuit Boards (AREA)

Description

【図面の簡単な説明】[Brief explanation of the drawing]

第１図はこの考案の一実施例に係る半導体素子
の実装構造を示す断面図、第２図は第１図の実装
工程を示す図、第３図はこの考案の他の実施例に
係る半導体素子の実装構造を示す一部断面図、第
４図はこの考案のさらに他の実施例に係る半導体
素子の実装構造を示す一部断面図、第５図は従来
例を示す一部断面図である。 （図面の主要な部分を表わす符号の説明）、１
…半導体チツプ、３…プリント基板、１５…金属
板。 FIG. 1 is a sectional view showing a mounting structure of a semiconductor element according to an embodiment of this invention, FIG. 2 is a diagram showing the mounting process of FIG. 1, and FIG. 3 is a semiconductor device according to another embodiment of this invention. FIG. 4 is a partial sectional view showing a mounting structure of a semiconductor device according to another embodiment of the present invention, and FIG. 5 is a partial sectional view showing a conventional example. be. (Explanation of symbols representing main parts of drawings), 1
...Semiconductor chip, 3...Printed circuit board, 15...Metal plate.

Claims (1)

【実用新案登録請求の範囲】[Scope of utility model registration request] 半導体素子プリント基板への実装構造にしてプ
リント基板に貫通穴を設けておき、実装しようと
する半導体素子と熱膨張係数が近似し且つ高い耐
熱性および高い熱伝導性を有し当該半導体素子が
固着された板材を前記貫通穴内に収納固定してな
ることを特徴とする半導体素子の実装構造。 A through-hole is provided in the printed circuit board for mounting a semiconductor element on a printed circuit board, and the semiconductor element has a thermal expansion coefficient similar to that of the semiconductor element to be mounted, high heat resistance, and high thermal conductivity, and the semiconductor element is fixed to the printed circuit board. A mounting structure for a semiconductor device, characterized in that a plate material made of aluminum is housed and fixed in the through hole.
JP5741485U 1985-04-19 1985-04-19 Pending JPS61174775U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP5741485U JPS61174775U (en) 1985-04-19 1985-04-19

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP5741485U JPS61174775U (en) 1985-04-19 1985-04-19

Publications (1)

Publication Number Publication Date
JPS61174775U true JPS61174775U (en) 1986-10-30

Family

ID=30581919

Family Applications (1)

Application Number Title Priority Date Filing Date
JP5741485U Pending JPS61174775U (en) 1985-04-19 1985-04-19

Country Status (1)

Country Link
JP (1) JPS61174775U (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2001110941A (en) * 1999-10-06 2001-04-20 Meito Chin Semiconductor device

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2001110941A (en) * 1999-10-06 2001-04-20 Meito Chin Semiconductor device

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