JPS61169950A - Buffer invalidating system - Google Patents

Abstract

PURPOSE:To invalidate only a required entry partially on the basis of an output of a mask by forming a means for masking the invalidation in accordance with each entry in a full associative system (TLB). CONSTITUTION:When an entry used by a job is to be invalidated, prelogic operation between the mask information corresponding to respective entries and an invalidating signal PPTLB is executed by mask circuits 81-8n. The masked output is '1' and the unmasked output is '0'. These outputs are inputted to d type FFs 41-4n corresponding to respective entries. When '0' is inputted, the corresponding entry value is invalidated, and when the invalid bits 71-7n of the corresponding entry are still '0' even if '1' is inputted, the entry is valid. When the invalid bits 71-7n are '1', the corresponding entry is invalid.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a system that can be partially invalidated in a TLB entry used to find a real address from a virtual address in a virtual storage system.

[Prior Art] In a fully associative method in which address translation is performed by referring to a TLB, when one job is completed, all TLB entries used by that job are invalidated. Conventionally, invalidation processing was performed as shown in FIG. That is, for TLB 1 having entries 21 and 22-, an invalidation circuit 31.3 corresponding to each entry is provided.
It is equipped with 2-.-. The invalidating circuit 31 and the like are provided with D-type flip-flops 41, 42, . . . and logic operation circuits 51, 52-, respectively. Each entry stores the correspondence between a virtual address and a real address from a central processing unit (not shown) in each column 61, 62, -. Given a virtual address, the real address can be easily determined by finding a matching entry on that page. When one job ends, all the entries used by that job are invalidated, but at this time, not all entries in the TLB should be invalidated, so the entries are invalidated one by one. During the invalidation process, the invalidation signal *D15 and the write signals *TLBWO, *TLBW1.- are applied to the invalidation circuit of the entry to be invalidated, and the invalidation bits 71, 72.- of the entry are set to 1''.

[Problems to be solved by the invention] Invalidating all entries in the TLB does not investigate the contents of the entries, so the processing up to invalidation is quick, but it requires rewriting next time. . Therefore, only predetermined entries are invalidated.

That is, in order to invalidate only the entries used by the job, the contents of the entries are sequentially checked and matching entries are invalidated. This method required an extremely long processing time.

[Means for solving the problem] In order to solve the above-mentioned problem, the present invention masks invalidation corresponding to each entry in the fully associative TLB used for converting a virtual address to a real address. and using the output of the mask,
This is to partially invalidate only the desired entry.

[Effect 1] Due to the above-mentioned configuration, in the present invention, mask information is prepared in advance for entries to be invalidated, and multiple entries to be invalidated can be invalidated by one invalidation instruction, and invalidation can be performed n times. There is no need to give instructions, and the invalidation processing time becomes faster.

[Embodiment] FIG. 1 is a diagram showing the configuration of an embodiment of the present invention, and 1 is T.
LB, 2 is mask information provided in the present invention, 21.2
2- is each entry, 31.32- is an invalidation circuit, 41.
42- is a D-type flip-flop, 51.52- is a logic operation circuit, 61.62- is each entry column, 7172- is an invalid bit, and 81.82.- is a mask circuit.

When a job ends, a process is performed to invalidate the entry used by that job. At this time, a mask symbol "O" is output as mask information corresponding to an entry that will not be invalidated, and a mask symbol "1" is output as mask information corresponding to an entry that is to be invalidated. Next, the mask information corresponding to each entry and the invalidation signal PPTLB are subjected to a pre-logical operation in mask circuits 81 and 82-. Its output is 1” when masked and °0 when unmasked.
", and is applied to the CLR input of the D-type flip-flop 51.52- corresponding to each entry. When "0" is input to the CLR input of the D-type flip-flop 51.52-, the value of the corresponding entry is invalidated.“L” is applied to the CLR inputs of the D-type flip-flops 51, 52--.
Even if input, the invalid bit 71.7 of the corresponding entry
If 2- is "0" as in the previous state, the entry is valid; if it is "l", the entry is invalid.

[Effect of the Invention J] In this manner, according to the present invention, it is possible to easily select invalidation of TLB entries for each entry. Therefore, the time required for data processing, including the operation after invalidation processing, can be shortened.

[Brief explanation of drawings]

FIG. 1 is a diagram showing the configuration of an embodiment of the present invention, and FIG. 2 is a diagram for explaining conventional entry invalidation processing. 1--TLB 2-Mask information 21.22-Entry 31.32-Invalidation circuit 41.42--D type flip-flop 61.62-
--- Entry fields 71.72 --- Invalid bits 81.82 --- Mask circuit patent applicant Fujitsu Ltd. agent Patent attorney Eisuke Suzuki Diagram 2 procedural amendment (Own ship 1, case display 1986) Patent Application No. 009758 2, Invention Name Buffer Invalidation Method 3, Relationship with the Amendment Person Case Patent Applicant Address 1015 Kamiodanaka, Nakahara-ku, Yozaki City, Kanagawa Prefecture Name (522) Fujitsu Limited Representative Mt. Hon Takuma 4, Agent address: 2-13-36 Yoyogi, Shibuya-ku, Tokyo, Number of inventions increased by the amendment: None 7, Detailed description of the invention in the specification subject to the amendment Drawing 8, Contents of the amendment (1) ) Amend “Not invalidated” on page 4, line 14 of the specification to “Not invalidated” (2) Amend Figures 1 and 2 of the drawings as shown in the attached sheet.

Claims (1)

[Claims] In a system that converts virtual addresses to real addresses using a fully associative method, TLB (Trans
1. A buffer invalidation method characterized in that the buffer invalidation method has a means for masking invalidation corresponding to each entry of a TLB, and only a desired entry is invalidated by the masking means.