JPS61150376A - semiconductor equipment - Google Patents
semiconductor equipmentInfo
- Publication number
- JPS61150376A JPS61150376A JP59271837A JP27183784A JPS61150376A JP S61150376 A JPS61150376 A JP S61150376A JP 59271837 A JP59271837 A JP 59271837A JP 27183784 A JP27183784 A JP 27183784A JP S61150376 A JPS61150376 A JP S61150376A
- Authority
- JP
- Japan
- Prior art keywords
- mos transistor
- gate
- film
- gate electrode
- metal
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims description 9
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 18
- 229910052751 metal Inorganic materials 0.000 claims description 15
- 239000002184 metal Substances 0.000 claims description 15
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 12
- 239000000758 substrate Substances 0.000 claims description 10
- 235000012239 silicon dioxide Nutrition 0.000 claims description 6
- 239000000377 silicon dioxide Substances 0.000 claims description 6
- 230000008018 melting Effects 0.000 claims description 5
- 238000002844 melting Methods 0.000 claims description 5
- 150000001875 compounds Chemical class 0.000 claims description 3
- 229920005591 polysilicon Polymers 0.000 description 10
- 229910052785 arsenic Inorganic materials 0.000 description 3
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 description 3
- 238000009792 diffusion process Methods 0.000 description 3
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 229910052698 phosphorus Inorganic materials 0.000 description 2
- 239000011574 phosphorus Substances 0.000 description 2
- 229910021341 titanium silicide Inorganic materials 0.000 description 2
- WQJQOUPTWCFRMM-UHFFFAOYSA-N tungsten disilicide Chemical compound [Si]#[W]#[Si] WQJQOUPTWCFRMM-UHFFFAOYSA-N 0.000 description 2
- 229910021342 tungsten silicide Inorganic materials 0.000 description 2
- 238000001947 vapour-phase growth Methods 0.000 description 2
- 229910021478 group 5 element Inorganic materials 0.000 description 1
- 239000012535 impurity Substances 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 239000012212 insulator Substances 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 150000002736 metal compounds Chemical class 0.000 description 1
- 230000001590 oxidative effect Effects 0.000 description 1
- 238000000206 photolithography Methods 0.000 description 1
- 239000003870 refractory metal Substances 0.000 description 1
- 238000004544 sputter deposition Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D64/00—Electrodes of devices having potential barriers
- H10D64/60—Electrodes characterised by their materials
- H10D64/66—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes
- H10D64/661—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes the conductor comprising a layer of silicon contacting the insulator, e.g. polysilicon having vertical doping variation
- H10D64/662—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes the conductor comprising a layer of silicon contacting the insulator, e.g. polysilicon having vertical doping variation the conductor further comprising additional layers, e.g. multiple silicon layers having different crystal structures
- H10D64/663—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes the conductor comprising a layer of silicon contacting the insulator, e.g. polysilicon having vertical doping variation the conductor further comprising additional layers, e.g. multiple silicon layers having different crystal structures the additional layers comprising a silicide layer contacting the layer of silicon, e.g. polycide gates
Abstract
(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.
Description
【発明の詳細な説明】
［発明の技術分野］
本発明は、ＭＯＳトランジスタからなる半導体装置に関
する。DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to a semiconductor device comprising a MOS transistor.
［発明の技術的背景とその問題点１
従来、集積回路に用いられるＭＯＳトランジスタは、例
えば第２図に示すような構造からなる。[Technical Background of the Invention and its Problems 1 Conventionally, a MOS transistor used in an integrated circuit has a structure as shown in FIG. 2, for example.
即ち、ＭｏＳトランジスタは、Ｐ型半導体基板１０の表
面に形成されたＮ型のソース１１及びドレイン１２を備
えている。ソース１１及びドレイン１２は、例えばヒ素
等の元素を拡散させて形成される拡散層からなる。That is, the MoS transistor includes an N-type source 11 and a drain 12 formed on the surface of a P-type semiconductor substrate 10. The source 11 and the drain 12 are made of a diffusion layer formed by diffusing an element such as arsenic, for example.
さらに、基板１０の表面上には、ゲートを構成する二酸
化シリコンからなるゲート絶縁膜１３が形成されている
。このゲート絶縁！１１１１３の表面上には、オーミッ
クコンタクト性を有する多結晶シリコン！ＩＩ （以下
ポリシリコン膜と称す）１４及びその表面上の高融点金
属又はその化合物からなる金属膜１５とからなる二層の
ゲート電極１６が形成されている。Further, on the surface of the substrate 10, a gate insulating film 13 made of silicon dioxide and forming a gate is formed. This gate insulation! On the surface of 11113 is polycrystalline silicon with ohmic contact properties! A two-layer gate electrode 16 is formed of a metal film 15 made of a high melting point metal or a compound thereof on the surface thereof.
金属ＩＩ＊１５は、例えばチタンシリサイド又はタング
ステンシリサイド等の化合物からなる。Metal II*15 is made of a compound such as titanium silicide or tungsten silicide.
ところで、例えば高集積化したＩＣメモリを構成する場
合、回路構成に必要な配線には低抵抗化が強く要求され
ている。このような高集積回路には、前記のような高融
点の金属膜１５を有するゲート電極からなるＭＯＳトラ
ンジスタが極めて有効に適用されることになる。しかし
ながら、このようなＭＯＳトランジスタの構造であると
、第３図に示すような多層構造の半導体装置を（形成し
た場合、ゲート電極材料である金属膜１５が接触する段
差部（ゲート配線部）ではステップカバレージが悪化す
るような問題がある。By the way, when configuring a highly integrated IC memory, for example, there is a strong demand for low resistance wiring for the circuit configuration. A MOS transistor having a gate electrode having a metal film 15 having a high melting point as described above is extremely effectively applied to such a highly integrated circuit. However, with such a MOS transistor structure, if a semiconductor device with a multilayer structure as shown in FIG. There is a problem where step coverage deteriorates.
［発明ゝの目的］
本発明の目的は、ＭＯＳトランジスタにおいて、高集積
回路を構成した場合、ゲート電極部でのステップカバレ
ージを向上して、安定な構造の半導体装置を提供するこ
とにある。[Object of the Invention] An object of the present invention is to provide a semiconductor device with a stable structure by improving step coverage in a gate electrode portion when a highly integrated circuit is constructed using a MOS transistor.
［発明の概要〕
本発明は、ＭＯＳトランジスタにおいて、そのゲート電
極の構造を二層の多結晶シリコン膜及びその各多結晶シ
リコン膜間に形成された高融点金属膜からなる三層構造
としたことが特徴である。[Summary of the Invention] The present invention provides a MOS transistor in which the gate electrode has a three-layer structure consisting of two layers of polycrystalline silicon films and a refractory metal film formed between the polycrystalline silicon films. is a feature.
このような構造のＭｏ８ トランジスタにより、低抵抗
特性を得ることができるとともに、ステップカバレージ
を向上することができる。With the Mo8 transistor having such a structure, low resistance characteristics can be obtained and step coverage can be improved.
［発明の実施例１
以下図面を参照して本発明の一実施例を説明する。第１
図は一実施例に係わるＭＯＳトランジスタの構成を示す
断面図である。第１図において、Ｐ型半導体基板１０の
表面上には、基板表面を酸化して二酸化シリコンからな
る酸化膜（ゲート絶縁膜１３）が形成される。ゲート絶
縁ｌｌ１１３の表面上には、多結晶シリコンからなるポ
リシリコン１１！１１４が気相成長法等により形成され
る。このポリシリコン膜１４の表面上に対して、ヒ素等
の第５属元素をイオン注入した後に、高融点金属化合物
からなる金属膜１５がスパッタ法等により形成される。[Embodiment 1 of the Invention An embodiment of the present invention will be described below with reference to the drawings. 1st
The figure is a cross-sectional view showing the configuration of a MOS transistor according to one embodiment. In FIG. 1, an oxide film (gate insulating film 13) made of silicon dioxide is formed on the surface of a P-type semiconductor substrate 10 by oxidizing the substrate surface. Polysilicon 11!114 made of polycrystalline silicon is formed on the surface of gate insulator 1113 by vapor phase growth or the like. After ion-implanting a group 5 element such as arsenic onto the surface of this polysilicon film 14, a metal film 15 made of a high melting point metal compound is formed by sputtering or the like.
この金属ｌｌ１１５は、例えばチタンシリサイド又はタ
ングステンシリサイド等からなり、ポリシリコンｉ！１
４とオーミックコンタクト性を得るように形成される。This metal 115 is made of, for example, titanium silicide or tungsten silicide, and is made of polysilicon i! 1
4 to obtain ohmic contact.
さらに、金属ＷＡ１５の表面上には、多結晶シリコンか
らなるポリシリコン膜１４が気相成長法等により形成さ
れる。このポリシリコン１１１４の表面上から、リン等
の不純物が金属膜１５の表面まで到達する加速電圧でイ
オン注入される。このようにして、二層のポリシリコン
膜１４及びそのポリシリコンｌ１１１４間に形成された
金属膜１５からなる三層構造のゲート＠ｔｉ２０が写真
蝕刻法により形成される。Furthermore, a polysilicon film 14 made of polycrystalline silicon is formed on the surface of the metal WA 15 by vapor phase growth or the like. From above the surface of this polysilicon 1114, impurities such as phosphorus are ion-implanted at an accelerating voltage that reaches the surface of metal film 15. In this way, a three-layered gate @ti20 consisting of two polysilicon films 14 and a metal film 15 formed between the two polysilicon films 1114 is formed by photolithography.
前記のようなゲート電極２０が形成された後、基板１０
の所定の表面領域に対して例えばヒ素又はリン等の元素
の熱拡散処理がなされる。これにより、Ｎ型拡散層であ
るソース１１及びドレイン１２が基板１０の表面に形成
される。この基板１０の表面には、ゲート絶縁膜１３と
同材質の二酸化シリコン膜が形成される。After the gate electrode 20 as described above is formed, the substrate 10 is
A thermal diffusion treatment of an element such as arsenic or phosphorus is performed on a predetermined surface area of the substrate. As a result, a source 11 and a drain 12, which are N-type diffusion layers, are formed on the surface of the substrate 10. A silicon dioxide film made of the same material as the gate insulating film 13 is formed on the surface of the substrate 10 .
このような構造のＭｏＳトランジスタにおいて、同実施
例の作用効果を説明する。先ず、ＭＯＳトランジスタの
ゲートを構成するゲート絶縁膜１３の表面上には、ポリ
シリコン膜１４と金属１１１５からなる二層構造が形成
されている。これにより、電気抵抗の低い低抵抗特性を
有するゲート電極２０を構成することができる。In the MoS transistor having such a structure, the effects of the same embodiment will be explained. First, a two-layer structure consisting of a polysilicon film 14 and a metal 1115 is formed on the surface of a gate insulating film 13 constituting the gate of a MOS transistor. Thereby, the gate electrode 20 having low electrical resistance and low resistance characteristics can be formed.
さらに、ゲート電極２０は轟融点金属である金属膜１５
の表面にポリシリコン膜１４を備えている。このため、
ゲート電極２０の表面上に二酸化シリコン膜等が形成さ
れて、この二酸化シリコン膜をマスクとしてゲート配線
が形成される場合、ゲート電極２０の表面上の段差部に
おけるゲート配線のステップカバレージは安定すること
になる。即ち、ゲート配線のステップカバレージは、金
属膜１５のない多結晶シリコンゲート上に形成されたゲ
ート配線の場合と同様となる。したがって、前記のよう
なゲート電極２０を備えたＭＯＳトランジスタを有する
高集積回路を構成した場合、安定なゲート配線構造の回
路を構成することができる。Furthermore, the gate electrode 20 is made of a metal film 15 made of a metal with a low melting point.
A polysilicon film 14 is provided on the surface. For this reason,
When a silicon dioxide film or the like is formed on the surface of the gate electrode 20 and a gate wiring is formed using this silicon dioxide film as a mask, the step coverage of the gate wiring at the stepped portion on the surface of the gate electrode 20 is stable. become. That is, the step coverage of the gate wiring is similar to that of a gate wiring formed on a polycrystalline silicon gate without the metal film 15. Therefore, when a highly integrated circuit including a MOS transistor including the gate electrode 20 as described above is constructed, a circuit with a stable gate wiring structure can be constructed.
［発明の効果〕
以上詳述したように本発明によれば、ＭＯＳトランジス
タのゲート電極部でのステップカバレージを向上でき、
しかも低抵抗特性の優れたゲート電極部を形成すること
ができる。したがって、メモリ等の高集積回路を構成し
た場合、ゲート配線部の構造を安定することが可能とな
り、安定で確実に動作する半導体装置を提供できるもの
である。[Effects of the Invention] As detailed above, according to the present invention, step coverage at the gate electrode portion of a MOS transistor can be improved;
Moreover, a gate electrode portion with excellent low resistance characteristics can be formed. Therefore, when a highly integrated circuit such as a memory is configured, the structure of the gate wiring portion can be stabilized, and a semiconductor device that operates stably and reliably can be provided.
第１図は本発明の一実施例に係わるＭＯＳトランジスタ
の構成を示す断面図、第２図は従来のＭＯＳトランジス
タの構成を示す断面図、第３図は第２図のＭｏＳトラン
ジスタを有する高集積回路を構成した場合の断面図であ
る。
１０・・・Ｐ型半導体基板、１１・・・ソース、１２・
・・ドレイン、１３・・・ゲート絶縁膜、１４・・・ポ
リシリコン膜、１５・・・金属膜。
出願人代理人 弁理士 鈴 江 武 彦第１図
Ｕ
第２図
朽
第３図FIG. 1 is a cross-sectional view showing the structure of a MOS transistor according to an embodiment of the present invention, FIG. 2 is a cross-sectional view showing the structure of a conventional MOS transistor, and FIG. 3 is a highly integrated structure having the MoS transistor of FIG. It is a sectional view when a circuit is constituted. DESCRIPTION OF SYMBOLS 10... P-type semiconductor substrate, 11... Source, 12.
...Drain, 13...Gate insulating film, 14...Polysilicon film, 15...Metal film. Applicant's representative Patent attorney Takehiko Suzue Figure 1 U Figure 2 Figure 3
Claims (1)
形成された基板の表面上に形成された二酸化シリコンか
らなるゲート絶縁膜と、二層の多結晶シリコン膜及びそ
の二層の多結晶シリコン膜間に形成された高融点金属又
はその化合物からなる金属膜からなる三層構造で前記ゲ
ート絶縁膜の表面上に形成されてなるゲート電極部とを
具備したことを特徴とする半導体装置。In a MOS transistor, a gate insulating film made of silicon dioxide formed on the surface of a substrate on which a source and a drain are formed, a two-layer polycrystalline silicon film, and a gate insulating film formed between the two layers of polycrystalline silicon films. What is claimed is: 1. A semiconductor device comprising: a gate electrode portion having a three-layer structure made of a metal film made of a high melting point metal or a compound thereof and formed on the surface of the gate insulating film.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP59271837A JPS61150376A (en) | 1984-12-25 | 1984-12-25 | semiconductor equipment |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP59271837A JPS61150376A (en) | 1984-12-25 | 1984-12-25 | semiconductor equipment |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS61150376A true JPS61150376A (en) | 1986-07-09 |
Family
ID=17505552
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP59271837A Pending JPS61150376A (en) | 1984-12-25 | 1984-12-25 | semiconductor equipment |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS61150376A (en) |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH01120867A (en) * | 1987-11-04 | 1989-05-12 | Seiko Epson Corp | Mis semiconductor device |
| EP0339586A2 (en) * | 1988-04-25 | 1989-11-02 | Nec Corporation | Semiconductor device having improved gate capacitance and manufacturing method therefor |
| JPH0512153U (en) * | 1991-07-26 | 1993-02-19 | 日本ビクター株式会社 | Thermal transfer printer |
| US5543362A (en) * | 1995-03-28 | 1996-08-06 | Motorola, Inc. | Process for fabricating refractory-metal silicide layers in a semiconductor device |
-
1984
- 1984-12-25 JP JP59271837A patent/JPS61150376A/en active Pending
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH01120867A (en) * | 1987-11-04 | 1989-05-12 | Seiko Epson Corp | Mis semiconductor device |
| EP0339586A2 (en) * | 1988-04-25 | 1989-11-02 | Nec Corporation | Semiconductor device having improved gate capacitance and manufacturing method therefor |
| JPH0512153U (en) * | 1991-07-26 | 1993-02-19 | 日本ビクター株式会社 | Thermal transfer printer |
| US5543362A (en) * | 1995-03-28 | 1996-08-06 | Motorola, Inc. | Process for fabricating refractory-metal silicide layers in a semiconductor device |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US5168340A (en) | Semiconductor integrated circuit device with guardring regions to prevent the formation of an MOS diode | |
| KR970077674A (en) | Manufacturing method of semiconductor integrated circuit device | |
| JP2633584B2 (en) | Semiconductor device and manufacturing method thereof | |
| US5521416A (en) | Semiconductor device having gate electrode and impurity diffusion layer different in conductivity type and method of manufacturing the same | |
| JPS61150376A (en) | semiconductor equipment | |
| JP2729422B2 (en) | Semiconductor device | |
| JP3013628B2 (en) | Semiconductor device | |
| JPS58215055A (en) | Semiconductor integrated circuit device | |
| JPH04316333A (en) | Manufacturing method of thin film transistor | |
| JPH0324056B2 (en) | ||
| JPS59169179A (en) | Semiconductor integrated circuit device | |
| JPS63241965A (en) | Insulated gate field effect transistor and its manufacturing method | |
| JPS6098666A (en) | Semiconductor memory device | |
| JPS6240765A (en) | Read-only semiconductor memory and manufacture thereof | |
| JPH0387061A (en) | semiconductor equipment | |
| JPS61228661A (en) | Semiconductor device and its manufacturing method | |
| JPS5897869A (en) | Manufacture of semiconductor device | |
| JPH0666427B2 (en) | Method for manufacturing MOS semiconductor integrated circuit device | |
| JPS58212133A (en) | Manufacture of semiconductor device | |
| JPS625657A (en) | Semiconductor integrated circuit device | |
| JPH0251259B2 (en) | ||
| JPS626664B2 (en) | ||
| JPH0239471A (en) | Mos field-effect transistor and conductor structure | |
| JPH02156542A (en) | Semiconductor device and manufacture thereof | |
| JPH1117165A (en) | Laminated gate structure in semiconductor device |