JPS61133646A - Manufacture of semiconductor device - Google Patents
Manufacture of semiconductor deviceInfo
- Publication number
- JPS61133646A JPS61133646A JP25550084A JP25550084A JPS61133646A JP S61133646 A JPS61133646 A JP S61133646A JP 25550084 A JP25550084 A JP 25550084A JP 25550084 A JP25550084 A JP 25550084A JP S61133646 A JPS61133646 A JP S61133646A
- Authority
- JP
- Japan
- Prior art keywords
- film
- layer
- barrier metal
- contact
- forming
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Landscapes
- Electrodes Of Semiconductors (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
Description
【発明の詳細な説明】
〔発明の技術分野〕
本発明は、半導体装置の製造方法に係り、特に、半導体
基板上に形成された拡散層領域と配線層との間に高い信
頼性をもつ微細面積のコンタクト電極を形成する方法に
関する。DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to a method for manufacturing a semiconductor device, and particularly to a method for manufacturing a semiconductor device, and in particular, a method for manufacturing a semiconductor device using a highly reliable microstructure between a diffusion layer region formed on a semiconductor substrate and a wiring layer. The present invention relates to a method of forming a contact electrode of an area.
半導体装置の分野では、1970年代以降、特に、高集
積化への傾向は強まる一方となり、超大規模集積回路(
超LSI)へと進歩し、1つの半導体チップ上にコンピ
ュータ等のシステムが構成されるまでになってきている
。In the field of semiconductor devices, since the 1970s, the trend towards higher integration has been particularly strong, and ultra-large scale integrated circuits (
The technology has advanced to the point where systems such as computers can now be constructed on a single semiconductor chip.
ところで集積回路の高速化と高集積化は素子の微細化に
よって実現される。例えばMO8集積回路では、素子の
微細化に伴い、多結晶シリコンゲート電極や、ソース拡
散層、ドレイン拡散層等と金属配線層との間で電気的接
続を行うためのコンタクト部の面積は縮小されると共に
PN接合の深さについても浅くなるように形成されるこ
とが必要となってくる。Incidentally, higher speed and higher integration of integrated circuits are achieved by miniaturization of elements. For example, in MO8 integrated circuits, as devices become smaller, the area of contact areas for electrical connections between polycrystalline silicon gate electrodes, source diffusion layers, drain diffusion layers, etc. and metal wiring layers is reduced. At the same time, it becomes necessary to form the PN junction to have a shallow depth.
しかしながら、コンタクト面線の縮小化あるいはPN接
合が浅く形成されるのに伴い、配線材料としてアルミニ
ウムーシリコン合金を用いた場合においても、アルミニ
ウム中に含まれる過剰シリコンの析出によるコンタクト
抵抗の増加や浅いPN接合の破壊等の問題が顕在化して
くる。特に超LSIの場合、数ミリ角のシリランチ21
1個当たり、百万個以上のコンタクトが存在するため、
このような接続特性の劣化は素子の信頼性の低下につな
がり、集積回路の高速化、高集積化への大きな障害とな
っている。However, as the contact surface lines become smaller or PN junctions are formed shallower, even when aluminum-silicon alloy is used as the wiring material, contact resistance increases due to the precipitation of excess silicon contained in aluminum and Problems such as destruction of PN junctions become apparent. Especially in the case of VLSI, a few millimeter square siri lunch 21
Since there are more than 1 million contacts per person,
Such deterioration of connection characteristics leads to a decrease in the reliability of elements, and is a major obstacle to increasing the speed and integration of integrated circuits.
例えば、第5図に示す如くP型のシリコン(8i)基板
21内に砒素(As)イオンをイオン注入して形成され
たPN接合の深さX=0.1μ仇となるようなN+型の
シリコン拡散層ηに対し、絶縁膜n内に穿孔されたコン
タクト窓冴を介してアルミニウム(A1)電極5を形成
した場合、該N+型のシリコン拡散層nとアルミニウム
電極5の間でシリコンとアルミニウムの相互作用に基づ
く界面反応によって前記PN接合部がショートすること
がある。For example, as shown in FIG. 5, the depth of the PN junction formed by implanting arsenic (As) ions into a P-type silicon (8i) substrate 21 is 0.1μ. When an aluminum (A1) electrode 5 is formed with respect to the silicon diffusion layer η through a contact window drilled in the insulating film n, silicon and aluminum are formed between the N+ type silicon diffusion layer n and the aluminum electrode 5. The PN junction may be short-circuited due to an interfacial reaction based on the interaction.
このような問題を解決する技術として、前記N+型のシ
リコン拡散層nとアルミニウム電極5との間に前述の如
き界面反応が発生するのを防止するため、障壁金属(バ
リヤーメタル)を形成する方法が注目されている。As a technique for solving this problem, there is a method of forming a barrier metal in order to prevent the above-mentioned interfacial reaction from occurring between the N+ type silicon diffusion layer n and the aluminum electrode 5. is attracting attention.
この方法は、例えば第6図に示す如く、P型のシリコン
基板21内に形成されたN+型のシリコン拡散層乙に対
応する位置にコンタクト窓Uを有するような絶縁層部を
形成した後、コンタクト電極5としてのアルミニウム層
の形成に先立ち、スパッタリング法により、全面にバリ
ヤーメタルとして窒化チタン膜がを形成しようというも
のであるが、この方法は、また以下に述べるような欠点
を有している。In this method, for example, as shown in FIG. 6, after forming an insulating layer portion having a contact window U at a position corresponding to an N+ type silicon diffusion layer B formed in a P type silicon substrate 21, Prior to forming the aluminum layer as the contact electrode 5, a titanium nitride film is formed as a barrier metal over the entire surface by sputtering, but this method also has the following drawbacks. .
すなわち、通常のスパッタリング法により、バリヤーメ
タルを形成した場合、コンタクト窓列の周囲におけるバ
リヤーメタルの膜厚は、平坦部でと薄くなる上、この部
分でバリヤーメタルの膜応力による歪が集中して膜にク
ラックが発生し易くなる。このように、バリヤーメタル
を形成したにもかかわらずバリヤー効果がなくなり、ア
ルミニウム層がとN+型のシリコン拡散層匹とが反応し
て第7図に示す如く、N+型シリコンがアルミニウム層
中へ溶は出し、シリコン原子の放出路にアルミニウムが
くさび状に浸入することがあった。これは、拡散層の突
き抜゛げごと呼ばれ、接合破壊の原因となっていた。In other words, when a barrier metal is formed by a normal sputtering method, the film thickness of the barrier metal around the contact window row is thinner at the flat parts, and the strain due to film stress of the barrier metal is concentrated in these parts. Cracks are likely to occur in the film. In this way, despite the formation of the barrier metal, the barrier effect disappears, and the aluminum layer reacts with the N+ type silicon diffusion layer, causing N+ type silicon to dissolve into the aluminum layer, as shown in Figure 7. Aluminum sometimes penetrated into the release path of silicon atoms in a wedge shape. This is called penetration of the diffusion layer, and is a cause of bond failure.
また、スパッタリング法によってバリヤーメタルを形成
する場合、拡散層表面に、シリコンの自然酸化膜が生成
され、接触抵抗が高くなるという問題があった。この問
題を解決するため、バリヤーメタルの形成に先立ち、ア
ルゴンイオン等を用いたスパッタエツチングによるシリ
コン自然酸化膜のクリーニング工程を付加するというよ
うな技術も提案されてはいるが、スパッタリングによる
ダメージあるいは装置内におけるデバイスの汚染等の問
題を依然として残している。Furthermore, when forming the barrier metal by sputtering, a natural oxide film of silicon is formed on the surface of the diffusion layer, resulting in an increase in contact resistance. In order to solve this problem, a technique has been proposed in which a cleaning process of the silicon natural oxide film is performed by sputter etching using argon ions, etc. prior to the formation of the barrier metal. However, there still remain problems such as contamination of devices within the system.
このように、スパッタリング法によってバリヤーメタル
を形成する方法では、接触抵抗が充分に低く、素子とし
ての信頼性の高いコンタクト電極を実現するには、多く
の問題があり、実用化は困難な状態であった。In this way, with the method of forming barrier metals by sputtering, there are many problems in realizing contact electrodes with sufficiently low contact resistance and high reliability as devices, making it difficult to put them into practical use. there were.
本発明は、前記実情に鑑みてなされたもので、微細でか
つ浅い半導体層(拡散層)をもつ基板に対しても、接合
特性を劣化させることなく、配線層と半導体層(拡散層
)との間に、低抵抗でかつ信頼性の高いオーミックコン
タクトを形成することを目的とする。The present invention has been made in view of the above-mentioned circumstances, and it is possible to connect a wiring layer and a semiconductor layer (diffusion layer) without deteriorating the bonding characteristics even for a substrate having a fine and shallow semiconductor layer (diffusion layer). The purpose is to form a low-resistance and highly reliable ohmic contact between the two.
そこで、本発明の方法では、拡散層等の半導体層を有す
る基板の表面に形成された絶縁膜上にコンタクト窓を形
成した後、まず、気相成長法により該コンタクト窓内に
露呈する基板の表面に選択的に高融点金属を形成し、こ
の後、バリヤーメタル、配線層を順次形成するようにし
ている。Therefore, in the method of the present invention, after forming a contact window on an insulating film formed on the surface of a substrate having a semiconductor layer such as a diffusion layer, first, a vapor phase epitaxy method is used to remove the substrate exposed within the contact window. A high melting point metal is selectively formed on the surface, and then a barrier metal and a wiring layer are sequentially formed.
〔発明の効果〕
すなわち、拡散層(半導体層)に対するコンタクト窓を
穿孔した後、スパッタリング法によりバリヤーメタルを
形成するに先立ち、金属化合物ガスを用いた高融点金属
の気相成長工程を導入することにより、基板表面を覆う
絶縁膜に形成されたコンタクト窓内にのみ選択的に高融
点金属膜が析出せしめられ、コンタクト窓の存在による
段差が緩和されるため、バリヤーメタルの膜厚が薄くな
る部分がほとんどなくなり、はぼ均一な膜厚のバリヤー
メタルが形成され、拡散層(半導体層)の突き抜けによ
る接合破壊はほとんど皆無となる。[Effects of the Invention] That is, after drilling a contact window for the diffusion layer (semiconductor layer) and before forming a barrier metal by sputtering, a vapor phase growth process of a high melting point metal using a metal compound gas is introduced. As a result, a high melting point metal film is selectively deposited only within the contact window formed in the insulating film covering the substrate surface, and the step difference due to the presence of the contact window is alleviated, so the barrier metal film thickness is reduced in the area where the barrier metal film is thinner. The barrier metal is almost completely eliminated, and the barrier metal has an almost uniform thickness, and there is almost no junction breakdown due to penetration of the diffusion layer (semiconductor layer).
また、気相成長法によって高融点金属膜が形成される際
に、半導体層(拡散層)と反応し、高融点金属が成長せ
しめられるという過程をとるため、基板表面上の自然酸
化膜は完全に除去され、極めて低抵抗のオーミックコン
タクトが実現可能となる。In addition, when a high melting point metal film is formed by vapor phase growth, the natural oxide film on the substrate surface is completely removed because it reacts with the semiconductor layer (diffusion layer) and grows the high melting point metal. This makes it possible to realize an ohmic contact with extremely low resistance.
このように、本発明の方法によれば、微細でかつ浅い拡
散層をもつ基板に対し、低抵抗でかつ極めて信頼性の高
い、拡散層へのオーミックコンタクトの形成が可能とな
る。As described above, according to the method of the present invention, it is possible to form a low resistance and extremely reliable ohmic contact to the diffusion layer on a substrate having a fine and shallow diffusion layer.
以下、本発明の実施例を、図面を参照しつつ詳細に説明
する。第1図に示すのは、本発明の一実施例の方法によ
って形成された半導体装置の構造を示すもので、P型の
シリコン基板1内のN+型のシリコン拡散層2に対応す
る部分にコンタクト窓3を有する絶縁膜4が形成されて
おり、このコンタクト窓3内に高融点金属層としてタン
グステン膜5が形成され、この上膜にバリヤーメタルと
しての窒化チタン膜6、そして電極配線層としてのアル
ミニウム膜7が順次形成されている。Embodiments of the present invention will be described in detail below with reference to the drawings. FIG. 1 shows the structure of a semiconductor device formed by the method of one embodiment of the present invention, in which a contact is made in a portion corresponding to an N+ type silicon diffusion layer 2 in a P type silicon substrate 1. An insulating film 4 having a window 3 is formed, a tungsten film 5 is formed as a high-melting point metal layer in this contact window 3, a titanium nitride film 6 is formed as a barrier metal on top of this film, and a titanium nitride film 6 is formed as an electrode wiring layer. Aluminum films 7 are sequentially formed.
次に、かかる構造の半導体装置の形成方法を説明する。Next, a method for forming a semiconductor device having such a structure will be explained.
まず、第2図に示す如く、P型のシリコン基板1上に砒
素(AS)をイオン注入することによって形成されたP
N接合深さX=0.1μmのN+型のシリコン拡散層2
0表面金体に絶縁膜として酸化シ」ノコン膜4を堆積し
、これにフォトリソエツチング法等により、コンタクト
窓3を穿孔する。(このときのエツチングは、反応性イ
オンエツチングを用いて行なう。)
次いで、第3図に示す如く、六弗化タングステン(WF
6 )とアルゴン(Ar)との混合ガスを用いた気相成
長法により、高融点金属被膜としてタングステン(W)
膜5を前記コンタクト窓3内に露呈するN+型のシリコ
ン拡散層2上にのみ選択的に形成する。形成条件として
は、基板温度は250〜450”O,反応炉内の圧力は
1×10−2〜760ちrr。First, as shown in FIG.
N+ type silicon diffusion layer 2 with N junction depth X = 0.1 μm
A silicon oxide film 4 is deposited as an insulating film on the zero surface gold body, and a contact window 3 is bored therein by photolithography or the like. (Etching at this time is performed using reactive ion etching.) Next, as shown in Figure 3, tungsten hexafluoride (WF
6) and argon (Ar) as a high-melting point metal coating by a vapor phase growth method using a mixed gas of argon (Ar).
A film 5 is selectively formed only on the N+ type silicon diffusion layer 2 exposed within the contact window 3. The formation conditions include a substrate temperature of 250 to 450"O, and a pressure in the reactor of 1.times.10@-2 to 760".
六弗化タングステンガスの分圧はI X 10−’〜5
×10−2の範囲にとるのが望ましい。また、膜厚は2
00〜1000 ;、とするのが望ましい。The partial pressure of tungsten hexafluoride gas is I x 10-'~5
It is desirable to set it in the range of x10-2. Also, the film thickness is 2
It is desirable to set it as 00-1000;.
この後、スパッタリング法により、バリヤーメタルとし
て窒化チタン膜(TiN ) 6を通常の形成条件で、
膜厚500〜1000 Aとなるように形成する。(第
4図)
そして最後に、コンタクト用電極および電極配線層とし
てのアルミニウム膜7を形成し、第1図に示したような
半導体装置が完成する。After this, a titanium nitride film (TiN) 6 is formed as a barrier metal by sputtering under normal conditions.
It is formed to have a film thickness of 500 to 1000 Å. (FIG. 4) Finally, an aluminum film 7 is formed as a contact electrode and an electrode wiring layer, and the semiconductor device as shown in FIG. 1 is completed.
このようにして形成されたコンタクト用電極は、N+型
シリコン拡散層上に自然酸化膜が残留していない状態で
被着せしめられたタングステン膜上に、バリヤーメタル
としての窒化チタン膜を介しく8)
て形成されているため、コンタクト抵抗が低く抑えられ
る。すなわち、タングステン膜の成長は、N+型のシリ
コン拡散層表面におけるシリコンとの反応によって進む
ため、前記自然酸化膜は完全に除去された状態でタング
ステン膜が被着せしめられており、コンタクト電極部が
1.0μm口以下の微細なものについても、コンタクト
抵抗を数十Ω程度におさえることができる。The contact electrode thus formed is formed on the tungsten film, which is deposited on the N+ type silicon diffusion layer without any natural oxide film remaining, through a titanium nitride film as a barrier metal. ), contact resistance can be kept low. That is, since the growth of the tungsten film progresses through reaction with silicon on the surface of the N+ type silicon diffusion layer, the tungsten film is deposited with the natural oxide film completely removed, and the contact electrode portion is Contact resistance can be suppressed to about several tens of ohms even for microscopic devices with a diameter of 1.0 μm or less.
また、バリヤーメタルとしての窒化チタン膜をスパッタ
リング法によって形成するに際しても、その下層のタン
グステン膜が均一な膜厚でコンタクト窓内に充填されて
いるため、コンタクト窓による段差が緩和され、はぼ均
一な膜厚の窒化チタン膜が形成し得ることになり、充分
なバリヤー効果を有するため、コンタクト電極としての
アルミニウム膜と拡散層との間に相互作用が生じること
もなく、デバイスとしての信頼性は極めて高いものとな
る。In addition, when forming a titanium nitride film as a barrier metal by sputtering, the underlying tungsten film is filled into the contact window with a uniform thickness, which reduces the level difference caused by the contact window and makes it more uniform. A titanium nitride film with a thickness of It will be extremely expensive.
なお、実施例においては、コンタクト窓内に形成する高
融点被膜として、六弗化タングステンを反応ガスとして
用いた気相成長法によって形成されるタングステン膜を
用いたが、反応ガスとして、塩化タングステン化合物6
等の他のタングステン化合物を用いて形成されるタング
ステン膜を用いたり、更には、モリブデン(Mo)、ニ
オブ(Nb )、タンタル(Ta)、チタン(Ti)の
弗化物、塩化物等による気相成長膜等から選択したもの
を使用してもよい。In the example, a tungsten film formed by a vapor phase growth method using tungsten hexafluoride as a reactive gas was used as a high melting point film to be formed within the contact window, but a tungsten chloride compound was used as the reactive gas. 6
It is also possible to use a tungsten film formed using other tungsten compounds such as tungsten compounds, etc., or use a gas phase film formed using fluorides, chlorides, etc. of molybdenum (Mo), niobium (Nb), tantalum (Ta), titanium (Ti), etc. A film selected from grown films and the like may be used.
また、実施例においては、バリヤーメタルとして窒化チ
タン膜を用いたが、その他車化タンタル、窒化ハフニウ
ムを用いてもよいことはいうまでもない。Further, in the embodiment, a titanium nitride film was used as the barrier metal, but it goes without saying that tantalum or hafnium nitride may also be used.
第1図は、本発明実施例の方法によって形成された半導
体装置のコンタクト部を示す図、第2図乃至第4図は、
同装置の製造工程を示す図、第5図乃至第7図は、従来
例を示す図である。
1・・・シリコン基板、2・・・シリコン拡散層、3・
・・コンタクト窓、4・・・酸化シリコン膜、5・・・
タングステン膜、6・・・窒化チタン膜、7・・・アル
ミニウム膜、21・・・シリコン基板、n・・・シリコ
ン拡散層、n・・・絶縁膜、U・・・コンタクト窓、5
・・・アルミニウム電極、26・・・窒化チタン膜。FIG. 1 is a diagram showing a contact portion of a semiconductor device formed by the method of an embodiment of the present invention, and FIGS. 2 to 4 are
Figures 5 to 7 showing the manufacturing process of the device are diagrams showing conventional examples. 1... Silicon substrate, 2... Silicon diffusion layer, 3.
...Contact window, 4...Silicon oxide film, 5...
Tungsten film, 6... Titanium nitride film, 7... Aluminum film, 21... Silicon substrate, n... Silicon diffusion layer, n... Insulating film, U... Contact window, 5
...Aluminum electrode, 26...Titanium nitride film.
Claims (2)
、障壁金属層を介して該半導体層に電気的に接続される
電極配線層を形成する方法であって、前記絶縁膜に対し
、前記半導体層へのコンタクト用窓明けを行なう穿孔工
程の後、前記障壁金属層および電極配線層の形成工程に
先立ち、形成された前記コンタクト用窓内に気相成長法
により高融点金属を選択的に被着する工程とを備えたこ
とを特徴とする半導体装置の製造方法。(1) A method for forming an electrode wiring layer electrically connected to the semiconductor layer via a barrier metal layer on an insulating film formed on a substrate having a semiconductor layer, the method comprising: , after the drilling step of forming a contact window in the semiconductor layer, and prior to the step of forming the barrier metal layer and the electrode wiring layer, a high melting point metal is selected in the formed contact window by a vapor phase growth method. 1. A method for manufacturing a semiconductor device, comprising a step of depositing the semiconductor device.
を防ぐものであることを特徴とする特許請求の範囲第(
1)項に記載した半導体装置の製造方法。(2) The barrier metal layer prevents an interfacial reaction between the semiconductor layer and the electrode wiring layer.
1) A method for manufacturing the semiconductor device described in item 1).
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP25550084A JPS61133646A (en) | 1984-12-03 | 1984-12-03 | Manufacture of semiconductor device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP25550084A JPS61133646A (en) | 1984-12-03 | 1984-12-03 | Manufacture of semiconductor device |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS61133646A true JPS61133646A (en) | 1986-06-20 |
Family
ID=17279610
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP25550084A Pending JPS61133646A (en) | 1984-12-03 | 1984-12-03 | Manufacture of semiconductor device |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS61133646A (en) |
Cited By (12)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS6384154A (en) * | 1986-09-29 | 1988-04-14 | Toshiba Corp | Manufacture of semiconductor device |
JPS63174319A (en) * | 1987-01-14 | 1988-07-18 | Hitachi Ltd | Manufacture of semiconductor device |
JPH02290019A (en) * | 1989-02-02 | 1990-11-29 | Matsushita Electric Ind Co Ltd | Manufacture of electrode wiring structure body and semiconductor integrated circuit device |
JPH0442952A (en) * | 1990-06-06 | 1992-02-13 | Matsushita Electron Corp | Electrode wiring of semiconductor device and formation thereof |
JPH06342790A (en) * | 1993-05-31 | 1994-12-13 | Nec Corp | Manufacture of semiconductor device |
US5847459A (en) * | 1994-08-31 | 1998-12-08 | Fujitsu Limited | Multi-level wiring using refractory metal |
KR100332131B1 (en) * | 1995-12-18 | 2002-11-04 | 주식회사 하이닉스반도체 | Method for forming metal film in semiconductor device |
US10833199B2 (en) | 2016-11-18 | 2020-11-10 | Acorn Semi, Llc | Nanowire transistor with source and drain induced by electrical contacts with negative Schottky barrier height |
US10872964B2 (en) | 2016-06-17 | 2020-12-22 | Acorn Semi, Llc | MIS contact structure with metal oxide conductor |
US10879366B2 (en) | 2011-11-23 | 2020-12-29 | Acorn Semi, Llc | Metal contacts to group IV semiconductors by inserting interfacial atomic monolayers |
US10937880B2 (en) | 2002-08-12 | 2021-03-02 | Acorn Semi, Llc | Method for depinning the Fermi level of a semiconductor at an electrical junction and devices incorporating such junctions |
US11043571B2 (en) | 2002-08-12 | 2021-06-22 | Acorn Semi, Llc | Insulated gate field effect transistor having passivated schottky barriers to the channel |
Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5021225A (en) * | 1973-06-29 | 1975-03-06 | ||
JPS5998535A (en) * | 1982-11-29 | 1984-06-06 | Hitachi Ltd | Manufacture of semiconductor integrated circuits |
-
1984
- 1984-12-03 JP JP25550084A patent/JPS61133646A/en active Pending
Patent Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5021225A (en) * | 1973-06-29 | 1975-03-06 | ||
JPS5998535A (en) * | 1982-11-29 | 1984-06-06 | Hitachi Ltd | Manufacture of semiconductor integrated circuits |
Cited By (22)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS6384154A (en) * | 1986-09-29 | 1988-04-14 | Toshiba Corp | Manufacture of semiconductor device |
JPS63174319A (en) * | 1987-01-14 | 1988-07-18 | Hitachi Ltd | Manufacture of semiconductor device |
JPH02290019A (en) * | 1989-02-02 | 1990-11-29 | Matsushita Electric Ind Co Ltd | Manufacture of electrode wiring structure body and semiconductor integrated circuit device |
JPH0442952A (en) * | 1990-06-06 | 1992-02-13 | Matsushita Electron Corp | Electrode wiring of semiconductor device and formation thereof |
JPH06342790A (en) * | 1993-05-31 | 1994-12-13 | Nec Corp | Manufacture of semiconductor device |
US5847459A (en) * | 1994-08-31 | 1998-12-08 | Fujitsu Limited | Multi-level wiring using refractory metal |
US6204167B1 (en) * | 1994-08-31 | 2001-03-20 | Fujitsu Limited | Method of making a multi-level interconnect having a refractory metal wire and a degassed oxidized, TiN barrier layer |
KR100332131B1 (en) * | 1995-12-18 | 2002-11-04 | 주식회사 하이닉스반도체 | Method for forming metal film in semiconductor device |
US11056569B2 (en) | 2002-08-12 | 2021-07-06 | Acorn Semi, Llc | Method for depinning the fermi level of a semiconductor at an electrical junction and devices incorporating such junctions |
US11043571B2 (en) | 2002-08-12 | 2021-06-22 | Acorn Semi, Llc | Insulated gate field effect transistor having passivated schottky barriers to the channel |
US11355613B2 (en) | 2002-08-12 | 2022-06-07 | Acorn Semi, Llc | Method for depinning the Fermi level of a semiconductor at an electrical junction and devices incorporating such junctions |
US10937880B2 (en) | 2002-08-12 | 2021-03-02 | Acorn Semi, Llc | Method for depinning the Fermi level of a semiconductor at an electrical junction and devices incorporating such junctions |
US10950707B2 (en) | 2002-08-12 | 2021-03-16 | Acorn Semi, Llc | Method for depinning the Fermi level of a semiconductor at an electrical junction and devices incorporating such junctions |
US11018237B2 (en) | 2002-08-12 | 2021-05-25 | Acorn Semi, Llc | Method for depinning the fermi level of a semiconductor at an electrical junction and devices incorporating such junctions |
US11610974B2 (en) | 2011-11-23 | 2023-03-21 | Acorn Semi, Llc | Metal contacts to group IV semiconductors by inserting interfacial atomic monolayers |
US10879366B2 (en) | 2011-11-23 | 2020-12-29 | Acorn Semi, Llc | Metal contacts to group IV semiconductors by inserting interfacial atomic monolayers |
US11804533B2 (en) | 2011-11-23 | 2023-10-31 | Acorn Semi, Llc | Metal contacts to group IV semiconductors by inserting interfacial atomic monolayers |
US10872964B2 (en) | 2016-06-17 | 2020-12-22 | Acorn Semi, Llc | MIS contact structure with metal oxide conductor |
US11843040B2 (en) | 2016-06-17 | 2023-12-12 | Acorn Semi, Llc | MIS contact structure with metal oxide conductor |
US10833199B2 (en) | 2016-11-18 | 2020-11-10 | Acorn Semi, Llc | Nanowire transistor with source and drain induced by electrical contacts with negative Schottky barrier height |
US11462643B2 (en) | 2016-11-18 | 2022-10-04 | Acorn Semi, Llc | Nanowire transistor with source and drain induced by electrical contacts with negative Schottky barrier height |
US12034078B2 (en) | 2016-11-18 | 2024-07-09 | Acorn Semi, Llc | Nanowire transistor with source and drain induced by electrical contacts with negative Schottky barrier height |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
US6309967B1 (en) | Method of forming a contact | |
EP0525637B1 (en) | Method for the formation of tin barrier layer with preferential (111) crystallographic orientation | |
KR100243286B1 (en) | Method for manufacturing a semiconductor device | |
JP2985692B2 (en) | Semiconductor device wiring structure and method of manufacturing the same | |
JPH0653163A (en) | Integrated-circuit barrier structure and its manufacture | |
JPS61133646A (en) | Manufacture of semiconductor device | |
JP3113800B2 (en) | Method for forming wiring of semiconductor device | |
KR100338941B1 (en) | Contact forming method for semiconductor device | |
JPS61144872A (en) | Semiconductor device | |
JPS6135517A (en) | Formation of semiconductor device | |
US6239015B1 (en) | Semiconductor device having polysilicon interconnections and method of making same | |
US6239029B1 (en) | Sacrificial germanium layer for formation of a contact | |
US5461006A (en) | Method for forming contacts with anomalously low resistance | |
JPS6292470A (en) | Semiconductor device | |
US5350711A (en) | Method of fabricating high temperature refractory metal nitride contact and interconnect structure | |
JPH03102819A (en) | Manufacture of semiconductor device | |
JPS6324668A (en) | Semiconductor device | |
JP3337758B2 (en) | Method for manufacturing semiconductor device | |
JP2694950B2 (en) | Method of forming high melting point metal film | |
JPH02235372A (en) | Semiconductor device and its manufacture | |
JP2541657B2 (en) | Diffusion barrier structure and manufacturing method thereof | |
JP3017810B2 (en) | Method for manufacturing semiconductor device | |
JPS6195517A (en) | Manufacture of semiconductor device | |
JP2754653B2 (en) | Aluminum wiring formation method | |
JPS628542A (en) | Manufacture of semiconductor device |