JPS61131295A - Back-up device of dynamic ram - Google Patents

Abstract

PURPOSE:To refresh automatically a dynamic RAM regardless of the type at the time of turning off the electric power source by changing over an electric power source, and selecting and refreshing an address signal and an address reading command from a counter when the electric power source is abnormal. CONSTITUTION:When the electric power source abnormality is detected, the electric power source is changed over to a back-up electric power source of a battery, etc., by an electric power source off detecting circuit 11 and an electric power source change-over circuit 12, and an electric power source power is supplied only to an oscillator 7, a counter 8, selector 10, a memory part 1, etc. On the other hand, a selector 11 controlled by the circuit 11 selects a row address and a row address reading command which the counter 8 outputs, accessed by a row address and the memory part 1 row-address-select(RAS)-only- refreshed. Consequently, regardless of the type pf the dynamic RAS, the dynamic RAM is automatically refreshed when the electric power source is turned off.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to a backup device for backing up a dynamic RAM for data storage in a system to which a microcomputer or the like is applied.

[Technical background of the invention and its problems] gRAM (random access memory) is indispensable as a data storage element in various devices to which microcomputers and the like are applied. However, RAM has the disadvantage that it loses stored data when the power goes out. Some computers and microcomputer-applied equipment must retain stored data even in the event of a power outage, and use that data to resume operation when power is restored. It is necessary to back up the RAM.

Incidentally, RAM can be roughly divided into dynamic RAM and static RAM. Dynamic RAM has a large storage capacity per element and is inexpensive, but requires constant refreshing to retain memory. on the other hand,
Although static RAM does not require such refreshing, it has the disadvantage that the storage capacity per element is small.

However, static RAM includes C-MOS static RAM, which has extremely low power consumption, and although it is expensive, battery backup is possible, so if RAM backup is required during a power outage, this C-MOS static RAM is usually used. MOS static RAM is used.

However, (-MOS static RAM is expensive and has a smaller capacity than dynamic RAM, so the area used by the C-T MOS static RAM in the system is limited to a very small area of the memory area in consideration of product cost.) Therefore, the amount of data to be protected must be kept to a minimum.

However, in recent years, the amount of data that needs to be protected has become larger, and instantaneous power outages are always a possibility. It is desirable to retain the contents even during a power outage.

Therefore, it is desired to realize a dynamic RAM backup device.

[Object of the Invention] The present invention has been made in view of the above circumstances, and its object is to provide a dynamic RAM backup device that enables dynamic RAM backup.

[Summary of the Invention] That is, in order to achieve the above object, the present invention provides a means for detecting a power abnormality by detecting the level of a system power supply, and a means for detecting a power abnormality by detecting a power abnormality, as a backup device for a device using a dynamic RAM as a memory element. a power supply switching means that switches to an emergency power supply from a battery to supply the memory element when an abnormality in the power supply is detected; and an address signal and a row address signal for dynamic RAM refresh that operate from the emergency power supply when an abnormality in the power supply is detected; means for generating a read command signal; and when a power supply abnormality is detected, the address signal and row address signal @read command signal generated by the read command signal generating means are sent to the memory element. and a means for supplying an inactive column address read signal to the memory element, detecting this in the event of a power outage, switching the power supply to a battery, and using the output of this battery to read the address and control signals from the memory element and the counter. By supplying the generating means to generate address and control signals for refresh, and supplying these to the memory element to perform RAS-only refresh, any memory device using dynamic RAM can be used without power outage. Make it possible to back up the contents from time to time.

[Embodiment of the Invention] Hereinafter, an embodiment of the present invention will be described with reference to the drawings.

Figure 1 is a block diagram showing the configuration of this device.
2 is a memory section composed of a plurality of dynamic RAMs of, for example, 64 Kbit, and 2 is connected to a data input/output terminal of the memory section 1 through a data bus.

3 is an address bus, 4 is a control line that provides various control signals for the RAM, 5 is a control line and address bus from a processor (central processing unit; CPU) such as a microcomputer, and 6 is a power failure detection signal line that provides a power failure detection signal. , 7 is an oscillation circuit using, for example, a crystal oscillator; 8 is an eight-digit binary counter that receives and counts the oscillation output of the oscillation circuit 7; and 9 is an output signal bus of the counter 8. Further, 10 is a selector, and this selector 10 normally selects the control line and address bus 5 and connects it to the address bus 3.
A control signal and an address signal from the CPU are supplied to the power supply section 1 through the power supply line 6, and a power-off signal S, which is a power-off detection signal, is sent from the power-off detection signal line 6.
When C is received, the counter output signal bus 5 is selected from 1 to 1, connected to the address bus 3, and the output of the counter 8 is given to the memory section 1. The output from this counter 8 is 8
Digit output terminal Q1. ~ Among Q8, the least significant digit output terminal Q1 is used as the RAS signal, and the output terminal Q2 of the second digit to the output terminal Q8 of the eighth digit (most significant digit) is used as the address terminal of the dynamic RAM. They are given in correspondence to Ao and A6, respectively.

Reference numeral 11 denotes a power failure detection circuit, which detects a power failure based on the voltage of a system driving power source (hereinafter referred to as system power supply VCC) obtained from a commercial power source, and outputs a power failure signal SC. be. Reference numeral 12 denotes a power supply switching circuit, which has a battery backup power supply and normally selects and outputs the system power supply VCC. A backup power source is selected in place of the power source VCC and outputted as the supply output VCC2. The output power of this power supply switching circuit 12 is supplied to the memory section 1, the oscillation circuit 7, the counter 8, and the selector 10.

Note that there are various known circuits as the power-off detection circuit 11 and the power-supply switching circuit 12, and an appropriate circuit is used among them. For example, the one shown in FIG. 2 may be used.

To explain the configuration of the figure, the power failure detection circuit 11 uses a PNP type transistor T1, the emitter of this transistor T1 is connected to the system voltage 'tAVCG, and a resistor R1 is connected between the emitter and the base. Further, the base of this transistor T1 is connected to a resistor R2, and furthermore, 3 to 3
．． It is grounded through a series circuit including a Zener diode ZD having a Zener voltage of about 5V. The Zener diode ZD is connected in the opposite direction. Also, the transistor T
The collector of No. 1 is grounded via a resistor R3.

The above is an example of the configuration of the power-off detection circuit 11.

-The power supply switching circuit 12 consists of PNP transistors T2 and N
Using a PN type transistor T3, among these, the emitter of the transistor T2 is connected to the system power supply vCC,
Further, the base is connected to the collector of the transistor T3 via a resistor R4. The base of the transistor T3 is connected to the collector of the transistor T1 via a resistor R5.

Further, the emitter of the transistor T3 is grounded.

BT is, for example, a rechargeable backup battery, and this battery BT has a diode D connected in the forward direction.
It is connected to the collector of the transistor T2 via.

A resistor R6 is connected in parallel to the diode D. The collector side output of the transistor T2 becomes the supply output of the power supply switching circuit 12, Vcc2.

This power-off detection circuit 11. The power supply switching circuit 12 operates as follows.

That is, the power failure detection circuit 11 detects a voltage drop in the system power supply Vcc and outputs a voltage failure detection signal, and supplies the system power supply Vcc to the Zener diode ZD to detect the voltage drop. Now, when the system voltage Vcc is normal, this system voltage Vcc is higher than the sum of the Zener voltage Vz and the base-emitter ON voltage of T1, and the voltage at the voltage dividing point of resistor R1 and resistor R2 is higher than the sum of the Zener voltage Vz and the base-emitter on voltage of T1. Enough to turn it on. Therefore, the transistor T1, which receives the voltage at the voltage dividing point of the resistor R1° and the resistor R2 as a base voltage, is turned on, and the collector voltage of the transistor T1 becomes "H". This collector voltage rHJ is NP
The signal is input to the base of the NI transistor T3, and in response to this, the NPNI transistor T3 is turned on. Therefore, N.P.
The PNPI transistor T2, which receives the collector voltage of N1 to transistor T3 as its base input, turns on.
The system voltage Vcc is output from the power supply switching circuit 12 through this PNP transistor T2, and the supply output VCC
It becomes 2.

On the other hand, if the voltage of the system power supply VCC drops due to a power failure such as a power outage, and the voltage of the system power supply VCC becomes lower than the sum of the Zener voltage Vz and the base-emitter ON voltage of T1, the voltage of the resistor R1゜resistance R2 The voltage at the voltage point is insufficient to turn on the transistor T1. Therefore, transistor T1, which receives the voltage at the voltage dividing point of resistor R1 and resistor R2 as a base voltage, is turned off at this point, and the collector voltage of transistor T1, that is, power supply interruption @
SC becomes rLJ. This power-off signal SC rLJ is input to the base of the NPNt transistor T3, and in response to this, the NPNI transistor T3 is turned off. Therefore,
The PNP transistor T2, which receives the collector voltage of the NPNI transistor T3 as its base input, is turned off, the system power supply Vcc is cut off by this PNP transistor T2, and the output of the battery BT is instead switched to the power supply via the diode D. It is output from the circuit 12 and becomes the supply output VCC2.

In this way, the level of the system power supply Vcc can be detected, and in the event of an abnormality, it is possible to switch from the system power supply VCC to the battery BT.

Note that the resistor R6 forms a charging circuit for the battery BT when the transistor 2 is turned on.

Next, the operation of this device will be explained.

In the normal state, the system power supply Vcc is at a normal level, so the power-off detection circuit 11 does not output the power-off signal Sc.
Therefore, the power supply switching circuit 12 supplies the system power supply Vcc to the memory section 1, the oscillation circuit 7, the counter 8, and the selector 10 as the supply power VCC2. Therefore, these can be operated by this power supply VCC2. Also, at this time,
Since there is no power-off signal Sc from the power-off detection circuit 11,
Selector 10 is a control line and address bus 5
Select this control line and address bus 5
Address information and control signals given through the CPU are given to the memory section 1, and the memory section 1 is
access.

When the system power supply Vcc is cut off, the power cutoff detection circuit 11
detects this and outputs a power-off signal Sc. Therefore,
The power supply switching circuit 12 uses the output of the battery BT as the power supply VCC2 instead of the system power supply Vcc, and supplies the memory unit 1,
It is applied to the oscillation circuit 7, counter 8, and selector 10. Therefore, these are the power supplies VCC2 supplied by this battery BT.
It becomes possible to operate. Also, at this time, upon receiving the power-off signal SC from the power-off detection circuit 11, the selector 10 selects the output signal bus 9 of the counter 8, and outputs the output signal of the counter 8 given via this output signal bus 9. It is applied to the memory section 1 as address information and a control signal to refresh the memory section 1.

That is, in order to maintain memory in a dynamic RAM, memory cells must be accessed and refreshed at regular intervals. This refresh method uses RAS only.
Refresh, automatic refresh, CAS
There are various types such as before RAS refresh, self-refresh, etc., but automatic refresh can be performed automatically by simply keeping the automatic refresh terminal at rLJ. If the device does not have it, it cannot be implemented, and the same applies to self-refresh.

Also, CAS before/R'AS refresh is CAS
Since the refresh address is generated internally, there is no need for a refresh address counter. However, if the memory element does not have that function, it cannot be used.

RAS-only refresh is the most basic refresh method and uses dynamic RAM CAS (Column
Address 5select) terminal is inactive, and RAS (RowAddress
5select) terminal is activated and controlled by this RAS terminal, and by inputting an address from the outside.

This device adopts this RAS-only refresh method so that it can be applied to any kind of dynamic RAM.

FIG. 3 shows the correspondence between counter and memory signals.

In this device, 64-DRA is used as dynamic RAM.
I'm using M. If the RAM is 64 bit elements,
To perform RAS-only refresh, RAS (R), which is a negative logic active signal input terminal, is used to take in row address information.

RAS given to W Address 5select)
A negative logic active CAS (Column Addr) that controls signals, sequentially switches addresses, and adjusts the timing for capturing column address information.
r
Just keep it at HJ. Note that at this time, the write enable signal (Write), which is an input/output signal, may be in any state.

Therefore, counter 8 is "1"! 118 from line
Among the terminals up to the II digit, "II 8" from the 2nd pa digit
Output terminal Q2 up to jj digit. ~Q8 are respectively input to the address input terminals An and ~△6 of the RAM, and the output terminal Q1 of the "1" digit is inputted to the RAS terminal, which is a signal input terminal for taking in row address information, and other controllers are input. 1~roll line (CAS which is a signal input terminal for taking in column address information and line 1~/enable terminal Write)
If CLK is kept at the level HJ, the counter 8 that receives the oscillation output CLK from the oscillation circuit 7 and counts it will be refreshed to generate outputs as shown in FIG. The content of is protected.

In other words, since RAS is the output of Ql, it changes at the clock rate of CLK, and for addresses, it is the output of C2, ~Q8, so the output of 1/2° to 1/128 of CLK is appropriate. Therefore, each time RAS or CAS becomes active, the address is updated and RAS-only refresh can be performed.

Of course, it is necessary to select the oscillation frequency of the oscillation circuit 7 to a refresh period necessary for the dynamic RAM forming the memory section 1.

In this way, in the event of a power outage, the power source is switched to the battery, and the output of this battery is used as an address by the memory section and counter.
This is applied to the control signal generation section to generate address and control signals, and this is applied to the memory section to perform RAS-only refresh, so no matter what kind of dynamic RAM the memory uses, power outages will not occur. From time to time, you will be able to back up the contents.

In particular, when the main power supply goes out, the book@stomach switches the power source to the battery, uses this as the power source to operate the refresh counter, and automatically refreshes the contents of the dynamic RAM for a few seconds to several tens of seconds. Ideal for protecting memory contents for a short period of time. That is, because a battery with a small power supply capacity is normally used due to mounting considerations, this method can only provide backup for a few seconds to several tens of seconds in a large-capacity memory device. Of course, if a battery with a large power capacity is used, backup for several minutes to several hours or more is possible, but there are also problems in cost and implementation, so from the practical point of view of the present invention, it is difficult to use a relatively small battery. A large capacity memory device can be powered up for a few seconds using a battery.
It has a remarkable effect when backing up against FI4 failure.

Note that in the above explanation, the output of the power switching circuit is always given to the counter and oscillation circuit, so that they are driven at all times, but the output of the power switching circuit (battery power ) to drive these counters and oscillator circuits.

Furthermore, the dynamic RAM used is not limited to 64) (dots), but can also be applied to various capacities such as 16 bits, 256 bits, etc.

[Effects of the Invention] As detailed above, according to the present invention, when a power outage occurs,
Since the dynamic RAM can be automatically refreshed and its stored contents retained, it is now possible to completely protect the stored contents of the main memory, which is made up of inexpensive, large-capacity dynamic RAM, and can be used without interruption after a power outage is restored. It is possible to provide a dynamic RAM backup device that has features such as being able to restart processing from a certain point.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing an embodiment of the present invention, FIG. 2 is a circuit diagram showing the configuration of a power-off detection circuit and a power switching circuit, and FIG. It is a diagram showing correspondence. DESCRIPTION OF SYMBOLS 1...Memory part, 2...Data bus, 3...Address bus, 4...Control line, 5...Control line and address bus, 6...Power failure detection signal line, 7...・Oscillation circuit, 8...Counter, 9・
... Output signal bus, 10... Selector, 11... Power failure detection circuit, 12... Power supply switching circuit, Vcc...
・System power supply, Sc... Power off signal. Applicant's agent Patent attorney Takehiko Suzue Figure 1

Claims (1)

[Claims] As a backup device for a device using a dynamic RAM as a memory element, there is a means for detecting a power supply abnormality by detecting the level of the system power supply, and a means for detecting a power supply abnormality by switching to an emergency power supply using a battery to supply the memory element when a power supply abnormality is detected. means for operating from the emergency power supply to generate an address signal for dynamic RAM refresh and a command signal for reading the row address signal when a power supply abnormality is detected; , means for applying to the memory element the address signal and the command signal for reading the row address signal generated by the command signal generation means for reading the address signal and the row address signal, and means for applying an inactive column address read signal to the memory element. A dynamic RAM backup device characterized by comprising: