JPS61123091A - Semiconductor memory device - Google Patents

Abstract

PURPOSE:To dynamically control the gate voltage of FET and to speed up the raise up time of a bit line and to improve action speed, by connecting the gate of FET consisting of the pull up circuit with the source by the circuit element which functions as a capacitor. CONSTITUTION:The memory circuit has the pull up circuit 1, a memory cell 2, a sense amplifier 3 and a write buffer 4, and connects two diodes connected serially with an opposite polarity which function as a capacitor between the gate source and a depletion mode FET which consists of pull up circuit 1. In write action, the step down of the gate potential is slightly delayed against the step down of the source voltage, and the small volume of charge is stored at the diode. When bit line begines to rise to high level, the voltage higher than the source by the volume of charge at the capacitor is impressed to the gate of FET of pull up circuit, resulting in the increase of pull up current, and the rise of the bit line potential is prompted.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a semiconductor memory device constituted by a field effect transistor (hereinafter referred to as FET) having a Schottky barrier gate, such as a GaAs field effect transistor. This is particularly relevant to pull-up circuits that raise the potential of bit lines and the like to a high level.

[Conventional technology]

A circuit provided to raise the potential of a bit line, etc. to a high level in order to improve the operating speed of a memory circuit is called a pull-up circuit, and its function is to draw a low current when transitioning from a high level to a low level. It is desirable that a high current flow when transitioning from a low level to a high level. However, the demand for such advanced functions complicates the circuitry and impedes the improvement of the degree of integration. In a memory circuit using GaAs FIF, T, for example, F in depletion mode as shown in FIG.
A simple circuit connecting the gate and source of the ET is used. Other memory circuit components connected to this are:
This is the same as in FIG. 1, which will be described later, and is omitted in this figure.

[Problem that the invention seeks to solve]

A pull-up circuit like the one shown in Figure 2 consists of FE
The gate and source of T are directly connected, forming a type of constant current circuit, so the current value can be changed depending on the situation, such as from a high level to a low level, or from a low level to a high level. I can't. The present invention aims to dynamically control the gate voltage of this FET to obtain a pull-up circuit that performs more preferable operation.

[Means for solving problems]

To achieve this objective, in the present invention, the gate and source of the FET constituting the pull-up circuit are connected by a circuit element that functions as a capacitor.

[Action of the invention]

As a result, when the bit line transitions from a low level to a high level, a state where the gate potential is temporarily higher than the source potential appears, and the pull-up current increases.

[Embodiments of the invention]

FIG. 1 shows one embodiment of the present invention. The difference from the prior art shown in FIG. 2 is that two diodes connected in series with opposite polarities are connected between the gate and source of the depletion mode FET constituting the pull-up circuit 1. Since this portion functions as a capacitor, it may be an ordinary parallel plate capacitor, but when actually formed in an integrated circuit, a diode, which occupies a smaller area, is more advantageous.

In addition to the pull-up circuit, the memory circuit includes memory cell 2.
, a sense amplifier 3, a write buffer 4, etc., but these parts are the same as known ones.

The operation of the pull-up circuit of the present invention will be described below, but the operation of this circuit should be understood as dynamic rather than static.

In a read operation, a pair of bit lines to which a plurality of memory cells are connected are held at a high level when not selected, and one of them is pulled down to a low level when selected. At this time, the pull-up circuit of the present invention also operates as a constant current circuit like a normal pull-up circuit.

Normally, a read operation is completed in a relatively short time, and the bit line, which has dropped to a low level, is pulled back to a high level. In this series of operations, when the source potential first drops to a low level, the gate potential also drops as the source potential drops, but there is a slight delay in this operation, and a small amount of charge is stored in the diode, which is a capacitor. If the bit line starts to rise to a high level before this charge is completely discharged, a voltage higher than the source potential by the amount of charge on this capacitor is applied to the gate of the FET in the pull-up circuit, and the pull-up current increases, making the bit cotton potential rise quickly.

How many volts the gate potential will actually increase depends on many factors such as bit line capacitance and pull-up current value, so it is difficult to say generally and it is difficult to actually measure it, but we assume average specifications. According to the simulation, Vdd is 0.8
In the case of V, a potential increase of about 0.15 V occurs, and the gate voltage becomes about 0.95 V.

The present invention performs the above operation dynamically, but statically the gate and source are coupled by a diode leak resistance, and is equivalent to a normal pull-up circuit.

In the above embodiment, two diodes connected with opposite polarities are used as the capacitor, but the same effect can be obtained whether these diodes are of the P-N junction type or the Schottky barrier type. It will be done. The connection direction may also be different from that shown in the figure, even if the anodes are connected to each other. In order to obtain the same effect with a single diode, it is required to use a diode that has a large forward rising voltage and a sufficiently small leakage current. In this case, the cathode will be connected to the gate.

Furthermore, although the above example shows a circuit using a normal GaAsFET, it is also possible to construct a similar circuit using a recently developed high electron mobility transistor (HEMT) and achieve the same effect. be.

〔Effect of the invention〕

Since the pull-up circuit of the present invention increases the rise speed of the bit line, it is possible to improve the operating speed of the memory circuit by using the pull-up circuit.

[Brief explanation of drawings]

FIG. 1 is a diagram showing the present invention, and FIG. 2 is a diagram showing the prior art. In the figure, 1 is a pull-up circuit, 2 is a memory cell, 3 is a sense amplifier, and 4 is a write buffer. Sheep 1 Figure rod 2 Figure V〃V ] 1ξQQ-

Claims (2)

[Claims] (1) Schottky barrier in depletion mode
1. A semiconductor memory device comprising, as a pull-up circuit, a structure in which the gate and drain of a gate field effect transistor are connected by a circuit element that effectively functions as a capacitor. (2) The circuit element that effectively functions as a capacitor is two diodes connected in series with opposite polarity,
2. The semiconductor memory device according to claim 1, wherein said pull-up circuit is connected to a bit line.