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JPS61110435A - Surface grinding method for semiconductor wafer - Google Patents

Surface grinding method for semiconductor wafer

Info

Publication number
JPS61110435A
JPS61110435A JP59230089A JP23008984A JPS61110435A JP S61110435 A JPS61110435 A JP S61110435A JP 59230089 A JP59230089 A JP 59230089A JP 23008984 A JP23008984 A JP 23008984A JP S61110435 A JPS61110435 A JP S61110435A
Authority
JP
Japan
Prior art keywords
wafer
semiconductor wafer
grinding
protective film
ground
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP59230089A
Other languages
Japanese (ja)
Inventor
Yukio Yamada
幸雄 山田
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Oki Electric Industry Co Ltd
Miyazaki Oki Electric Co Ltd
Original Assignee
Oki Electric Industry Co Ltd
Miyazaki Oki Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Oki Electric Industry Co Ltd, Miyazaki Oki Electric Co Ltd filed Critical Oki Electric Industry Co Ltd
Priority to JP59230089A priority Critical patent/JPS61110435A/en
Publication of JPS61110435A publication Critical patent/JPS61110435A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/304Mechanical treatment, e.g. grinding, polishing, cutting
    • H01L21/3046Mechanical treatment, e.g. grinding, polishing, cutting using blasting, e.g. sand-blasting

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Finish Polishing, Edge Sharpening, And Grinding By Specific Grinding Devices (AREA)
  • Mechanical Treatment Of Semiconductor (AREA)

Abstract

PURPOSE:To prevent damage on the wafer surface by grain from generated during the grinding by executing the grinding after the surface protection film is deposited in such a way as the mound is formed at the periphery, covering the entire part of surface facing to the surface of wafer to be ground. CONSTITUTION:A wafer 10 is mounted on the spinner apparatus and resist is dropped as a protection film 11. When the wafer 10 on which resist is dropped is rotated, mound portion 12 is generated at the periphery of wafer 10. This wafer 10 is dried and it is placed on the spinner again. Resist is dropped and the wafer is rotated again. The mound portion 12 further grows at the periphery of wafer 10 when it is rotated. The wafer 10 having the mound portion in sufficient height is absorbed by a vacuum absorption table 13, a grind stone 14 located at the upper part of table 13 is rotated, and the grinding surface of the wafer 10 is ground to the predetermined thickness.

Description

【発明の詳細な説明】 (産業上の利用分野) この発明は半導体ウェハの平面を研削する方法に関し、
詳しくは、半導体ウェハの素子形成面或はその裏面を砥
石の様な機械的研削手段によって研削する方法に関する
ものである・ (従来の技術) 半導体ウェハの平面研削は、誘電体分離構造の半導体集
積回路装置の製造に用いられ、例えば特公昭46−27
417号、特公昭51−20267号、特公昭53−1
4476号などに示されるように単結晶半導体ウェハの
一主平面に複数の溝又は孔を形成し、この形成面に誘電
体膜を被着形成し、更に多結晶半導体層を成長させて基
板支持体を作る。その後対向する主平面を前記溝又は孔
の底部に達する位置まで前記単結晶半導体ウェハを研削
し、誘電体分離基板を構成する。
[Detailed Description of the Invention] (Industrial Application Field) The present invention relates to a method for grinding a flat surface of a semiconductor wafer.
More specifically, it relates to a method of grinding the element forming surface of a semiconductor wafer or its back surface using a mechanical grinding means such as a grindstone. Used in the manufacture of circuit devices, for example,
417, Special Publication No. 51-20267, Special Publication No. 53-1
4476, a plurality of grooves or holes are formed in one principal plane of a single crystal semiconductor wafer, a dielectric film is deposited on this formed surface, and a polycrystalline semiconductor layer is further grown to support the substrate. Build a body. Thereafter, the single crystal semiconductor wafer is ground until the opposing main planes reach the bottoms of the grooves or holes, thereby forming a dielectric isolation substrate.

又、半導体ウェハーの裏面に機械的損傷を与えることに
よシ塑性歪層(ダメージ層)を形成し、ウニ・・−中の
重金属による結晶欠陥を除去する、いわゆるr、タリン
グと呼ばれる手法は、例えばrsamiconduct
or World l 983.7の33イージ〜37
ページに亘って記載されている様に、ウニ・・−裏面を
砥石或は砥粒によるう、ピングなどが行われる。
In addition, there is a method called r, taring, in which a plastic strain layer (damage layer) is formed by mechanically damaging the back surface of a semiconductor wafer, and crystal defects caused by heavy metals in sea urchins are removed. For example, rsamiconduct
or World l 983.7's 33 easy ~ 37
As described throughout the page, the back side of the sea urchin is polished with a grindstone or abrasive grains, etc.

この様に半導体ウエノ・の表面を砥石或は砥粒によって
研削する際は、被研削面と対向する面を清浄て保つべく
、レジストなどくよる保護膜をコーティングするが、研
削時の砥粒が保護膜中奥深く入り込みウエノ・表面を傷
つけるという問題にしばしば遭遇する。この損傷モード
を第2図及び第3図を用いて説示する。第2図(1)〜
(e)は、この種研削作業の準備工程を含む工程断面図
であり第3図d1グラインダーの模式図で、(1)は平
面図(b)は断面図である。
When grinding the surface of a semiconductor wafer using a whetstone or abrasive grains, a protective film such as a resist is coated to keep the surface facing the surface to be ground clean, but the abrasive grains during grinding are coated with a protective film such as resist. We often encounter the problem of penetrating deep into the protective film and damaging the surface of the film. This damage mode will be explained using FIGS. 2 and 3. Figure 2 (1) ~
(e) is a process cross-sectional view including the preparation process for this type of grinding work, and is a schematic diagram of the FIG. 3 d1 grinder, and (1) is a plan view, and (b) is a cross-sectional view.

まず研削作業に当って、第2図(&)で示すように半導
体ウェハー1の被研削面と対向する面に保護膜2として
例えばレノストを摘下し、図示しない回転装置によりこ
のウェハー1を4000 rpm程度の速度で15 s
ec程回転させ3μm厚の保護膜2を均一にコーティン
グする。そして乾燥後、真空吸着テーブルJK、保護膜
2で表面が覆われたウニ・・−1を第2図(b)に示す
ように吸着させ、更に@2図(ellc示すように砥石
4を回転させると共に図示しない散水装置によ〕水を供
給しながらウニ・・−1を所定の厚さに研削する。
First, during the grinding operation, as shown in FIG. 15 s at a speed of about rpm
Rotate by ec to uniformly coat the protective film 2 with a thickness of 3 μm. After drying, the vacuum suction table JK adsorbs the sea urchin... The sea urchin...-1 is ground to a predetermined thickness while supplying water with a water sprinkler (not shown).

(発明が解決しようとする問題点) しかし、この研削時に砥石4により削られた7917片
或は砥粒(これらを一括して符号5として表す)5が、
テーブル3の周縁部から入り込み保護膜2を破り、ウエ
ノ・−1の表面を損傷させる。
(Problems to be Solved by the Invention) However, the 7917 pieces or abrasive grains (these are collectively represented as 5) 5 cut by the grindstone 4 during this grinding are
It enters from the peripheral edge of the table 3, breaks the protective film 2, and damages the surface of Ueno-1.

これは第3図(B)及び(b)で示すグラインダーの真
空吸着力が弱いためである。即ち、この種研削は水の供
給を伴うため吸着力の高い真空Iングが使用できず、管
5に太線矢印で示す方向にエアーを供給した際に生ずる
吸引現象、即ち管6内に細線矢印で示す方向にエアーが
流れることによυ生ずる吸引力によりウニ・・−1を吸
着させる為、周縁部が中央部に比べ弱いことに起因する
This is because the vacuum suction force of the grinder shown in FIGS. 3(B) and 3(b) is weak. That is, since this type of grinding involves the supply of water, a vacuum I ring with a high suction force cannot be used, and the suction phenomenon that occurs when air is supplied to the tube 5 in the direction shown by the thick line arrow, that is, the thin line arrow inside the tube 6. This is due to the fact that the periphery is weaker than the center because the suction force generated by air flowing in the direction shown by υ attracts the sea urchin...-1.

従って本発明は、ペンチェリポングなどの比較的弱い吸
引力によって保持した半導体ウニ・・−の研削に際して
も、保護膜で覆われたウエノ・表面が損傷しない研削方
法を提供するものであるO(間層を解決するだめの手段
) この発明°は半導体ウエノ・の平面を砥石のような機械
的研削手段によって所定量研削するに際し、前記ウエノ
・の被研削平面と対向する面全面罠装置する表面保護膜
を、前記ウエノ・の周縁部が盛り上がるように施す、い
わゆるバンク(土手)状の表面保護膜を形成して研削を
行うことKある。
Therefore, the present invention provides a grinding method that does not damage the surface of a semiconductor sea urchin covered with a protective film even when the semiconductor sea urchin is held by a relatively weak suction force such as a pencheripong. (Means for Solving Interlayer Problems) This invention provides a surface trapping device for the entire surface of the semiconductor wafer, which is opposite to the plane to be ground, when the plane of the semiconductor wafer is ground by a predetermined amount using a mechanical grinding means such as a grindstone. Grinding is sometimes performed by forming a so-called bank-shaped surface protective film, which is applied so that the peripheral edge of the wafer is raised.

(作用) この発明方法の特徴的な作用は、前記半導体ウニ八周縁
部に設けたバンク状の表面保護膜の存在により、研削時
に発生する研削屑を、この保護膜形成面と密着するテー
ブルとの間に進入させないようにして研削を行うことに
ある。
(Function) A characteristic effect of the method of the present invention is that due to the presence of the bank-shaped surface protective film provided on the peripheral edge of the semiconductor urchin, grinding debris generated during grinding is removed by the table that is in close contact with the surface on which the protective film is formed. The purpose is to perform grinding while preventing the particles from entering between the holes.

(実施例) 第1図(為)及び(C)はこの発明方法の好ましい一実
施例図であシ、まず(&)に示すように半導体ウエノ・
JOを図示しないスピナー装置(回転塗布装置)に搭載
し、保護膜1ノとして例えば粘度t o o cp程度
のレノストを摘下する。レノストが摘下された半導体ウ
ェハ10を、例えば3000 rpm程度の速度で5s
ec回転させると、ウエノ・10の周縁部に1ないし2
μmの盛り上がり部分12が生じる。
(Example) Figures 1 (for) and (C) are diagrams of a preferred embodiment of the method of this invention. First, as shown in (&),
The JO is mounted on a spinner device (rotational coating device), not shown, and renost having a viscosity of about t o cp, for example, is removed as the protective film 1 . The semiconductor wafer 10 with Lennost removed is heated for 5 seconds at a speed of about 3000 rpm, for example.
When you rotate ec, 1 or 2 will appear on the periphery of Ueno 10.
A raised portion 12 of μm is generated.

そしてこのウェハ10を120℃で5分乾燥させ再度ウ
ェハ10を図示しないスピナー装置に搭載し、上述した
と同様のレジストを摘下し、やはシ3000 rpm程
度の速度で5 sec程度回転させると(b)に示すよ
うにウニ・・100周縁部の盛り上が9部分12が更に
隆起する。この隆起部分12の高さは3μm4Qれば充
分である。又この時の保護膜1ノの盛り上がシ部分12
以外の厚さは5ないし10μmである。そして充分な高
さになった盛り上がり部12をもつウェハ10を(cl
 K示すように真空吸着テーブル13に吸着させ、テー
ブルノコ上部に配置された砥石J4を回転させ、ウエハ
ノ0の被研削面を所定の厚さ研削する。この研削時に砥
石14によシ削られたシリコン片或は砥粒(これらを一
括して符号15として示す)15は、盛り上がシ部12
によってガードされる。このガード力は相当強力である
。それはウニ・・10の鴫縁部に形成された盛り上がシ
部12によって生じた真空吸着テーブルノ3とのすきt
15が陽圧となり、この盛)上がシ部12でのみ真空吸
着デープル13と密着するからである。
Then, this wafer 10 was dried at 120° C. for 5 minutes, and the wafer 10 was again mounted on a spinner device (not shown), the same resist as described above was removed, and the spinner was rotated for about 5 seconds at a speed of about 3000 rpm. As shown in (b), the raised portion 9 12 of the periphery of the sea urchin 100 is further raised. It is sufficient for the height of this raised portion 12 to be 3 μm4Q. Also, at this time, the raised part 12 of the protective film 1
The thickness other than that is 5 to 10 μm. Then, the wafer 10 having the raised portion 12 with a sufficient height is placed (cl
As shown in K, the wafer 0 is suctioned to the vacuum suction table 13, and the grindstone J4 placed on the top of the table saw is rotated to grind the surface of the wafer 0 to be ground to a predetermined thickness. During this grinding, the silicon pieces or abrasive grains (these are collectively designated as 15) 15 ground by the grinding wheel 14 are attached to the raised portion 12.
guarded by. This guard power is quite strong. That is the gap t between the vacuum suction table 3 and the sea urchin... created by the raised part 12 formed on the edge of the sea urchin 10.
15 becomes a positive pressure, and the upper part of this bulge comes into close contact with the vacuum suction daple 13 only at the bottom part 12.

(発明の効果) 以上説明した様にこの発明方法に従えば、真空吸着テー
ブルに吸着されるウェハは、このウニ・・の周縁部に形
成された盛り上がり部(バンク状の土手)のみで吸着さ
れる為、比較的吸着力の弱いペンチエリIンデ方式の吸
着装置を採用しても高い吸着力を呈すので、研削時に発
生する砥粒などKよるウェハ表面の損傷を保護し得る。
(Effects of the Invention) As explained above, if the method of the invention is followed, the wafers that are attracted to the vacuum suction table are attracted only by the bulges (bank-like banks) formed at the periphery of the urchin. Therefore, even if a pentier-in-det type suction device, which has a relatively weak suction force, is used, the wafer surface can be protected from damage caused by K such as abrasive particles generated during grinding.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図(&〕〜(C)は本発明の好ましい実施例方法の
工程断面図であシ、第2図(&)〜(c)は従来方法の
工程断面図、第3図(al t (b)はこの種方法に
用いられるグラインダの模式図であシ、(〜は平面図を
(b)は断面図を示す。 10・・・半導体ウェハ、1ノ・・・保護膜、J2・・
・盛り上がシ部、13・・・真空吸着テーブル、14・
・・砥石、15・・・シリコン片及び砥粒、ノロ・・・
すき間。 特許出願人 沖電気工業株式会社 宮崎沖電気株式会社 第1図 昭和  年  月  日
FIGS. 1(&) to (C) are process sectional views of a preferred embodiment method of the present invention, FIGS. 2(&) to (c) are process sectional views of a conventional method, and FIG. (b) is a schematic diagram of a grinder used in this type of method (~ shows a plan view, and (b) shows a cross-sectional view. 10... Semiconductor wafer, 1... Protective film, J2...・
- Raised portion, 13... Vacuum suction table, 14.
...Whetstone, 15...Silicon pieces and abrasive grains, slag...
Gap. Patent applicant Oki Electric Industry Co., Ltd. Miyazaki Oki Electric Co., Ltd. Figure 1 Showa Year Month Day

Claims (3)

【特許請求の範囲】[Claims] (1)半導体ウェハの被研削平面と対向する平面に表面
保護膜をコーティングし、この保護膜コーティング面を
平坦な真空吸着テーブル上に載置した後、前記被研削平
面を機械的研削手段によって所定量研削する方法に於て
、前記表面保護膜は、前記半導体ウェハの周縁部が盛り
上がる様に施した後、前記真空吸着テーブル上に載置し
て行う事を特徴とする半導体ウェハの平面研削法。
(1) After coating the surface of the semiconductor wafer opposite to the surface to be ground with a surface protective film, and placing the surface coated with the protective film on a flat vacuum suction table, the surface to be ground is placed in place by mechanical grinding means. In the quantitative grinding method, the surface protection film is applied so that the peripheral edge of the semiconductor wafer is raised, and then the semiconductor wafer is placed on the vacuum suction table. .
(2)前記半導体ウェハの周縁部を盛り上げる表面保護
膜のコーティングは、半導体ウェハ上に高粘度の表面保
護膜材を滴下し、このウェハを低速回転させることによ
り行うことを特徴とする特許請求の範囲第1項記載の半
導体ウェハの平面研削法。
(2) The coating of the surface protective film that bulges the peripheral edge of the semiconductor wafer is performed by dropping a highly viscous surface protective film material onto the semiconductor wafer and rotating the wafer at a low speed. A method for surface grinding a semiconductor wafer according to scope 1.
(3)前記表面保護膜はフォト・レジストである事を特
徴とする特許請求の範囲第1項記載の半導体ウェハの平
面研削法。
(3) The method for surface grinding a semiconductor wafer according to claim 1, wherein the surface protective film is a photoresist.
JP59230089A 1984-11-02 1984-11-02 Surface grinding method for semiconductor wafer Pending JPS61110435A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP59230089A JPS61110435A (en) 1984-11-02 1984-11-02 Surface grinding method for semiconductor wafer

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP59230089A JPS61110435A (en) 1984-11-02 1984-11-02 Surface grinding method for semiconductor wafer

Publications (1)

Publication Number Publication Date
JPS61110435A true JPS61110435A (en) 1986-05-28

Family

ID=16902373

Family Applications (1)

Application Number Title Priority Date Filing Date
JP59230089A Pending JPS61110435A (en) 1984-11-02 1984-11-02 Surface grinding method for semiconductor wafer

Country Status (1)

Country Link
JP (1) JPS61110435A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2001096065A1 (en) * 2000-06-13 2001-12-20 Shin-Etsu Handotai Co., Ltd. Method for polishing work
WO2014188879A1 (en) * 2013-05-24 2014-11-27 富士電機株式会社 Method for manufacturing semiconductor device

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2001096065A1 (en) * 2000-06-13 2001-12-20 Shin-Etsu Handotai Co., Ltd. Method for polishing work
WO2014188879A1 (en) * 2013-05-24 2014-11-27 富士電機株式会社 Method for manufacturing semiconductor device
CN105190844A (en) * 2013-05-24 2015-12-23 富士电机株式会社 Method for manufacturing semiconductor device
JP6004100B2 (en) * 2013-05-24 2016-10-05 富士電機株式会社 Manufacturing method of semiconductor device
JPWO2014188879A1 (en) * 2013-05-24 2017-02-23 富士電機株式会社 Manufacturing method of semiconductor device
US9972521B2 (en) 2013-05-24 2018-05-15 Fuji Electric Co., Ltd. Method for manufacturing semiconductor device to facilitate peeling of a supporting substrate bonded to a semiconductor wafer

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