JPS6095370A - Integrated circuit device - Google Patents

Abstract

PURPOSE:To obtain an integrated circuit device capable of having multi-function over an inspection, etc. without increasing the number of terminals by making the device have plural operating functions while using common input and output. CONSTITUTION:Inputs I3, I4 and inputs I5, I6 are not used simultaneously. Also, outputs O3, O4 and O5, O6 are also the same as above. In this case, the outputs O3, O4 are used together with the inputs I3, I4, and the outputs O5, O6 are used together with the inputs I5, I6. The first chip enable signal C supplied by a terminal 1C is inputted to one input of an AND gate A1 and A2, and the second chip enable signal obtained through an invertor 11 from the terminal 1C is supplied to one input of an AND gate A3 and A4. The first mode activates a circuit by inputs I1-I4 and outputs O1-O4 in accordance with the first chip enable signal C, and the second mode activates a circuit operated by the inputs I1, I2, I5 and I6 and the outputs O1, O2, O5 and O6 in accordance with the second enable signal. The input which is not required in each mode is inhibited to ''0'' by the AND gate.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an integrated circuit device, and particularly to a digital logic circuit suitable for monolithic integration.

With the shift to LSI digital logic integrated circuits, the number of internal nodes has increased dramatically, and testing methods for the entire LSI have become extremely complex, especially when these nodes include storage elements (state flip processor 1, etc.). As is well known.

An effective method for this purpose is to arrange the 70 clips at important points in the logic circuit and divide them into several groups, so that each group of 7 lip-flops can be used independently in the test operation mode, which is different from the normal operation mode. By operating it as a shift register and outputting the four inputs, data, output, etc. to the outside, any 70 rip 70 can be input at any time.
There is a known method for simplifying testing by converting general sequential logic into combinatorial logic using a method of reading and rewriting the state of a TUG (so-called scan path method). Although this method is certainly extremely effective because it simplifies the LSI testing method, its drawback is that the number of testers and output terminals increases significantly. This means that large-scale logic circuits
It was not noticeable when the integrated circuit was constructed using the conventional method of using a printed circuit board with a large number of connector terminals as the basic unit, but as the degree of integration of integrated circuits increased. As a result, the current situation is that there is no margin for the number of terminals, which is extremely disadvantageous.

SUMMARY OF THE INVENTION An object of the present invention is to provide an integrated circuit device that can be multifunctional, such as testing, without increasing the number of terminals.

Another object of the present invention is to provide a digital integrated circuit in which a logic section is operated using a common input/output terminal so as to have a circuit having a plurality of operating functions.

The integrated circuit device according to the present invention, particularly the hemi-nolithic integrated circuit, is an integrated circuit having a plurality of input terminals and output terminals, in which at least one control terminal is provided, and the input terminal, The present invention is characterized in that the functions of at least some of the output terminals are set, and input/output conditions for circuits with different operating functions are defined.

In the present invention, physically, even if there are n input (output) terminals, if a separate function is assigned to each terminal according to the logical state of one tree of control terminals, for example, 1.0, We will focus on the fact that it functions as 2n terminals. Of course, consideration must be given to the allocation so that among the 2n functions, the first n functions and the latter n functions are not used at the same time. This μ theory can be easily extended to the case of m control inputs.

In addition, the present invention uses a so-called third value in a region other than the normal logic voltage range (for example, -0.5V to +a5V in TTL) (for example, by connecting an inverter input terminal that operates at a value of +8V to a normal TTL input terminal in parallel). ) Note that if this is used as a mode control input, the terminal efficiency can be further improved.

According to the present invention, the present invention has a plurality of input terminals, a plurality of output terminals, etc. - or a plurality of operating modes, and at least some of the input terminals and output terminals perform different functions in the different operating modes. A digital integrated circuit controlled by the mode control input terminals is obtained, and furthermore, at least some of the input (output) terminals physically double as control terminals, and in the normal logic voltage range, - Turn on the operation mode (
Functions as a 100% terminal, and in a certain voltage range (hereinafter referred to as the 3rd value) higher or lower than the normal logic voltage range, it inhibits the - operation mode and activates other operation modes at the same time. A digital integrated circuit can be obtained which functions as a control terminal. Furthermore, in such a digital integrated circuit, a (monolithic) digital integrated circuit is also obtained which includes, as a reduced operating mode, at least one test operating mode in addition to a normal operating mode, the latter of which can be used for logic debugging or fault diagnosis. .

A first embodiment of the present invention will be described with reference to FIG. The logic section 10 of the semiconductor integrated circuit has six inputs, ~I6.6
One output 0. ~0. It operates in response to a chip enable signal (mode control signal) C or D. Input I...
I and I are always necessary inputs, and are directly taken in from input terminals Ill and I□, respectively. It is necessary to always take out to output 011, and output terminal 011,
0. They are each taken out by t. Input 1. ,
I4 and inputs I,, I, are never used at the same time,
Only one set is used. to the output, 04 and 0. ,0. Also, only one set is used at the same time, where the output Os, 04 is the input I,,I. The outputs Os, Oa are used with the inputs 1. , shall be used with I6. input! , or engineering. are applied to the AND gates A and ^ respectively, and the first chip enable signal C applied at the terminal IC is input as is to the AND gates A and ^, and the input terminal I □ and 工□ are entered. A second chip enable signal obtained from the terminal IC via the inverter 11 is applied to the input terminals of the AND gates A and A, and input terminals I□ and I□ are respectively connected thereto. On the other hand, the outputs O1 and 0. are the first
The second enable signal C is connected to output terminals 0□ and Oo through AND gates A and A6 and OR gates and Rtt'', respectively. Similarly, outputs O1 and 0. Input AND gates A and Aa and OR gate R
, and R3 to output terminals O1 and O8. The logic unit 10 according to this embodiment has two circuits with different operating functions operating in different operating modes.

That is, the mode of tsl corresponds to the high level of the first enable signal C, inputs I, , I, peak J4 output 0110,
,O,,04IC, and the second mode 7 is for activating the circuit operating from the second enable signal C at the high level of the input I,,I,,I,,I. , output o,
,o,,o,,o,activates the circuit that operates. Unnecessary inputs in each of these modes are inhibited to 0 by an AND gate in this example. In this way, according to this embodiment, many functions can be achieved while keeping the number of terminals small.
This allows integrated circuits with input/output logic functions. It is easily considered that the number of input/output mode control inputs and the mode switching logic are not limited to those in this example.

Next, a second embodiment of the present invention will be described with reference to FIGS. 2 and 3.

The logic circuit 20 has the same configuration as shown in FIG.
+, 0* are output terminals 0. i, 01. - is connected to. Irikani, ~I6 are each AND gate A+-
Input terminal I! via Aa! I and I□, output 0. ~06 is connected to the output terminals O□, 0□ via the AND gate As~^, the OR gate RI, and the gate. All of the above-mentioned configurations are the same as in the first embodiment. In this embodiment, an inverter 21 connected to the input terminal Ill supplies a second enable signal C, and this enable signal C is inverted by an inverter 22 to provide a first enable signal C to the circuit 20 and each AND gate. . Here, the terminal wire □ is at the normal logic level (for example, T
In the case of TL logic, when the voltage is 0 to 5.5 V), the inverter 21 generates a high level output C as a low level input, and the terminal I□ is at the third logic level (for example, around IOV).
Sometimes this is used as a high-level logic input to inverter 2.
1 produces a low level output C. It is a theory that the enable signal C1 and the enable signal C as outputs can drive each AND gate in exactly the same way as in the first embodiment to realize the second operation mode.
There's no need to do it. However, in this embodiment, the input terminals I, .
When the K third level input is applied, that is, in the first operation mode, the input of the logic circuit 20! It must be taken into account that 3 is always given a high level. FIG. 3 shows a specific example of the inverter 21 for reference. This circuit includes transistors Q*, Q- and resistors R, , R, and if the resistance value ratio R1/R1 is set appropriately small, the transistor Q! is usually (DTTLlz
Bell (0/1)GV remains off at ~5.5V, but here a voltage (third level input voltage) that is sufficiently larger than the Zener withstand voltage of transistor Q1 is applied to the input terminal! When the voltage is applied to □, the transistor Q turns on, and thus the desired mode control output C is obtained.

As described above, the present invention appropriately utilizes the independent or third-level mode control manual EN to allow a plurality of input/output signal terminals to be shared depending on whether the input/output signals are used or not in each operation mode. By doing so, the number of terminals in a monolithic logic integrated circuit can be reduced over an extremely wide range and the number of terminals can be effectively utilized, so the effects of the present invention are enormous.

It should be noted that the present invention is not limited to the above-mentioned embodiments, but it goes without saying that it can be widely applied.

[Brief explanation of the drawing]

1 and 2 are the first and second embodiments of the present invention, respectively.
A block diagram showing the configuration of an integrated circuit according to an embodiment of
The figure is a circuit diagram showing a part of FIG. 2. 10.20...Logic department, person, ~ person,...
・And gate, 11□+ 111 # I goose 1 #
Ill...Input terminal SO, l, O□. 0□, 0□・・・Output terminal, 11, 21.22・
River...inverter. No.l 已茅 2I21 //z( /,!'/( 3rd I21

Claims (1)

[Claims] 1o In an integrated circuit device having at least 8 input terminals (N is an integer of 1 or more), a logic section including at least 2N input terminals, and an output terminal, i to connect the input terminals of the input terminals to the N input terminals of the 2N ports, respectively.
and second means for respectively connecting the eight input terminals to the remaining N of the 2N input terminals;
and a control terminal for inputting a signal for switching between the first means and the second means, and by switching between the first means and the second means using the signal, different operation modes can be achieved. An integrated circuit device characterized in that the integrated circuit device is configured to be set. 2. Some of the eight input terminals are allocated as the control terminals, and the switching signal has a voltage level different from the input data supplied to the logic section. An integrated circuit device according to claim 1. & A smaller number of output terminals than the output terminals of the logic section are provided, and the data output from the output terminals of the logic section is configured to be taken out to the outside by sharing the output terminals. An integrated circuit device according to claim 1.