JPS60954B2 - Polycrystalline silicon fuse memory and its manufacturing method - Google Patents
Polycrystalline silicon fuse memory and its manufacturing methodInfo
- Publication number
- JPS60954B2 JPS60954B2 JP55180003A JP18000380A JPS60954B2 JP S60954 B2 JPS60954 B2 JP S60954B2 JP 55180003 A JP55180003 A JP 55180003A JP 18000380 A JP18000380 A JP 18000380A JP S60954 B2 JPS60954 B2 JP S60954B2
- Authority
- JP
- Japan
- Prior art keywords
- fuse
- polycrystalline
- polycrystalline silicon
- film
- insulating film
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
- 230000015654 memory Effects 0.000 title claims description 28
- 229910021420 polycrystalline silicon Inorganic materials 0.000 title claims description 27
- 238000004519 manufacturing process Methods 0.000 title claims description 8
- 229910052751 metal Inorganic materials 0.000 claims description 17
- 239000002184 metal Substances 0.000 claims description 17
- 230000003647 oxidation Effects 0.000 claims description 12
- 238000007254 oxidation reaction Methods 0.000 claims description 12
- 238000000034 method Methods 0.000 claims description 10
- 238000005530 etching Methods 0.000 claims description 8
- 230000008018 melting Effects 0.000 claims description 8
- 238000002844 melting Methods 0.000 claims description 8
- 239000000758 substrate Substances 0.000 claims description 6
- 239000010408 film Substances 0.000 description 28
- 238000005520 cutting process Methods 0.000 description 7
- 239000000463 material Substances 0.000 description 3
- 230000001590 oxidative effect Effects 0.000 description 3
- 239000013078 crystal Substances 0.000 description 2
- 230000008021 deposition Effects 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 229910014299 N-Si Inorganic materials 0.000 description 1
- 238000005275 alloying Methods 0.000 description 1
- 238000006243 chemical reaction Methods 0.000 description 1
- 230000007423 decrease Effects 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 230000017525 heat dissipation Effects 0.000 description 1
- 239000012535 impurity Substances 0.000 description 1
- 150000002739 metals Chemical class 0.000 description 1
- 229910052750 molybdenum Inorganic materials 0.000 description 1
- 150000004767 nitrides Chemical class 0.000 description 1
- 229910021332 silicide Inorganic materials 0.000 description 1
- 229910052715 tantalum Inorganic materials 0.000 description 1
- 239000010409 thin film Substances 0.000 description 1
- 229910052721 tungsten Inorganic materials 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/525—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body with adaptable interconnections
- H01L23/5256—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body with adaptable interconnections comprising fuses, i.e. connections having their state changed from conductive to non-conductive
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
Landscapes
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Read Only Memory (AREA)
- Design And Manufacture Of Integrated Circuits (AREA)
- Semiconductor Memories (AREA)
Description
【発明の詳細な説明】
本発明は、低電圧・低電流で切断可能で、しかも信頼性
の高い多結晶シリコン・フューズ・メモ川こ関し、かつ
その容易な製造方法を提供するものである。DETAILED DESCRIPTION OF THE INVENTION The present invention provides a highly reliable polycrystalline silicon fuse memory that can be cut with low voltage and low current, and an easy manufacturing method thereof.
現在、ＩＣ中に形成されたフューズ・メモリは、低容量
のプログラマフル・ＲＯＭとして工程バラツキの吸収や
、徴調用として幅広く用いられている。Currently, fuse memories formed in ICs are widely used as low-capacity programmable ROMs for absorbing process variations and for tuning purposes.
フューズ材料としては、ＡＩ，ＡＩ−Ｓｉ、低融点金属
の薄膜や、多結晶シリコンが使われている。しかしなが
ら、これらを切断するためには数Ｖ以上、数皿ｈＡ以上
が必要であり、通常、ＩＣ外部駆動によって切断、すな
わち書きこまれる。書き込み回路をＩＣ内部に設ける場
合には、駆動トランジスタの耐圧、電流制限によって書
き込み、電圧１０Ｖ以下、電流１肌Ａ以下が望まれる。
特に多結晶シリコンによるフューズ・メモリは切断後の
信頼性が高いので、年々用途が広がっているが、特にＩ
Ｃ内部に書込み回路を設ける場合には、切断が容易でな
いため、フューズ・メモリ構造に特別の配慮が必要であ
る。第１図には、多結晶フューズ・メモリの従来例の平
面図（第１図ａ）、断面図（第１図ｂ）を示した。As fuse materials, AI, AI-Si, thin films of low melting point metals, and polycrystalline silicon are used. However, in order to cut these, several V or more and several plates hA or more are required, and the cutting, that is, writing is usually done by an external drive from the IC. When a write circuit is provided inside an IC, it is desired that the voltage is 10 V or less and the current is 1 A or less due to the withstand voltage and current limit of the drive transistor.
In particular, fuse memories made of polycrystalline silicon have high reliability after disconnection, so their uses are expanding year by year.
If a write circuit is provided inside the C, special consideration must be given to the fuse memory structure since it is not easy to disconnect. FIG. 1 shows a plan view (FIG. 1a) and a cross-sectional view (FIG. 1b) of a conventional example of a polycrystalline fuse memory.
Ｓ単結晶上のＳｊ０２膜１ ０上に、フューズ・メモリ
はフューズ部１と両端の電極部２で構成され、金属配線
３が接続されている。低電流・低電圧切断を可能にする
ため、多結晶シリコン，フューズ部１の厚みはできるだ
けうすく、幅はできるだけ細くする必要があった。また
、フューズ部１の長さは、あまり長いと抵抗が大きくな
ってしまい、切断電圧が増加し、短くするには幅と同様
「加工上の問題があった。現状では、書込み電圧１０Ｖ
以下、電流１仇ｈＡ以下にするには、ヒューズ部１の厚
みを１０００△以下、幅を２ｒの以下、長さを４山肌以
下のドープト・多結晶を用いている。しかし、厚みが他
の多結晶電極（例えば、ＭＯＳ・ＦＥＴのゲートやドレ
イン・ソース、バイポーラ・トランジスタのェミッタな
ど）や多結晶配線領域の約５０００Ａ〜１〃肌に比して
特別薄いため、多結晶の堆積をヒューズ部と配線領域と
の２回、マスク・エッチング工程を２回必要とした。The fuse memory is composed of a fuse part 1 and electrode parts 2 at both ends, and a metal wiring 3 is connected to the Sj02 film 10 on the S single crystal. In order to enable low current and low voltage disconnection, it was necessary to make the polycrystalline silicon fuse part 1 as thin as possible and its width as thin as possible. In addition, if the length of the fuse part 1 is too long, the resistance will increase and the cutting voltage will increase.To shorten the fuse part 1, as well as the width, there are processing problems.Currently, the write voltage is 10V.
Hereinafter, in order to reduce the current to 1 hA or less, a doped polycrystalline material having a thickness of 1000 Δ or less, a width of 2r or less, and a length of 4 peaks or less is used for the fuse portion 1. However, the thickness is extremely thin compared to the skin of other polycrystalline electrodes (e.g., gates, drains, and sources of MOS/FETs, emitters of bipolar transistors, etc.) and polycrystalline wiring regions, so Crystal deposition was required twice in the fuse area and wiring area, and mask etching process was required twice.
かつ、前述の様に、特別フューズ部１のみ微細加工を必
要としたので、歩留り上問題があった。本発明は、叙上
の欠点を克服すべ〈なされたものであり、フューズ部の
幅または厚さを制御性の良い熱酸化することによって微
細化し、低電圧・低電流書込みが可能な多結晶シリコン
・フューズ・メモリを提供するものである。また、本発
明のフューズ・メモリは、熱酸化にする微細化が可能な
ため、特別フューズ部多結晶のための多結晶堆積、マス
ク・エッチング工程が不必要となる利点をも有する。さ
らに、フューズ部多結晶は熱酸化膜で被覆されるため、
切断前後共、外界の影響を受けにくく、信頼性が高く、
かつ熱酸化膜の熱伝導性の低さが、切断をより容易にし
ている。以下に、本発明について図面を参照しながら具
体的に詳述していく。第２図ａ，もとｃには、本発明に
よる多結晶シリコン・ヒューズＧメモリの一実施例が、
それぞれ平面図、電流方向断面図、第２図ａのＡ−Ａ′
線にそうフューズ部断面図として示されている。Moreover, as mentioned above, only the special fuse part 1 required microfabrication, which caused a problem in terms of yield. The present invention has been made to overcome the above-mentioned drawbacks, and is made using polycrystalline silicon which can be miniaturized by thermally oxidizing the width or thickness of the fuse part with good controllability, and which enables low voltage and low current writing.・Provides fuse memory. Furthermore, since the fuse memory of the present invention can be miniaturized by thermal oxidation, it has the advantage that polycrystal deposition and mask etching processes for special fuse section polycrystals are unnecessary. Furthermore, since the fuse part polycrystal is covered with a thermal oxide film,
Both before and after cutting, it is not affected by the outside world and is highly reliable.
Moreover, the low thermal conductivity of the thermal oxide film makes cutting easier. The present invention will be specifically explained in detail below with reference to the drawings. FIG. 2a, original c shows an embodiment of the polycrystalline silicon fuse G memory according to the present invention.
A plan view, a cross-sectional view in the current direction, and A-A' in Fig. 2a, respectively.
The fuse section is shown as a sectional view.
Ｓ基板上のＳｉ０２膜等絶縁膜１０の上面に、本発明に
よる多結晶シリコン・ヒューズ・メモリがフューズ部１
及び電極部２によって構成され「金属配線３は、多結晶
を熱酸化して得られる酸化膜１１を開孔して得られるコ
ンタクト部４に接して設けられている。フューズ部１は
、熱酸化によって幅、厚さ共に多結晶の酸化膜１１への
変換でうすくなっている。A polycrystalline silicon fuse memory according to the present invention is formed on the upper surface of an insulating film 10 such as a Si02 film on an S substrate.
The metal wiring 3 is provided in contact with a contact portion 4 obtained by opening an oxide film 11 obtained by thermally oxidizing polycrystal. The width and thickness of the oxide film 11 have become thinner due to the conversion to the polycrystalline oxide film 11.
これから、従来通りの寸法でフューズ・メモリをつくれ
ば酸化膜１１の厚さの約１／２の厚みだけ上面及び側面
の各表面から多結晶の寸法が小さくなっていることがわ
かる。特に、従来のフューズ部１の断面が２舷風幅×０
．１仏の厚に対し、本発明は、熱酸化前のフューズ部１
が２山肌幅ｘｏ．５ｖの厚と配線領域と同時に堆積した
Ｓｉ多結晶を用いれば、熱酸化膜１１を約０．５５仏の
形成しただけでほぼ同断面積とでき、さらに厚くすれば
、さらに小さくでき、低電流切断が可能となる。この場
合、電極部２や他の多結晶配線領域の平面積は充分大き
いので、抵抗は約２倍になるのみであり、通常この抵抗
は無視できるので、ＩＣ動作上ほとんど問題がない。フ
ューズ部１が微細化されればされる程、この熱酸化によ
る多結晶断面の減少は顕著なので、従来のヒューズ・メ
モリの微細化よりも切断電流が低くでき、かつ工程数が
少なくなる分、さらに有利となる。From this, it can be seen that if a fuse memory is manufactured with conventional dimensions, the dimensions of the polycrystalline are reduced from the top and side surfaces by approximately 1/2 of the thickness of the oxide film 11. In particular, the cross section of the conventional fuse part 1 is 2 broadside wind width x 0
．． The thickness of the fuse part 1 before thermal oxidation is
is 2 mountain surface width xo. By using a thickness of 5V and polycrystalline Si deposited at the same time as the wiring area, it is possible to have almost the same cross-sectional area by forming the thermal oxide film 11 of only about 0.55cm. becomes possible. In this case, since the planar area of the electrode portion 2 and other polycrystalline wiring regions is sufficiently large, the resistance only increases by about twice, and this resistance can usually be ignored, causing almost no problem in IC operation. The smaller the fuse section 1 is, the more remarkable the reduction in the polycrystalline cross section due to thermal oxidation becomes. Therefore, the cutting current can be lower than in conventional fuse/memory miniaturization, and the number of steps is reduced. It will be even more advantageous.
また、フューズ電極部２にコンタクト開孔部４を設ける
ことが、工程増加になるがプロセス的には容易であり、
かつ多層配線の場合には、他の多結晶配線部のコンタク
ト開孔と同機にできるので、特別な工程増加にはならな
い。多結晶シリコン・フューズ・メモリは、不純物を添
加したドープト・多結晶、または後で拡散やイオン注入
されたものが使われ、特にｎ型の場合熱酸化速度が速い
ので、熱酸化による他領域の拡散増加を抑える効果もあ
る。第２図の例において、多結晶上面を熱酸化膜前に、
例えば窒化膜で被っておけば、多結晶の側面のみが酸化
されるので、寸法の大きい電極部２や他の多結晶配線領
域の抵坑はほとんど増加せず、多結晶ヒューズ部１のみ
の断面を小さくできる。Further, providing the contact hole 4 in the fuse electrode part 2 increases the number of steps, but it is easy in terms of process.
In addition, in the case of multilayer wiring, contact openings can be made at the same time as other polycrystalline wiring parts, so there is no need to increase any special process steps. Polycrystalline silicon fuse memory uses doped polycrystals with impurities added, or those that are later diffused or ion-implanted, and the rate of thermal oxidation is particularly fast in the case of n-type, so thermal oxidation can damage other areas. It also has the effect of suppressing the increase in diffusion. In the example shown in Figure 2, the top surface of the polycrystal is placed before the thermal oxide film,
For example, if it is covered with a nitride film, only the side surfaces of the polycrystalline are oxidized, so the resistance of the large electrode section 2 and other polycrystalline wiring areas will hardly increase, and the cross section of only the polycrystalline fuse section 1 will be oxidized. can be made smaller.
極端な場合は、厚さの方が幅よりも大きいヒュ−ズ部１
が形成でき、これは基板側への熱放散がより少なくなる
ので、切断が容易となる。第３図には、本発明によるフ
ューズ・メモリの他の実施例の工程に沿ったフューズ部
１の断面図が示されている。In extreme cases, the thickness of the fuse section 1 is greater than the width.
can be formed, which results in less heat dissipation to the substrate side, which facilitates cutting. FIG. 3 shows a cross-sectional view of the fuse portion 1 along the process of another embodiment of the fuse memory according to the present invention.
同時に、他の多結晶配線領域の断面図が、第３図に対応
して第４図に示した。第３図ａと第４図ａには、Ｓ基板
上絶縁膜１０の上にＷ，Ｍｏ，Ｔａもしくはそれらの桂
化物である高融点金属５、さらにその上に多結晶層１を
積層したものを示す。例えば、高藤点金属５の厚みは１
０００Ａ以下「多結晶層は０．５〆である。第３図ｂと
第４図ｂには、多結晶フューズ部１及び多結晶配線領域
２を残した断面をそれぞれ示す。この場合、例えばフュ
ーズ部１の幅は２仏肌、配線領域２の幅は４仏肌である
。第３図ｃと第４図ｃには「多結晶をマスクにして高融
点金属５を１仏以上オーバーェッチした断面を示した。
フューズ部１の下には金属５はなくなってしまい、両端
の電極部（図示せず）で支えられて、絶縁膜１０から浮
いた形になっている（第３図ｃ）。それに対し「第４図
ｃにおいて、配線領域部２の下には金属５が残っている
。この状態で熱酸化すると、・フューズ部１は上面・底
面及び両側面の全面から酸化され、断面積は著しく減少
する（第３図ｄ）のに対し、第４図ｄにおいて配線領域
２は、金属５の存在によって厚い部分が残り、抵抗の増
加が少ないと共に、素子とのコンタクト部は金属５を介
しているので、開孔してコンタクト部を作る必要はなく
、たとえ、酸化が高温のため基板Ｓｉと金属５とが合金
しシソサイドができても、上部の多結晶２の存在のため
合金化は深く進まないで止められる。特に、第３図ｄの
様に、フューズ部１が絶縁膜１０から浮いた形になれば
、フューズ部の電流による温度上昇は、さらに容易とな
り、切断しやすい。第５図、第６図には、ヒューズ部と
配線領域のそれぞれに対し、本発明の他の実施例に沿っ
た断面図が対応して示されている。At the same time, a cross-sectional view of another polycrystalline wiring region is shown in FIG. 4 corresponding to FIG. 3a and 4a show a structure in which a high melting point metal 5 such as W, Mo, Ta or their silicides is laminated on an insulating film 10 on an S substrate, and a polycrystalline layer 1 is further laminated thereon. shows. For example, the thickness of Takafuji point metal 5 is 1
000A or less "The polycrystalline layer has a thickness of 0.5〆. Figures 3b and 4b show cross sections with the polycrystalline fuse section 1 and the polycrystalline wiring region 2 remaining, respectively. In this case, for example, the fuse The width of the portion 1 is 2 squares, and the width of the wiring region 2 is 4 squares.Figures 3c and 4c show ``The high melting point metal 5 is overetched by more than 1 inch using polycrystal as a mask. A cross section is shown.
The metal 5 is no longer present under the fuse section 1, and is supported by electrode sections (not shown) at both ends, floating above the insulating film 10 (FIG. 3c). On the other hand, in Fig. 4c, the metal 5 remains under the wiring area 2. When thermally oxidized in this state, the fuse part 1 is oxidized from the entire top, bottom, and both side surfaces, and the cross-sectional area On the other hand, in the wiring region 2 in FIG. 4d, a thick portion remains due to the presence of the metal 5, and the increase in resistance is small, and the contact area with the element has no metal 5. There is no need to open a hole to form a contact part, and even if the substrate Si and the metal 5 are alloyed and sisoside is formed due to the high temperature of oxidation, the presence of the polycrystalline 2 on the top will cause alloying. Particularly, if the fuse part 1 is in a shape floating from the insulating film 10 as shown in FIG. 3d, the temperature of the fuse part increases more easily due to the current, making it easier to break. FIGS. 5 and 6 respectively show cross-sectional views of the fuse portion and the wiring area according to other embodiments of the present invention.
多結晶シリコン１と２を選択エッチする際、例えばレジ
スト７をマスクにしてＣＶＤ酸化膜やＰＳＧ等エッチ速
度の大きい第２の絶縁膜６をェッチし、その後多結晶層
１と２をエッチする。さらに、レジスト７をマスクにし
て第２絶縁膜６をサイド）エッチすれば、幅の狭いヒュ
ーズ部１上の第２絶縁膜６は除去でき（第５図ａ入配線
領域２の上に絶縁膜６は残る（第６図ａ）。このサイド
・エッチの際、エッチ速度が小さいながら絶縁膜１０も
わずかにエッチされるが、これを防ぐためには、多結晶
層１と２の選択エッチの際、全部ェツチせずに、絶縁膜
１０の上に多結晶層１と２をうすく残す。そして後工程
の熱酸化工程で、酸化膜に変換可能な厚み（例えば０．
５仏 Ｓｉ０２膜厚に対し、約０．２仏多結晶層を残す
）の多結晶層を酸化する。また、第２絶縁膜６は、１層
でなくても多層にもすることができ、例えばＣＶＤＳｉ
０２ ｏｎＳｉ３Ｎ４も可能である。When selectively etching polycrystalline silicon 1 and 2, for example, using resist 7 as a mask, second insulating film 6 having a high etch rate, such as a CVD oxide film or PSG, is etched, and then polycrystalline layers 1 and 2 are etched. Furthermore, by etching the second insulating film 6 on the side using the resist 7 as a mask, the second insulating film 6 on the narrow fuse part 1 can be removed (see FIG. 5a). 6 remains (Fig. 6a).During this side etching, the insulating film 10 is also slightly etched, although the etch rate is low, but in order to prevent this, it is necessary to , without etching them all, leaving a thin layer of polycrystalline layers 1 and 2 on the insulating film 10.Then, in the subsequent thermal oxidation process, a thickness that can be converted into an oxide film (e.g.
Oxidize the polycrystalline layer with a thickness of about 0.2 mm (remaining a polycrystalline layer of approximately 0.2 mm with respect to the thickness of the 5 mm Si02 film). Further, the second insulating film 6 can be made of not only one layer but also of multiple layers, for example, CVDSi
02 onSi3N4 is also possible.
次に、熱酸化工程を行なえば、フューズ部１は上面及び
側面から酸化されて、充分断面積を小さくでき、一方、
配線領域２は、第２絶縁膜６の存在のため酸化による断
面積の減少はわずかである（第５図ｂと第６図ｂをそれ
ぞれ参照）。以上の様に、本発明によれば、多結晶シリ
コンのフューズ部を熱酸化することによって、断面積を
精度よく減少することができ、しかも多結晶配線領域用
の多結晶層と同じものが用いられるため、工程数が減少
できる。Next, if a thermal oxidation process is performed, the fuse part 1 will be oxidized from the top and side surfaces, and the cross-sectional area can be sufficiently reduced.
In the wiring region 2, due to the presence of the second insulating film 6, the cross-sectional area decreases only slightly due to oxidation (see FIGS. 5b and 6b, respectively). As described above, according to the present invention, by thermally oxidizing a polycrystalline silicon fuse part, the cross-sectional area can be reduced with high accuracy, and the same polycrystalline layer as that for the polycrystalline wiring region is used. The number of steps can be reduced.
勿論、本発明は工程こそ増加するが、従来の多結晶フュ
ーズ・メモリ構造にも適用でき、切断電流化が達成でき
る。本発明の具体例として、主に多結晶シリコン・フュ
ーズについて述べてきたが、熱酸化や陽極酸化の可能な
他の配線材料、例えばＡＩ，Ｎ−Ｓｉヒューズ０にも適
用でき、同様な効果を得ることができる。本発明は、Ｉ
Ｃに書き込み回路の組込まれた低容量プログラマフル・
ＲＯＭとしてのヒューズ・メモリとして有効であり、Ｍ
ＯＳ・ＩＣ、バィポーラ・ＩＣの両方に適用でき、応用
範囲は極めて広夕し、。Of course, the present invention increases the number of steps, but it can also be applied to conventional polycrystalline fuse memory structures and can achieve increased cutting current. As a specific example of the present invention, we have mainly described polycrystalline silicon fuses, but it can also be applied to other wiring materials that can be thermally oxidized or anodized, such as AI, N-Si fuses, and similar effects can be achieved. Obtainable. The present invention is based on I
Low capacity programmer full with built-in writing circuit in C.
It is effective as a fuse memory as ROM, and M
It can be applied to both OS/IC and bipolar IC, and the range of applications is extremely wide.
第１図ａとｂは、それぞれ多結晶シリコン・ヒューズ・
メモリの従来例の平面図及び断面図、第２図ａとｂとｃ
は、それぞれ本発明による多結晶０シリコン・ヒューズ
・メモリの一実施例の平面図及び互いに直交する断面図
である。
第３図ａ〜ｄは、本発明によるメモリの製造工程例に沿
ったヒューズ部の断面図であり、第４図ａ〜ｄは、第３
図に対応した配線領域の断面図である。第５図ａとｂは
、本発明によるメモリの他の製造工程例を示す断面図、
第６図ａとｂは、第５図に対応した配線領域の断面図で
ある。１・・・・・・多結晶シリコン・ヒューズ部、２
・・・・・・多結晶シリコン・ヒューズ電極部または配
線領域、３…・・【金属配線、４・・…・コンタクト部
ト５……高融点金属、６・…・・第２絶縁膜、７・・…
・レジスト、１０・…・・基板上絶縁膜、１１，２１・
・…・熱酸化膜。
第１図
第３図
第４図
第２図
第５図
第６図Figures 1a and 1b show polycrystalline silicon fuses, respectively.
Plan view and sectional view of conventional example of memory, Figure 2 a, b and c
1A and 1B are a plan view and a mutually orthogonal cross-sectional view, respectively, of an embodiment of a polycrystalline silicon fuse memory according to the present invention. 3A to 3D are cross-sectional views of the fuse portion along an example of the manufacturing process of the memory according to the present invention, and FIGS.
FIG. 3 is a cross-sectional view of a wiring area corresponding to the figure. 5a and 5b are cross-sectional views showing other manufacturing process examples of the memory according to the present invention,
6a and 6b are cross-sectional views of the wiring area corresponding to FIG. 5. FIG. 1... Polycrystalline silicon fuse section, 2
...Polycrystalline silicon fuse electrode part or wiring region, 3... [Metal wiring, 4... Contact part 5... High melting point metal, 6... Second insulating film, 7...
・Resist, 10... Insulating film on substrate, 11, 21.
...Thermal oxide film. Figure 1 Figure 3 Figure 4 Figure 2 Figure 5 Figure 6
Claims (1)
具備する多結晶シリコン・フユーズ・メモリにおいて、
多結晶フユーズ部の少なく共１つの表面に形成された前
記多結晶の熱酸化膜の厚みが、前記多結晶フユーズ部の
厚みもしくは幅の１／２以上であることを特徴とする多
結晶シリコン・フユーズ・メモリ。 ２ 前記多結晶フユーズ部の前記絶縁膜側の底面が、前
記多結晶の熱酸化膜で被覆されていることを特徴とする
特許請求の範囲第１項記載の多結晶シリコン・フユーズ
・メモリ。 ３ 絶縁膜上に堆積した多結晶シリコン膜を、少なくと
も電極及び配線に用いる多結晶配線領域及び該配線領域
より幅狭い多結晶フユーズ部とその両端のフユーズ電極
部とを残す工程と、熱酸化工程によつて前記配線領域及
び前記フユーズ部、フユーズ電極部の表面に多結晶の熱
酸化膜を被覆し、かつ前記熱酸化膜の厚みが前記フユー
ズ部の多結晶厚みもしくは幅の１／２以上にせしめる工
程と、前記フユーズ電極部の一部にコンタクト用酸化膜
開孔部を設ける工程より成る多結晶シリコン・フユーズ
・メモリの製造方法。 ４ 前記多結晶シリコン膜上に第２の絶縁膜を被覆し、
前記配線領域及び前記フユーズ電極部上の一部には前記
第２絶縁膜を残し、前記フユーズ部上には前記第２絶縁
膜を残さない工程の後、前記熱酸化工程を行なうことを
特徴とする特許請求の範囲第３項記載の多結晶シリコン
・フユーズ・メモリの製造方法。 ５ 前記第２絶縁膜のサイド・エツチにより前記フユー
ズ部上の前記第２絶縁膜を除去することを特徴とする特
許請求の範囲第４項記載の多結晶シリコン・フユーズ・
メモリの製造方法。 ６ 前記絶縁膜と多結晶シリコン膜の間に高融点金属膜
をはさみ、前記配線領域及び前記フユーズ部、フユーズ
電極部の多結晶を選択的に残した後、該多結晶をマスク
にして前記高融点金属膜をオーバ・エツチして、前記フ
ユーズ部下のみの前記高融点金属を除去する工程の後、
前記熱酸化工程を行なうことを特徴とする特許請求の範
囲第３項から第５項のいずれか記載の多結晶シリコン・
フユーズ・メモリの製造方法。[Claims] 1. In a polycrystalline silicon fuse memory formed on a substrate covered with an insulating film and provided with electrodes at both ends,
A polycrystalline silicon film characterized in that the thickness of the polycrystalline thermal oxide film formed on at least one surface of the polycrystalline fuse portion is 1/2 or more of the thickness or width of the polycrystalline fuse portion. fuse memory. 2. The polycrystalline silicon fuse memory according to claim 1, wherein the bottom surface of the polycrystalline fuse portion on the insulating film side is covered with the polycrystalline thermal oxide film. 3. A step in which the polycrystalline silicon film deposited on the insulating film is left with at least a polycrystalline wiring region used for electrodes and wiring, a polycrystalline fuse portion narrower than the wiring region, and fuse electrode portions at both ends thereof, and a thermal oxidation step. A polycrystalline thermal oxide film is coated on the surfaces of the wiring region, the fuse part, and the fuse electrode part, and the thickness of the thermal oxide film is 1/2 or more of the polycrystalline thickness or width of the fuse part. 1. A method for manufacturing a polycrystalline silicon fuse memory, comprising the steps of: forming an oxide film opening for contact in a part of the fuse electrode section; 4. Covering the polycrystalline silicon film with a second insulating film,
The thermal oxidation step is performed after the step of leaving the second insulating film on a part of the wiring area and the fuse electrode part and not leaving the second insulating film on the fuse part. A method for manufacturing a polycrystalline silicon fuse memory according to claim 3. 5. The polycrystalline silicon fuse according to claim 4, wherein the second insulating film on the fuse portion is removed by side etching the second insulating film.
Memory manufacturing method. 6. Sandwiching a high melting point metal film between the insulating film and the polycrystalline silicon film, selectively leaving the polycrystals in the wiring region, the fuse part, and the fuse electrode part, and then using the polycrystals as a mask to remove the high melting point metal film. After the step of over-etching the melting point metal film to remove the high melting point metal only below the fuse,
Polycrystalline silicon according to any one of claims 3 to 5, characterized in that the thermal oxidation step is performed.
Method of manufacturing fuse memory.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP55180003A JPS60954B2 (en) | 1980-12-19 | 1980-12-19 | Polycrystalline silicon fuse memory and its manufacturing method |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP55180003A JPS60954B2 (en) | 1980-12-19 | 1980-12-19 | Polycrystalline silicon fuse memory and its manufacturing method |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS57104252A JPS57104252A (en) | 1982-06-29 |
| JPS60954B2 true JPS60954B2 (en) | 1985-01-11 |
Family
ID=16075747
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP55180003A Expired JPS60954B2 (en) | 1980-12-19 | 1980-12-19 | Polycrystalline silicon fuse memory and its manufacturing method |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS60954B2 (en) |
Families Citing this family (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS599958A (en) * | 1982-07-07 | 1984-01-19 | Fujitsu Ltd | Semiconductor device |
| JPS6122652A (en) * | 1984-07-10 | 1986-01-31 | Toshiba Corp | Semiconductor device |
| JP2523856Y2 (en) * | 1989-07-28 | 1997-01-29 | シャープ株式会社 | Semiconductor device |
-
1980
- 1980-12-19 JP JP55180003A patent/JPS60954B2/en not_active Expired
Also Published As
| Publication number | Publication date |
|---|---|
| JPS57104252A (en) | 1982-06-29 |
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