JPS609135A - Method for formation of lsi acception map - Google Patents

Abstract

PURPOSE:To enable to form the non-defective map of LSI covering the whole region of an IC wafer by a method wherein a testing device in addition to an LSI circuit is assembled in an LSI chip, the defectiveness of IC wafers is tested, and the result showing acception or rejection is inputted to a holding device. CONSTITUTION:An LSI 2 is compored of an LSI circuit 10 having the circuit constitution same as that of the LSI and a testing circuit 30 which is arranged within the LSI 2 adjoining to the LSI circuit 10. The application pattern for testing is inputted to the block 10 to be tested as a test block, and the test circuit 30 with which the accesption and rejection of the block 10 to be tested will be judged by comparing the output of the LSI 2 with certain expected pattern is formed. The acception and rejection of the LSI 2 are supplied to the result holding device, which is a fail flag 21, provided in the scribing region of the IC wafer 1 as the result of test. The acception map of the LSI ranging to the whole surface of the wafer 1 can be formed by inputting a shift signal SH into the fail flag pertaining to the test result held in said fail flag 21 and by repeating a shifting operation successively.

Description

[Detailed description of the invention]

(1) Technical field of the invention The present invention relates to a method for creating a non-defective LSI map, in particular
The present invention relates to a method for creating a good LSI map that can be used to display the quality of LSI embedded in a FC wafer on a FC wafer. (2) Background of the technology At the LSI manufacturing stage, when the LSI is incorporated into a product such as a computer, it is necessary to maintain the desired performance. The LSI is tested individually (wafer probing test, etc.) while buried in the
After chip separation, only LSI chips that are found to be good are used in products. Various methods have been used to clearly identify which LSI chips are found to be good in such LSI quality tests and those which are found to be poor in Sr depth. Originally this L
If the quality of the SI could be analyzed at a glance within the IC wafer, it would be convenient for those involved in chip cutting. Since the time required is often relatively long, the current situation is that it is difficult to cover the analysis of pass/fail. This invention provides such I
This research aims to develop a technique for analyzing good (or defective) LSI products in a number of steps related to the quality test of LSIs in C wafers. (3) Conventional technology and problems

[The test method for LSI is schematically shown in Figure 1. This test method is based on the L S embedded in the IC wafer 1.
Install the LSI tester 3 to I 2, and engage the pins of the LSI tester 3 to the specified terminals of the LSI 2! U11-
Generate various application patterns for dest with the 8r tester 3. Access L'LS I 2 from the outside, apply the application pattern to L S' I 2, and compare the results with the reference pattern. In this LSI test, the pass/fail results of each LSI 2 are determined by connecting an IC tester 3 to a computer and testing each LSI one after another. As the test progresses, the hJ computer remembers whether the LSI is good or defective, and waits until the LSI is separated. In the LSI2 test method, all the measurement circuits for LSI testing are built into the IC tester 3, and the LSI2 is only tested by connecting its terminals (that is, the terminals of the IC tester 3 to the pins). Therefore, the total number of good and bad LSI 2 is n
It was inconvenient to analyze whether the LSI was good or bad because it had to rely on the memory of the device. Also, in the conventional test method, LS
It takes a considerable amount of time to connect the measurement terminal of I tester 3 to 1812 and measure it, and due to the constraint on the number of bins, the LS
Tests such as I2 were likely to be difficult. These inconveniences have become more serious as LSIs have been integrated on a larger scale in recent years, and conventional LSIs are no longer viable.
SI's testing methods were becoming insufficient. (4) Purpose of the Invention This invention was made in view of the above-mentioned conventional problems, and its purpose is to simplify the pass/fail test of LSI, shorten the number of defects during the test, and create a map of 181 non-defective products. (5) lr of the invention: 4. In order to achieve the above object, this invention incorporates testing means in addition to the LSI circuit into the LSI chip, and While the test means can test the quality of the LS'1 circuit, means for holding the test results by the test means are installed in the scribing area of the IC wafer every 1 to 81 chips. The gist of this invention is to create a non-defective LSI map covering the entire IC by inputting the results into the holding means.The most characteristic feature of this invention is that L.S.
This allows the I-chip to perform a self-test 1!1li-J. The test means built into the LSI chip for this self-test consists of a pattern to be applied to the LSI circuit to be tested and a pattern corresponding to this application pattern.
(a memory that stores the expected pattern to be output from the LSI circuit, and a memory that stores the expected pattern to be output from the LSI circuit, and
It comprises means for comparing the output pattern from the circuit with the expected pattern, and means for generating a good/bad signal for the 81 circuits in response to the output from the comparing means. The signal from the good/bad signal @ generating means is configured to be input to the holding means installed outside the LSI, and the holding means is placed between the LSI chip and the adjacent LSI chip within the IC wafer. That is, it is provided in the scribing area. Such a holding means is provided for each LSI chip, and one holding means is provided adjacent to it in a predetermined direction.
A shift 1 to register is constructed by connecting the shift register with the holding means of the shift register, and by applying a shift clock to this shift register, a 0.1 sequence of the dest result is obtained. A fail flag flip 70 tab may be used as a holding means for configuring such shift registers.
Alternatively, a light emitting diode (L I3D ) may be used and the LED may be blinked based on the LSI dest result. Embodiments of the present invention will be described in detail below with reference to the accompanying drawings. (6) Implementation of the invention FIGS. 2 and 3 are diagrams showing an embodiment of the invention. First, M of LSI2 used in this example
e? To explain M, this LSI 2 includes an LSI circuit 10 having a circuit configuration similar to the conventional LSI, and is arranged in the LSI 2 adjacent to this LSI circuit 10, and uses the LSI circuit 10 as a block to be tested. (hereinafter LS
A test application pattern is input to the block under test 10, with the I circuit 10 being the block to be tested, and a comparison is made between the expected pattern which is the output pattern, and the test voltage of the block under test 10 is determined. It has a test means, ie, a test circuit 30, for determining pass/fail. The test circuit 30 includes a memory 15 that has an application pattern section 15a that stores a pattern that should be applied to the block under test 10, an expected pattern section 15b that stores a pattern that should be output from the block under test 1 (), and a memory 15 that stores a pattern that should be applied to the block under test 10; It has a coincidence detection means 3 for comparing the actual output pattern from the test block 10 and the expected pattern. The memory 15 includes a read-only memory (ROM) in which data is written in the applied pattern section 1581 and the expected pattern section 15b, respectively.
is used. Furthermore, the address of the applied pattern section 15a and the corresponding address of the expected pattern section 15b are complementary to each other. Address information to memory 15 is created by address counter 11 and address decoder 12. The output of the address decoder 12 is branched into two streams, one of which is inverted by the address inversion circuit 13. The non-inverted address and the inverted address are selected by a multiplexer 14 which is selectively activated by a switching signal S.
The application pattern portion 1 in the memory 15 is selected according to the
5a and the expected pattern section 15b, the purpose of which is to switch addresses that are complementary to each other. A multiplexer 16 is disposed between the memory 15 and the block under test 10, and divides the data to the block under test 10 between the normal horn side Δ and the memory 15 side depending on whether or not the DST signal T is generated. I am trying to select between and input it. That is, the multiplexer 16 outputs the test signal 1
- When ■ is 1, the memory 15 side is selected and data is input to the target I to block 10, and T is O.
11 normally selects the input side Δ and inputs data. During the test of the block under test 10, the J3 pattern output is temporarily held as parallel information in the shift 1 to register 18, and then converted to serial data and sent to the coincidence detection means 3.
Enter 1. - The number configuration means 31 outputs the data (pattern) output from the shift register 18 to the destination block [1 ts 10 output] 3.
Comparator 1 that compares all bits according to the number of bits
Although 4111 signals may be generated by a node, this embodiment employs a circuit configuration in which the number of outputs is compared using a compressed bit width. That is, according to this embodiment, the matching detection means 31
For example, a counter 19 having a mode terminal MO to which output data of the block under test 10 is serially transferred, and an expected pattern section 15 of the output data of this counter 19 and a memory persimmon.
If the output of the block under test 10 is m bits, the counter 19 counts the number of 1's in the m bits and compresses the data into bits ( or degenerate) data is output. Here, the relationship between m and throat is as follows: 1=9.0g2it (when m = 2'1') 1=
(10 (72m >+1'(m≠2''). Among the conditions above, α is a positive integer. In line with this, pitch I and width are also set in the memory 15. That is, the application pattern section 15a of the memory 15 has a pitch 1 to a width (in FIG.
3, on the other hand, the expected pattern section 151) has a bit width (in FIG. )have. In this manner, the output pattern from the block under test 10 compressed into bits is compared with the expected pattern from the memory 15 in the -21 comparator 20 of the negative number output circuit 31, and the result is a match signal. Or output as a mismatch signal. This result signal is externally transmitted to the test circuit 30 into a fail flag 21 provided outside the LSI chip, and this fail flag is activated based on the coincidence signal or mismatch signal. The fail flag 21 is set to 41. from the flip-flop. t, and the compressed output data of the destination block 10 is stored in the memory 1.
When the data from 5 match, it outputs a signal of 0. When it does not match, it outputs a signal of 1 and holds it. Therefore, the fail flag 21 is located at the L where the other fail flag 21 is attached.
The machine office worker (OL) is used as a holding means to hold the test results as to whether the SI chip is good or not. As is clear from FIG. 3, the fail flags 21 are arranged in stages for each LSI chip, and each of the seven fail flags 21 is connected in a fixed direction (one vertical column in FIG. 3). Shift 1 to register 47.t operate in synchronization with a certain clock φ0 operation.The result holding means, that is, the fail flag 21 is connected to the LSI depth and LS in the IC wafer.
It is arranged between the I-depth, that is, in the scribing area, and is reserved. The LSI test and non-defective product map for the IC 1-1, which has the 4M structure as explained above, and the test result holding means are incorporated as shown in FIGS. 2 and 3. We will explain the creation procedure. First, I will explain the operation of LSI 2.
S I 2 selects the normal input side of Marubrek-IJ16 when the Dest Shintan T is O, and inputs data from the normal input side to the block under test, that is, the LSI circuit 10, It is processed by the block under test 10 and output to the normal output side B. Next, when the LSI performs a self-test, this test is started with the dest signal T set to 1. When the test signal T becomes 1, a trigger signal Q as shown in FIG. 4 is applied to the count enable terminal 23, and the address counter 11 starts counting in synchronization with the clock ψf. Since this is a self-testing, address counting is performed in a style in which the address counter is incremented by one hair at φ1. As a result of this operation, address information is supplied from the address decoder 12 to the application pattern section 15a of the memory 15, a predetermined address of the application pattern section 15a is called based on this address information, and the data at that address is Since the signal D' is 1, it is selected by the Jζ remultiple node 16 and inputted to the block under test 10. On the other hand, the expected pattern section 15b sends the designated address to the address inversion circuit 13. Inversion 1. The data read out for the address is supplied to the inverter 20. In the block under test 10, after the application pattern is supplied from the application pattern section 15a, a predetermined input series is applied. Then, a predetermined output series appears on the output side, and this output is used as data to be sent to the shift register 12.
Incorporate into. The acquisition operation in the shift 1 to register 12 is performed along the acquisition tarlock φl'. The acquisition clock φ1' has a predetermined delay (time delay) after the application pattern is called from the memory 15 until it passes through the multiplexer 16 and the block under test 10, so this delay is one hour, which is later than IJφf. It becomes a clock. On the other hand, the data taken into the shift mill register 18 is serially transferred to the counter 19 of the minus number output circuit 31, but this serial transfer is performed in synchronization with the transfer lock φ2. The transfer lock φ2 transmits a tarlock according to the output pin 1 to number from the block under test after the clock φ]' for loading the shift 1 register is activated and until the wash clock is output. . For example, if the output power of block 1o is n1 as described in Section 2, then 1n will be emitted between the transmission of tarokk φ1' and the next transmission. Generates a clock signal. In synchronization with this transfer lock, the counter 19
The data is input one bit at a time from the shift 1 register 18 to the mode terminal of. The counter 19 is configured to increment one hair when the mode from the shift register 18 is 1, so when it reaches 1, it counts up in synchronization with the transfer lock. In other words, the counter 19 counts how many 1's there are among the outputs of the m-pips 1 to 1 of the block under test 10. Therefore, the count result of the counter 19 is supplied from the counter 19 to the comparator circuit 20 as the output of the block under test 10 compressed from the point of view (2), and here the memory 15
It is compared with the expected pattern of the bits sent from the expected pattern unit 15b, and if there is a match in this comparison, a match signal is output, and if there is no match, a mismatch signal is output. This results in the self-test of the LSI ending in line 41. The pass/fail of the LSI 2 determined by the test circuit 30 incorporated in the LSI 2 is determined as a test result C by a result holding means disposed in the scribing area of C1, that is, a fail flag 21. supplied to The fail flag 21 indicates that if there is a match in the comparison operation sent to the comparator 20 by J3, O will be obtained as the result signal C, and if there is no match, the result signal C will be set to 1, that is, F]. is output. The fail flag 21 operates in synchronization with the clock φO, which is delayed by a predetermined period of time ('I) after the clock φ1'. You can follow each LS
Since the test results are displayed on all of the fail flags 21 connected to I, the test results held in these fail flags 21 can be shifted for one column by inputting the shift signal 5t-1 to the fail flags. Then, in the same manner, perform the shift operation for the column ①, repeating the shift operation sequentially in the same manner as Jζ, thereby producing seven good LSI chips to be placed in front of the wafer 1. I can do that. Although a fail flag is used as the test result holding means in the embodiment described above, the present invention is not limited to such a member, and for example, a light emitting diode may be used as the test result holding means. In this case, since the pass/fail of the LSI obtained as a test result is displayed by the lighting or non-lighting of the light emitting diode, it is possible to create a good product map on the IC chip 1 itself, and the operator can You can easily check whether the LSI is good or bad. When a fail flag (J, fail flag flip Cl knob) is used as a test result holding means as in d3 in my father's example, the reliability of this flip knob becomes a problem, but depending on the LSI mask length, Is it more than enough? ? This problem can be avoided by configuring a flip-flop circuit with a mask length C of i, or by converting the flip-flop into two wheels, or by chaining it with a shift register to make it into two wheels. (7) Effect of the invention" Also, as explained above in n+2, if this invention has j, then
While constructing the LSI so that it can perform self-tests, it is also possible to provide a means for retaining the test results of the LSI.
Alternatively, since the good quality map is created by having the user perform a direct 4F display operation, it is easy to create a good quality map.
1i, and has the effect that information for analyzing good/bad LSI products on IC wafers can be easily obtained. Furthermore, in establishing this method of creating a good product map, we improved the LSI itself so that the TSR could overcome the self-test, which made the operation of the LSI test itself even easier and reduced the test time. It is also possible to achieve the effect that the time can be shortened. In particular, this effect holds great promise in light of the fact that the degree of integration of 1c is likely to increase in the future, and the conventional LSI test using the ICC Brata method is gradually becoming a VA valve. be.

[Brief explanation of drawings]

FIG. 1 schematically shows the operation status of a conventional pass/fail test for LSI, and FIG. Figure 1 and Figure 3 are enlarged views showing the configuration of an IC wafer for which a good product map is created according to the present invention.
FIG. 4 is a time rate diagram showing click operations at each part of the circuit configuration shown in FIG. 1...IC wafer 2...S (3...IC tester 10...block under test (LSI circuit) 11...
Address counter 12... Address de''-da 13... Address inversion circuits 14, 16... Multiplexer 15... Main input 15a... Application pattern section 15b
...Expected pattern section 18...Shift 1-register 19...Counter 20
... Comparator 21 ... Fail flag (test result holding means) 30.
...Test circuit (test means) 31...-Multiple structure circuit Special FF Applicant Fujitsu Ltd. Figure 1 Figure 3 Figure 2 I II

Claims (1)

[Claims] 1) A test means is incorporated in the LSI chip in addition to the LSI circuit, and the test means is used to test whether the LSI circuit is good or not. A means for holding the test results by the test means is provided for each LSI chip, and the pass/fail results of the LSI chips are input into the holding means to create a 1-3L good product map covering the entire IC wafer. [Method for creating SI quality product map] 2) The method for creating a non-defective LSI map according to claim 1, wherein a fail flag flip-flop is used as the means for storing test results. 3) The method for creating a non-defective LSI map according to claim 1, wherein a light emitting diode is used as the means for retaining the test results.