JPS6089963A - Integrated circuit memory device - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a semiconductor device, and is particularly directed to a Flip-Flop type semiconductor memory device constructed from a VcMISFET type semiconductor device.

As a semiconductor memory device, a flip-flop type dynamic memory type semiconductor memory device comprising four MISFETs is known from US Pat. No. 3,541,530. This dynamic memory type semiconductor storage device does not store information by constantly supplying current from the power supply, so there is no wasted power consumption. Furthermore, the area of the memory cell can also be reduced. However, since stored information is lost due to leaks, it is necessary to periodically refresh it. Therefore, a complicated refresh peripheral circuit is required.

On the other hand, in a static memory type semiconductor memory device, a flip-flop type memory device in which two inverter circuits consisting of a load MISFET and a drive MISFET are cross-cancelled is disclosed in U.S. Patent No. 3,560,76. Known by No. 4. This type of memory device does not require the refresh circuit used in the dynamic memory type semiconductor memory device described above.

However, power consumption is high. In order to reduce this power consumption, it is necessary to reduce the channel conductivity β (channel width W/channel length Il'') in the load MISFET of the memory device.As a result, the channel length must be increased. Therefore, the problem arises that the size of the load MISFET increases and the integration density deteriorates.Therefore, in order to reduce the load means and improve the integration density, the load MISFET
Japanese Patent Application Laid-Open No. 50-1 proposed using polycrystalline silicon made with high resistance by ion implantation as a load means instead of SFET.
It is known from Publication No. 1644.

(3) However, it is difficult to make the area occupied by a memory cell as small as that of a dynamic memory type memory cell.

Therefore, there has been a desire for a memory device that has a low integration density and is easy to refresh, comparable to a dynamic memory type memory device.

One object of the present invention is to operate the cell itself in a static memory manner, constantly compensating for charge leakage with a high resistance element, and to connect the data lines to four M I S F E
An object of the present invention is to provide a semiconductor memory device that operates in a dynamic memory manner, such as a flip-flop type memory cell made of Ts.

Another object of the present invention is that four M I S F E T
An object of the present invention is to provide a static memory type semiconductor memory device having a cell area approximately equal to that of a flip-flop type memory cell made of s.

Another object of the present invention is to provide a semiconductor inverter device suitable for a semiconductor memory device and a method of manufacturing the same.

Still another object of the present invention is to provide a highly integrated MIS type semiconductor memory device with a multilayer wiring structure.

One embodiment of the present invention uses four MISFETs to configure a dynamic flip 7-lop type memory cell that holds charge, which is written information, in an information storage means, and transfers the amount of charge leaking from the information storage means to a power supply voltage line. The information storage means is supplemented through a connected load means made of high-resistance polycrystalline silicon.

The objects, features, and effects of the present invention will be clearly understood from the following description of preferred embodiments based on the drawings.

In FIG. 1, a portion 1 indicated by a dashed line is a diffusion layer formed by selectively dispersing impurities of a conductivity type opposite to that of the substrate on the surface of the semiconductor substrate.
The part 2a*2be2c shown by the broken line is a polycrystalline silicon layer, and 2a is the power supply line (VDDlin
e), 2b is one end of the transmission FET Qs-Q4, the source of the driving FETQ+-Qt and the driving FE
The line connecting the gate of TQ=-Qt and the load resistances R, , R, 2C is the word line (Word L
ine). 3a and 3b are load resistors R+ and Rz
3alJ''-Rt, 3b in the polycrystalline silicon layer constituting
is R2. This is the polycrystalline silicon layer 2a, 2b.
However, the impurity concentration is lower and the resistivity is higher than that.

5a, 5b+ 5c are aluminum electrode wiring films;
is the true digit line (d Line), 5b is the ground life (GND Line), and 5C is the ver digit line (d Line). 6a and 6b are contact portions between the diffusion layer and the electrode wiring portion constituting the other end of the transmission FET Qa, and a portion 7a indicated by a two-dot chain line;
, 7b are driving FET Q+, Q! This is the contact portion between the silicon gate of the transmission FET Qs=C4 and the diffusion layer forming one end portion of the transmission FET Qs=C4, and is the portion directly contacted to the diffusion layer by the polycrystalline silicon layer.

This part of the contact technology is called direct contact.

Figure 2 shows the semiconductor memory device (memory cell A/) shown in Figure 1.
It is a circuit diagram of device (memory cel+). In the figure, all portions shown within the dashed line frame are made of polycrystalline silicon layers formed at the same time. In other words, the power supply voltage line (vl) to which the power supply voltage is applied
/1ne) is also the wire bonding part for connection with the external lead.
Everything except the ding pad is made of polycrystalline silicon.

The junctions Da and Db are the direct contact portions 7a and 7b shown in FIG. 1.

FIG. 3 is a layout diagram in which four memory cells of FIG. 1 are arranged. In the figure, a broken line indicates a polycrystalline silicon layer, a solid line indicates an aluminum (ε) wiring layer, and a two-dot chain line indicates a direct contact portion. The diffusion region has been omitted to simplify the diagram. Furthermore, in the figure, C1,.

C1, is the diffusion layer in the first memory cell and A A ,
The contact portion of the digit line that consists of the digit line shares the contact in another memory cell (not shown).

Similarly, C21*c2□ is a contact part in the second memory cell, Ca5e Cat is a contact part in the third memory cell, and C4HC4t is a contact part in the fourth memory cell, and these are also connected to other memory cells. They share contacts (not shown). For the digit line, both contacts with Al are shared by other memory cells, so from the perspective of one memory cell, only one contact is required. G, , G, , G are contact portions between the adjacent line and the diffusion layer (source region) in the first, second, third, and fourth memory cells, respectively. Since one contact with the ground line is required for one memory cell, as a result, only two contacts are required for one memory cell. Rt - Rt is the load resistance of the first memory cell,
Rs, R, C load resistance of the second memory cell, RseRe
represents the load resistance of the third memory cell, and R1, R@ represents the load resistance of the fourth memory cell. As is clear from the figure when looking at the arrangement of four memory cells, CH+
Ctt + G2 s Rs e The second memory cell indicated by R4 is C1z C+t* G+ e Rt e
O is also arranged with the first memory cell indicated by R4 shifted laterally. C5I-C5t-Gs, 11!
The third memory cell, denoted l , Ra , is arranged with the first memory cell rotated by 180° about point II AIT. Furthermore, C411C4! l G4 +
The fourth memory cell indicated by R7*RII is arranged horizontally shifted from the third memory cell. Four such memory cells are further connected to -L, line and Lt
They are arranged in the vertical direction (or column direction) with line symmetry about the Lt line. Also, in the horizontal direction (or row direction), shift as is)
(shift) l, are arranged in a state to form a memory matrix.

Next, the MISFET section and load resistance section within the memory cell will be explained.

Figure 4A shows a MISFET, especially the LOCOS (Local Oxidation
ofSilicon) structure. 1 is a diffusion layer, 8a is a semiconductor surface badge 5i01[, 8b&-1
A gate insulating film, 9 is a semiconductor substrate.

Further, FIG. 4B shows a portion of the polycrystalline silicon layer for loading.

2aw 2b+ 2c is a low-resistance polycrystalline silicon layer portion used as a wiring, and 3a is a high-resistance polycrystalline silicon layer portion used as a load resistor.

4 is a CVD-8in film. The figure shows the state immediately after the impurity is introduced into the polycrystalline silicon layer.

FIG. 5A (when the room temperature is 25° C.) and FIG. 5B (when the room temperature is 70° C.) show how much current should be supplied through the load means in order to retain the stored information. This is the holding current IDM in the two memory cells.
and mark 711] Correlation diagram with tolerant VDM for four samples a
@ b, ct d are shown. The holding current IDM and the applied voltage DM are the current flowing in the power supply voltage line (VDD Line) shown in FIG. 2 and the voltage supplied to that line, respectively.

As is clear from this figure, when the room temperature is 25°C, even in sample a, which requires the largest holding current, when the power supply voltage VDD is 12V, it is approximately 5X per memory cell.
]O-'A, which makes it possible to retain information. Therefore, the power consumption per memory cell is 0.6
X 10-' W (0.6 μW) is sufficient.

Note that as the temperature of the device increases, the current required to retain information increases. This is because the current leaking through the junction becomes thicker as the temperature rises.
The diagram shows the required holding currents for the same samples a, b, c, and d as in Figure 5A, and a comparison between the two diagrams will clarify the above.

However, according to the present invention, the specific resistance of the polycrystalline silicon layer used as the load means decreases as the temperature rises, so the supply current increases as the leakage current increases. Due to temperature rise, l:
There is no risk that information retention will become impossible.

Note that the resistance of the portion of the polycrystalline silicon layer constituting the load means is controlled by adjusting the amount of impurity implanted, for example, by ion implantation. FIG. 6 is a correlation diagram showing the correlation between the amount of ion implantation and the resistance value R6.

Ion implantation amount is 10111/CIi! In the following, 1
The resistance value is approximately constant at 010Ω/mouth, and the resistance value can be easily controlled. However, it goes without saying that when the holding current is large, it is necessary to increase the amount of ion implantation in order to lower the resistance value.

Next, the memory cell (me-mo) of the present invention shown in FIG.
ry cell) will be explained using FIGS. 7A to 7B and FIGS. 8A to 88.

(1) A semiconductor substrate having a specific resistance of 8 to 200 cm is prepared, and a thermal oxide film with a thickness of 1 μm is formed on the surface of this substrate.

(The thermal oxide film is selectively etched to expose the surface of the semiconductor substrate where the MISFET is to be formed.

(3) After bonding, a thickness of 750 mm is applied to the exposed semiconductor substrate surface.
A gate oxide film (Sin, ) 12 of ~100 OA is formed. (See Figures 7A and 8A) (4) Gate oxide film 1 in the area that should be in direct contact with the polycrystalline silicon layer
2 is selectively etched to create a direct contact hole 1.
Form 3.14. (See Figures 7B and 8B) (5) Oxide film 11, gate enhancement film 12, contact hole 1
3.14] Silicon is applied to the entire surface of the semiconductor substrate with CVD (Chemical Vapor Dep).
Deposited by osi-tion method to a thickness of 300 mm.
Form a polycrystalline silicon layer of 0 to 500 (lA).

(6) Selectively etching the polycrystalline silicon layer 14. Then, using the remaining polycrystalline silicon layer 4 as a mask, the gate oxide film 12 is selectively etched. (7th
(See Figure C and Figure 8C) (7) A CVD-8 inch film is deposited on the entire main surface of the semiconductor substrate 10 to a thickness of 2,000 to 30 cm.
Deposit to a thickness of 00A.

(8) The above CV only on the polycrystalline silicon layer that is aligned with the resistor
D-8in, film 15 is selectively left (9) Using the polycrystalline silicon layer as a mask, diffuse phosphorus into the semiconductor substrate 10 to form a source region 16 and a drain region 17 with an impurity concentration of 10'' atoms/Ca. At this time, impurities are also introduced into the polycrystalline silicon layer and the gate electrode 1
8, Direct contact 7 b, Word 1in
e20. # and VDD line 21 are formed. (See Figures 7D and 8D) 0 [The above CVD-8in, film 1
5 is removed, and PSG is applied to the entire main surface of the semiconductor substrate 10.
(Phospho-8ili-cate-Glass)
The film 20 is formed to a thickness of 7000-9000A.

αD Thereafter, A/ is deposited on the entire surface of the semiconductor substrate ]00 film to form an Al film 21 having a thickness ]μ.

α side: The above Al film is selectively etched, and the ground line y
(ground 1ine) 22, and digi
Form t 1ines23.24. (See FIGS. 7E and 8E) The method for obtaining the memory cell of the present invention has been described above, but the following modifications can be made to this method.

In order to adjust the resistance value of the fat load resistor R+ -R2, impurity ions are implanted into the polycrystalline silicon layer 14 after the step (5) according to the relationship shown in FIG.

(bJ After step (6), the CVD 5iOt film 15 was formed, but the semiconductor substrate 1 was left with the gate oxide film 12 left.
A CVD-8 inch film 15 may be formed on the entire main surface. In this case, as shown by S in FIG. 8C, the oxide film 11 is
The step difference in the polycrystalline silicon layer 140 is not large, and CVD
-8 The adhesion state of the iO1 film 15 is good.

(cl CVD-8in) Instead of using an external deposition method like the film 15, the surface of the polycrystalline silicon layer 14 may be thermally oxidized, and the thermal oxide film formed on the polycrystalline silicon layer 14 may be used as a mask. Particularly in this case, since the side surfaces of the polycrystalline silicon layer can be sufficiently covered, introduction of impurities can be sufficiently prevented.

(di) Since the memory cell of the present invention forms a multilayer wiring, it is preferable to have a LOGO8 structure as shown in FIG. 4A, which allows for planarization. Examples of the LOCO8 structure will be described later.

tel The film to cover the polycrystalline silicon layer where the resistor is to be formed is not limited to CVD-8i ~ film, but also Si, N4
It may also be an insulating film.

Next, in a complementary MIS type semiconductor memory device, each memory cell is configured with a flip-flop using a high-resistance polycrystalline silicon layer as a load means and a single conductivity type MI 5FET as a switch means. An embodiment will be described in which a peripheral circuit is configured in a MIS type circuit.

FIG. 9 shows a basic circuit diagram using a CMIS (complementary MIS) circuit as a peripheral circuit.

1 is a memory cell, N-channel MISFETMa"
It is composed of Ma, and high resistance R,,R,. That is, an N-channel MISFETM.

and high resistance R8 constitute one inverter,
Another inverter is configured by the N-channel/I/MI8FETM and the high resistance R2. By cross-coupling these two inverters, seven lip-flops, which form the main part of the memory cell, are constructed.

M,,M, are P-channel MISFETs that constitute the precharge circuit PC, and serve as precharge transistors for dynamic operation.

M, ~M,. is the MI for configuring the sense amplifier SA.
SFET, M, , M, is P channel MI SF
E TMa = Mao is P channel/L'MISFE
It is T. Mll is P-channel MIS for switching
It is an FET.

A pair of data HA! +-1jt is the above sense amplifier SA
Although not shown, the line lI'+lt' is connected to the output of the data input circuit.

In this circuit, MISFETM, MI are turned on and off according to the low level and high level of the chip selection signal CE. M
When I SFE TM, , Me are turned on, a capacitor (not shown) attached to the data line 111-1t is charged. MISFET Ms1M4 is turned on by the high level of the word signal. When the clock signal φ becomes high level, the sense amplifier SA becomes MISFET
, I becomes operational by turning on.

When reading data from a memory cell, by setting the word signal to a high level while the chip selection signal CE is at a high level, the MI S FETMS 0M4 is turned on and the data line 1m-
The state of It is set.

Thereafter, the clock signal φ becomes high level, so that the sense amplifier SA becomes operable, and the sense amplifier SA performs an amplification operation in accordance with the state of the data line.

Data is written to the memory cell using data lines 1+ and lJ.
This is done by setting the word signal to high level while the state of t is set.

As mentioned above, CMIS type semiconductor memory device (Sem
(iconductor memory device)
In , an N-channel MISFET is used as the memory cell driving means, a high-resistance polysilicon is used instead of a P-channel MISFET as the load means, and the memory cell peripheral circuit is a normal CMIS type circuit. .

Next, such a CMIS type semiconductor memory device (Semiconductor)
A specific example consisting of an inductor memory device will be described below.

FIG. 10 is a block diagram of a 4-bit CMOS static RAM. In the figure, An~A1
1 is a terminal to which an external address signal is supplied, DIN
t DOllT are input and output terminals, W
E indicates a write enable signal terminal and CB indicates a write enable signal terminal. 50 to 61 are address buffer 1 circuit, 62 is an input buffer circuit, 63 is a write enable buffer circuit, 64 is a chip enable circuit, 65 is an output buffer circuit, 66 is an R8W decoder circuit, 67 is a clock generation circuit, 68 is a memory cell Matrix (memory)
cell matrix), 64 pieces in row, co
There are 64 cells in lumn. 69 is c
o 1 umn input circuit; 70 indicates a co 1 umn decoder circuit;

Next, each circuit section shown in FIG. 10 will be specifically explained.

FIG. 11 shows the row decoder circuit (ro decoder circuit) in FIG.
w decoder circuit) 66, ri07
clock generator circuit
cuit ) 67, memory cell matrix circuit (me
mory cell matrix circuit)
68, column input/output circuit and column decoder circuit (c
column decoder circuit) 70
FIG. In the figure, RD.

RD, . . . are column address decoder circuits (ro
waddress decoder circuit
), and is located in the center of the memory cell matrix, that is, between the 32nd and 33rd columns in order to speed up the process. LD,...LDt5. L.D.
t6 is a column address decoder circuit (column a
ddressdecoder circuit). From this column address decoder circuit, mutually true (
It outputs two address output signals: true (true) and false (bar). Therefore, from the LD, address output terminal Y
I-Yt, LDt to address output terminals Y,, Y4,
LD, , to address output terminal y2. ．． y30 and L
Address output terminals y, , f Y112 are drawn out from D, . These address output terminals are connected to decoder and driver circuits (D+ -Da -Dso, Da2
) are connected.

This decoder driver circuit outputs two address output signals. Therefore, 32 decoder driver circuits can select from 1st to 64th column address. And a5. Only one column is selected by the address control signal a5. S.A.

S Aa and S Ae+ -S Aag are sense amplifiers, which correspond to the sense amplifier SA in FIG. PC,
.

PCa, PCe+, and PCss are precharging circuits, and correspond to the precharging circuit PC constituted by precharging transistors M, . . . M6 in FIG. The N-channel MI SFETM2o corresponds to Mll in FIG. Same, P channel MISFETTM
, , are precharging transistors that hold the sense amplifier line SAL at a high level (■cc level) until the information is determined, and the sense amplifiers SA, , S
Aa = 5A61*5 Disable Aaa. In particular, if measures are taken to maintain the sense amplifier at a high level, external noise will not cause these sense amplifiers to operate. In the case of Fig. 9, MISFETMB
When is OFF, the junction J becomes floating, which makes it easy for noise to enter. Therefore, there is a possibility of operating in a state where the information of 11-1t is not determined.

Next, specific circuits for obtaining signals input to the circuit shown in FIG. 11 are shown in FIGS. 12 to 19.

Figure 12 shows the chip enable buffer r circuit 6 of Figure 10.
4, from the external chip enable signal CE to the internal signal CE, CE, CE2°CE8. Generate φM and X. Similarly, the state of the switch SW in FIG. 12 shows the state in which the signals shown in the figure are extracted from each output terminal when the chip enable signal CE is input.

Further, in order to extract the signals shown from each output terminal by inputting the chip enable signal CE, the state of the switch SW may be changed. Such switching of the switch SW is normally realized by slightly changing the wiring within the semiconductor integrated circuit using a known master slice technique.

FIG. 13 shows the write enable buffer circuit 6 of FIG.
3, the internal signals φlet WE and φW are generated from the external write enable signal WE. In this case as well, CE is the same as in FIG.

CE switching is performed by a master slice.

FIG. 14 shows the data-in buffer circuit 62 of FIG. 10, which generates internal data signals die and ain from an external data input signal I)tN.

FIG. 15 shows the address buffer circuits 51 to 5 of FIG.
4 and address signal A from the outside. ~A4 to internal address signal a. - a4 and a.

~a4 is generated.

FIG. 16 shows the address buffer circuit 55.5 of FIG.
6, internal address control signals a@, a@ and internal address signals a, , a@ are generated from an external address signal Aa=As, respectively.

FIG. 17 shows the address buffer circuits 57 to 6 of FIG.
1, and generates internal address signals a, -a11 and a7-all from external address signals 7-A11.

FIG. 18 shows a timing pulse generation circuit which uses internal address signals an to aIIs aQ all and internal signals CB to generate internal signals φ8. φXllφx2 is generated.

FIG. 19 shows a timing pulse generation circuit which generates internal signals φ, φA+A11+φM.

Generate φM.

External signals are generated as shown in the timing charts shown in FIGS. 20 to 22. In particular, Fig. 20 is a timing chart of a read cycle, and Fig. 21 is a timing chart of a write cycle.
cle) timing chart and Figure 22 shows read and write timing in one cycle.
20 to 22, tc is the cycle time,
tAC is access time, tc+e is chip enable width, t is chip enable precharge time, t4 is address hold time, tAB is address setup time, tOFF is output buffer delay time, tws
is write enable setup time, tDIH is input data retention time, tww is write enable width, tMOD is modify time, tWPL is WE-+C
E time, tDll is input data setup time, twH is write enable holding time, and tT is rise/fall time.

Next, the structural features of the above-mentioned CMIS type semiconductor device and its manufacturing method will be explained.

FIG. 23 is a sectional view of such a CMIS type semiconductor memory device.

103 is an N-type semiconductor substrate, 104 is a P-type semiconductor well,
105 is a thick Sin film, 106 is a gate insulating film, 10
7 is a polycrystalline silicon gate electrode; 108 is a polycrystalline silicon layer formed at the same time as the gate electrode;
, is masked by a CVD film 109 to prevent impurity doping in the core portion 108a, forming a high-resistance 'ai'. This polycrystalline silicon layer 108 is used as a high resistance material serving as a load means of the memory cell. 110
is the source of the P-channel MISFET, 111 is the drain of the P-channel MISFET, 112 is the source of the N-channel MISFET, and 113 is the P-channel MISF
ET drain, 114 is PSG for cleaning the surface
The membrane 115 is an aluminum electrode.

24A to 24J show the method of manufacturing such a semiconductor memory device in the order of steps.

(1) Oxidize the surface of the N+ type semiconductor substrate 103 to
S in the part where the film 105 is formed and the well is to be formed.
+Q, film 105 is removed by photoetching. Then, in this state, ions are implanted into the well. 116
is a photoresist film. (See FIG. 24A) (2) Next, a P-type semiconductor well 104 is formed by diffusing P-type impurities. (See Figure 24B) (3) Remove the Sin film 105 formed on the semiconductor surface, then thinly oxidize the surface to form an insulating film 118, and then apply the nitride (813N4) film 17 on the surface. After that, a photoresist film 116 is formed. Then, the nitride film 117 is photo-etched using the photoresist film 116 as a mask. (24th C
(See figure) (4) Apply a photoresist film 16 to areas other than the well portion. In this state, ions are implanted.

(See FIG. 24D) (5) In this state, an isolation film for element isolation is formed by selectively oxidizing the nitride film 117 as a mask, and further the nitride film 11 used as a mask is
Remove 7. Then, the back surface of the semiconductor substrate 103 is also etched. (See Figure 24E) (6) The semiconductor surface is thermally oxidized to form a gate insulating film 106.
Then, polycrystalline silicon layers 107 and 108 are formed. 307 constitutes a gate electrode, and 108 constitutes a high resistance element serving as a load means for the memory cell. Note that after forming the polycrystalline silicon layers 107 and 108, thin ions are implanted to control the specific resistance of the high resistance element to a constant value. (
(See Figure 24F) (7) Mask 11 on the semiconductor well part
form 9.

In this state, the source of the P-channel MISFET.

A window opening for drain diffusion is provided, and a P-type impurity is diffused through the window opening to form a source 110 and a drain 111. (See Figure 24G) (8) Remove the above mask, and conversely cover the P channel portion with mask 19. Note that at this time, a portion of the polycrystalline silicon layer 108 is also covered with a mask.

This is because it is necessary to prevent impurities from diffusing in order to maintain a high resistance state. (See FIG. 24H) In this state, window openings for source and drain diffusion are provided, and N-type impurities are diffused through the window openings to form the source 112 and drain 113.

(9) After that, a PSG film 114 is formed. This PSG
The film 114 is photoetched to form a window opening for electrode extraction. (See Figure 24I) After that, an aluminum electrode is formed. (See Figure 24J) The present invention has been described above based on specific examples.
According to the present invention, the following effects can be expected.

(al) The resistor of the high-resistance element made of polysilicon used as the load means has a high specific resistance, so it only requires an extremely small area. The current should be small enough to supply a minute current sufficient to replenish the leakage of charge.

For example, a resistance value of approximately IOGΩ may be used. Note that leakage is caused by a current flowing through a junction of parasitic capacitance and a tailing current flowing through a MISFET in an OFF state.

A small amount of current to supplement this is passed through a polycrystalline silicon high resistance material used as a load means to an information storage means (cap).
ac i tor) By flowing VC, Ce1l
Internally, it works using a static memory method that does not require periodic refresh.

On the other hand, outside the cell, the precharge circuit (
Dynamic operation of operating PC, PC, , PC, . . . ) is possible. Of course, it is not always necessary to use a precharge circuit for clock driving, and static operation may be performed. Even in this case, a static memory type semiconductor memory cell having a cell area approximately equal to that of a flip 7 four-tub type memory cell made of a dynamic type 4M08FET can be obtained.

Incidentally, the cell area of the present invention is 0.38 in terms of area ratio compared to a flip-flop memory cell/l/ (6M OS-memoryCell) consisting of a static memory type 6M08FET using an enhancement type MO8FET as a load means. becomes extremely small. In addition, compared to a 6M0S memory cell using a depletion type MO8FET as a load means, which is known to be able to reduce the cell area, the cell area of the present invention is
1 liter can be made smaller at 0.65. Furthermore, when compared with a 0MO8 type memory cell, the area ratio of the present invention is extremely small at 0.31. In particular, 0MO
In the case of an 8-type memory cell, a gap above a certain level must be provided between the P-channel MO8FET and the N-channel MO8FET in order to interpose a well junction, and this has been a major cause of lowering the degree of integration. However, according to the present invention, 10,000 channel type MISFE circuits out of complementary MIS type circuits are used as memory cells.
Since only the T is used and the other channel type MISFET is not used, it is not necessary to leave a wide gap between the MISFET elements, so high integration can be achieved.

(bl) Only a small amount of current flows through the polycrystalline silicon high resistance material that is the load means, and it can be refreshed sufficiently, so the power consumption can be almost the same as that of complementary MIS memory.Of course, there is a circuit for refreshing. is also no longer necessary.

10,000, Complementary MIS type circuits are used for peripheral circuits, and the characteristics of complementary MIS type circuits can be fully utilized.

(C) Since the polycrystalline silicon layer constituting the load means and the polycrystalline silicon layer for applying the power supply voltage to the load means can be integrally formed, a special region for contacting the two is required. This makes it unnecessary, and the area occupied by the contact region can be reduced.

That is, in a memory matrix (memory array) made up of a plurality of memory cells, a power supply voltage line and a load means are formed of an integrated polycrystalline silicon layer, and the power supply voltage line and a pad made of aluminum wiring are memory matrix
y matrix ) is connected outside. Therefore, the number of connection points (the number of contacts) is extremely small.

This point is not limited to the above-mentioned memory cells, but includes load means connected to the terminal to which the power supply voltage is applied and a ground terminal.
The present invention can be applied to general semiconductor devices using an inverter element consisting of driver means connected to both terminals.

[Brief explanation of drawings]

FIG. 1 is a layout diagram of a semiconductor memory device showing one embodiment of the present invention. FIG. 2 is a circuit diagram of the semiconductor memory device shown in FIG. 1. FIG. 3 is a layout diagram in which four semiconductor memory devices of FIG. 1 are arranged. 4A and 4B are cross-sectional views showing the MISFET section and the load resistance section, respectively. FIGS. 5A and 5B are correlation diagrams between the current required to retain information and the voltage used in a semiconductor memory device. FIG. 6 is a correlation diagram between the amount of impurity implanted into polycrystalline silicon and the resistance. 7A to 7E are plan views showing manufacturing steps for obtaining the semiconductor memory device shown in FIG. 1. FIG. Figures 8 to 8E are cross-sectional views of Figures 7A to 7E, respectively. FIG. 8A is a sectional view taken along the line A-A' of FIG. 7A. FIG. 8B is a sectional view taken along line BB' in FIG. 7B. FIG. 8C is a sectional view taken along line c-c' of FIG. 7C. FIG. 8D is a sectional view taken along b-ry of FIG. 7D. FIG. 8E is a sectional view taken along the line E-E' of FIG. 7E. FIG. 9 is a circuit diagram showing another embodiment of the present invention, in which a peripheral circuit includes a complementary MISFET (hereinafter referred to as
2 is a circuit diagram using a circuit (referred to as CMIS). FIG. 10 is a block diagram of a 4-bit CMIS 5tatic RAM. FIG. 11 is a circuit diagram showing another embodiment of the present invention, and shows the specific circuit diagram of FIG. 10 shown in a block diagram. FIG. 12 is a chip enable buffer circuit diagram used in the circuit shown in FIG. 11. FIG. 13 is a write enable buffer circuit diagram used in the circuit shown in FIG. 11. FIG. 14 is a data in buffer circuit diagram used in the circuit shown in FIG. 11. FIG. 15 shows an external address signal A used in the circuit shown in FIG. From A4
FIG. 3 is an address buffer circuit diagram for buffering up to FIG. 16 is an address buffer circuit diagram for buffering the external address signal An=A6 used in the circuit shown in FIG. 11. FIG. 17 is an address buffer circuit diagram for buffering external address signals A to AII used in the circuit shown in FIG. 11. FIG. 18 is a timing pulse generation circuit diagram used in the circuit shown in FIG. 11. FIG. 19 is a timing generation circuit diagram similarly used in the circuit shown in FIG. 11. Figure 20 shows the read cycle.
cle) is a timing chart. FIG. 21 is a timing chart of a write cycle. Figure 22 shows read (re) in one cycle.
3 is a timing chart when performing an ad) and a write. FIG. 23 is a cross-sectional view of a CMI 5 type semiconductor memory device. 24th A to 24th
FIG. J is a cross-sectional view showing the manufacturing method for obtaining the semiconductor device shown in FIG. 23 in order of steps. 1... Diffusion layer, 2... Low resistance polycrystalline silicon layer, 3
... High resistance polycrystalline silicon layer, 9... Semiconductor substrate,
Q+ -Q-...Drive FET, Qs, Q4.
...Transmission FBT, R,,R,...Load resistance. Figure 5B Figure Seal Sword mouth arm 1 Figure 24q Figure 24/-/

Claims (1)

[Scope of Claims] 1. An integrated circuit memory device in which a large number of memory cells are arranged in a matrix, comprising: (a) a first power supply wiring layer extending on a straight line (fi); First and second memory cells provided on both sides of the first power supply wiring layer (C1) are connected to the first power supply wiring and the first power supply wiring to supply power to the first and second memory cells. a second power supply wiring layer (61) provided on both sides of the second power supply wiring layer and a second data line (61 at one end) for transmitting complementary signals provided on both sides of the second power supply wiring layer substantially parallel thereto; are connected to the first and second data lines, respectively, and the other ends are connected to the first memory cells, respectively; third and fourth switch means (gl connected to the control terminals of the first and second switch means), the other ends of which are connected to the second data line of the second memory cell; or a first word line provided on both sides of the integrated first power supply wiring layer substantially parallel thereto (hl connected to the control terminals of the third and fourth switch means, or integrated with the first word line); An integrated circuit memory device comprising second word lines provided on both sides of the first power supply wiring layer substantially parallel to the first power supply wiring layer. 2. At least one of the peripheral circuits corresponding to the plurality of memory cells. 3. The integrated circuit memory device described in the patent, characterized in that the second power supply wiring layer and the first and second data lines include metal members. The integrated circuit memory device according to claim 1 or 2. 4. Claim 1, wherein the first power wiring layer is made of a member containing polycrystalline Si. 5. The integrated circuit memory device according to any one of clauses 3 to 5. 5. The integrated circuit memory device according to any one of clauses 1 to 3, wherein the first and second word lines are made of a member containing polycrystalline Si. An integrated circuit memory device according to any one of clauses 4.