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JPS6077278A - Discriminating circuit of character entry area - Google Patents

Discriminating circuit of character entry area

Info

Publication number
JPS6077278A
JPS6077278A JP58186162A JP18616283A JPS6077278A JP S6077278 A JPS6077278 A JP S6077278A JP 58186162 A JP58186162 A JP 58186162A JP 18616283 A JP18616283 A JP 18616283A JP S6077278 A JPS6077278 A JP S6077278A
Authority
JP
Japan
Prior art keywords
character
area
black
circuit
memory
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP58186162A
Other languages
Japanese (ja)
Inventor
Yuji Isobe
磯部 祐司
Kiyokazu Hanatani
花谷 清和
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP58186162A priority Critical patent/JPS6077278A/en
Publication of JPS6077278A publication Critical patent/JPS6077278A/en
Pending legal-status Critical Current

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  • Character Input (AREA)

Abstract

PURPOSE:To omit the storage and discrimination of character entry information every business form by scanning binary picture data by a window having double frames, discriminating and storing the number of black picture elements in an area separated by the frames and controlling the segmentation of a character pattern by the output of the stored contents. CONSTITUTION:An observation part 1 has plural CCD conversion elements arrayed straight and the business form is read out by regarding the arrayed direction as the main scanning direction to observe the density of each unit area. The output of the observation part 1 is binary-coded by white and black elements in a binary coding circuit 2 and the picture is scanned 3 by the double-frame window constituted by the inner and outer frames having prescribed size and the number of black elements in each area separated by frames is detected 4. The character entry area on the business form is discriminated 5 by the number of detected black picture elements and the contents are stored in a memory 6. A segmenting circuit 8 segments and outputs a character pattern stored in a memory 7 as one character under control by the output of the memory 6.

Description

【発明の詳細な説明】 −(a)発明の技術分野 本発明は文字認識装置、特にフリーフォーマット帳票に
記入された文字の読取りに用いる文字認識装置に関する
DETAILED DESCRIPTION OF THE INVENTION - (a) Technical Field of the Invention The present invention relates to a character recognition device, and particularly to a character recognition device used for reading characters written on free format forms.

(1))技術の背景 欠字認識装置は、帳票」二に手書きあるいは印刷によっ
て記入された文字パターンを読み取り、これをパターン
認識技法によって認識する装置であるが1通常、いった
ん1行分の文字パターンを読み取うたあと、順次その中
から1文字分ずつの文字パターンを取り出しく文字の切
り出しと称する)1文字毎に認識を行っている。
(1)) Background of the technology A missing character recognition device is a device that reads a character pattern written by hand or print on a form and recognizes it using pattern recognition techniques. After reading the pattern, character patterns for each character are sequentially extracted from the pattern (referred to as character extraction), and recognition is performed for each character.

前記文字の切り出しを容昌にするため、これまでの多く
の文字認識装置においては、たとえば文字認識装置が検
出できない色彩のインクによって1文字毎に文字記入枠
を指定した帳票、あるいは文字記入行を指定した帳票を
用いている。
In order to accurately cut out the characters, many conventional character recognition devices use, for example, a form in which a character entry frame is specified for each character using ink of a color that cannot be detected by the character recognition device, or a character entry line is The specified form is being used.

(C)従来技術と問題点 前記のように、従来の欠字認識装置は文字記入枠等を指
定した帳票を用いるようになっているが。
(C) Prior Art and Problems As mentioned above, conventional missing character recognition devices use forms in which character entry frames and the like are specified.

帳票の種類によって文字記入枠等の位置が異なるので1
文字認識装置に対し帳票の種別を知らせる必要がある。
The position of the text entry frame etc. differs depending on the type of form, so 1.
It is necessary to inform the character recognition device of the type of form.

一方2文字認識装置は帳票の種別毎に帳票」二の文字記
入枠の位置等の文字記入情報を予め記憶しておく必要が
ある。
On the other hand, the two-character recognition device needs to store in advance character entry information such as the position of the character entry frame for each type of form.

前記帳票の種別は各帳票上の右上隅等に識別記号を印刷
することによって標示し2文字認識装置はこれを認識す
ることによって帳票の種別を識別し、予め記憶する帳票
毎の文字記入情報に基づいて文字パターンの切り出しを
行っていた。
The type of the form is indicated by printing an identification symbol on the upper right corner of each form, and the two-character recognition device identifies the type of form by recognizing this, and inputs the pre-stored character entry information for each form. Based on this, character patterns were extracted.

ところが1文字認識装置を利用する業務の増加と共に帳
票の種類が非電に増大し、これに伴ゲで前記帳票の種別
毎の文字記入情報の記憶等の処理が煩5jlFになると
いう問題が生じていた。
However, as the number of businesses that use single-character recognition devices increases, the number of types of forms increases, and as a result, a problem arises in that processing such as storing character entry information for each type of form becomes cumbersome. was.

(d)発明の目的 本発明の目的は、帳票毎の文字記入情報の記憶および帳
票の種別の識別を必要としない文字認識装置を提供する
ことにある。
(d) Object of the Invention An object of the present invention is to provide a character recognition device that does not require storing character entry information for each form and identifying the type of form.

(e)発明の構成 本発明になる文字記入領域判別回路は、方眼状に配列さ
れる画素毎に黒画素と白画素との何れかの241ifデ
ータとして表される画像を所定寸法の二重枠のウィンド
ーによって走査する走査回路と。
(e) Structure of the Invention The character writing area discriminating circuit according to the present invention is capable of dividing an image expressed as 241if data of either a black pixel or a white pixel for each pixel arranged in a grid shape into a double frame of a predetermined size. and a scanning circuit for scanning by a window.

前記ウィン1−の内枠と外枠とによって区切られる各領
域内の黒画素の数を検出する検出回路と。
a detection circuit for detecting the number of black pixels in each area divided by the inner frame and the outer frame of the window 1-;

前記検出回路によって得られる前記各領域内の黒画素の
数によって帳票−1−の文字記入領域を識別する識別回
路とを備えるものである。
and an identification circuit that identifies the character entry area of the form-1- based on the number of black pixels in each area obtained by the detection circuit.

(f)発明の実施例 以下・本発明の要旨を実施例によって具体的に説明する
(f) Examples of the Invention The gist of the present invention will be specifically explained by examples.

第1図は本発明一実施例の構成を示ずブロック図であり
、1は直線状に配列される2048個のCCD変換素子
を有し、その配列方向を主走査方向として帳票をラスク
走査によって読み取り、帳票上の方眼状に配列される0
、1■平方の画素毎の濃度を観測する観測部、2は観測
部1によって得られる前記画素毎の濃度を2値化し黒画
素と白ii!I素との何れかによって表す2値化回路、
:3は2値化回路2によって2値データとして得られる
画像を所定寸法の内枠と外枠とを備える二重枠のウィン
l” −によって走査する走査回路、4は前記ウィンド
ーの内枠と外枠とによって区切られる各領域内の黒画素
の数を検出する検出回路、5は検出回路4によって得ら
れる前記各領域内の黒画素の数によって帳票上の文字記
入領域を識別する識別回路、6(ハ:′1(別回路5に
よって得られた識別を記憶するメモリ、7は2(11“
I北回路2によって得られた2値F!111g+データ
を格納するメモリ、8は2値画像データとしてメモリ7
に記憶する文字パターンを1文字分ずつりノリ出して出
力する切出し回路である。
FIG. 1 is a block diagram, not showing the configuration, of an embodiment of the present invention, in which 1 has 2048 CCD conversion elements arranged in a straight line, and a form is scanned by rask scanning with the arrangement direction being the main scanning direction. Read and 0 arranged in a grid on the form
, 1 ■ Observation section that observes the density of each pixel of square, 2 binarizes the density of each pixel obtained by the observation section 1 and divides it into black pixel and white ii! A binarization circuit represented by either I element,
: 3 is a scanning circuit that scans the image obtained as binary data by the binarization circuit 2 using a double frame window l''- having an inner frame and an outer frame of predetermined dimensions; 4 is a scanning circuit that scans the image obtained as binary data by the binarization circuit 2; a detection circuit that detects the number of black pixels in each area delimited by the outer frame; 5 an identification circuit that identifies a character entry area on the form based on the number of black pixels in each area obtained by the detection circuit 4; 6(c:'1(memory for storing the identification obtained by another circuit 5, 7 is 2(11"
Binary F obtained by I north circuit 2! 111g + memory for storing data, 8 is memory 7 as binary image data
This is a cutting circuit that extracts and outputs the character pattern stored in the memory one character at a time.

、[森回路:3は、第2図に示すように直列接続される
Y1固のXピノ1−のシフトレジスタ9とY(固の<2
048−X)ビットのシフトメモIJIOとからなる記
1.Q部、および7個のXピッ[・のシフトレジスタ9
に対応して設けられ第3図に示すように外枠が(xxy
)ビ・ノドで内枠がC(X−2d) X (Y−2d)
 )ビットの二重枠のりイン1−”−によって構成され
 q (、、l、:北回(洛2の出力は1ビ、21・ず
つNo、1のシフトレジスク10に矢印へのように入力
される。
, [Mori circuit: 3 is the shift register 9 of the X pino 1- of the Y1 fixed and the Y (<2 of the fixed
048-X) Bit shift memory IJIO and 1. Q part, and shift register 9 of 7 X pins [・
As shown in Figure 3, the outer frame is (xxy
) Bi-nod and the inner frame is C (X-2d) X (Y-2d)
) bit double frame paste-in 1-”- is configured by q (,,l,:northern (Raku 2 output is input to the shift register 10 of 1 bit, 21, 1 by No. 1 as shown by the arrow) Ru.

なお、×・Yおよびdの値は帳票に記入する文字の寸法
および間隔によって予め決定する。
Note that the values of ×Y and d are determined in advance based on the size and spacing of characters to be written on the form.

検出回1洛4は第一の検出回路4−1と第二の検出回路
4−2からなり、第一の検出回路4−1は二重枠−ウィ
ン1−一のハツチングを施した領域(第3図参照)しに
対応するシフトレジスタ9上の黒画素(” 1 ” )
の数を検出し、第二の検出rIjl路4−2は二重枠ウ
ィンドーの内枠領域Mに対応するシフトレジスタ9上の
黒画素(2値デーク“1”)の数を検出する。
Detection circuit 14 consists of a first detection circuit 4-1 and a second detection circuit 4-2, and the first detection circuit 4-1 has a double frame-win 1-1 hatched area ( The black pixel (“1”) on the shift register 9 corresponding to
The second detection rIjl path 4-2 detects the number of black pixels (binary data "1") on the shift register 9 corresponding to the inner frame area M of the double frame window.

識別回路5ば 1、領域りおよび領域Mに対応するシフトレジスタ9上
に5焦1iJi素が全く検出されない場合には。
If no 5-focus 1iJi element is detected on the shift register 9 corresponding to the identification circuit 5b1, area 1, and area M.

帳票上の当該領域には文字が記入されていないものと判
断する。
It is determined that no characters are written in the area on the form.

11、領域りおよび領域Mに対応するシフ1−レジスタ
91の何れにも黒画素が検出され、且つ領域Mに対応す
るシフ1〜レジスタ9上の黒画素数が所定数α未満の場
合には、これを゛ごめ°゛ (ノイズ)であると判11
J1する。
11. If a black pixel is detected in any of the shift 1 registers 91 corresponding to the area M and the number of black pixels on the shift 1 registers 91 corresponding to the area M is less than the predetermined number α, , this is judged to be ゛gome°゛ (noise)11
Play J1.

iii 、 ’jQ’j 15 Lおよび領域Mに対応
するシフトレジスタ9上の何れにも黒画素が検出され、
且つ領域Mに対応するシフトレジスク9」二の黒画素数
が所定数α以」二の場合には、帳票上の当該領域を文字
記入領域として識別する。
iii, 'jQ'j 15 A black pixel is detected on any of the shift registers 9 corresponding to L and area M,
In addition, if the number of black pixels of the shift register 9'2 corresponding to the area M is equal to or greater than the predetermined number α, the area on the form is identified as a character entry area.

iv、領域りに対応するシフ1〜レジスタ9上には黒画
素が検出されず、領域Mに対応するシフトレンスタ9.
にに所定数α未満の黒i+qi素が検出される場合には
、ごれを″ごみ′であると判断する。
iv, no black pixels are detected on the shift registers 9 to 9 corresponding to the area M, and no black pixels are detected on the shift registers 9 to 9 corresponding to the area M.
If less than a predetermined number α of black i+qi elements are detected, the dirt is determined to be "dust."

V 領域1.に対応するシフ1−レジスタ9上には黒画
素が検出されず、領域Mに対応するシフ)−レノン、り
91−に所定数αツ」二の黒p111素が検出される場
合には、帳票−にの当該領域を1文字分の文字記入領域
として識別する。
V area 1. If no black pixel is detected on the shift register 9 corresponding to the area M, and a predetermined number of black p111 pixels are detected on the shift register 9 corresponding to the area M, The corresponding area on the form is identified as a character entry area for one character.

識別回路5による前記111およびyの識別はメモリ6
に記1aされ、切出し回路8は2値画像データとしてメ
モリ7に記taされている文字パターンをメモリ6に記
1.aする識別にしたかって1文字分ずつりJ2′)出
して認識部(図示省1■偵乙こ出力する。
The identification of 111 and y by the identification circuit 5 is performed by the memory 6.
1a, and the extraction circuit 8 records the character pattern recorded in the memory 7 as binary image data in the memory 6. If you want to make an identification, one character at a time is output (J2') and outputted to the recognition section (1).

(g)発明の詳細 な説明したように1本発明によれば、フリーフォーマノ
1〜帳票を用いることによって、帳票毎の文字証人情報
の記憶および帳票の種別の識別をノビ・要としないとい
う効果がある。
(g) Detailed Description of the Invention According to the present invention, by using free-form mano 1 to forms, it is not necessary to memorize character witness information for each form and to identify the type of form. effective.

【図面の簡単な説明】[Brief explanation of drawings]

第1図は本発明−実施例のブ1:1ツク図、第2図およ
び第3図は走査回路の説明図である。 図中、2は2値化回路、3は走査回路、4は検出回路、
5は識別回路である。
FIG. 1 is a block diagram of an embodiment of the present invention, and FIGS. 2 and 3 are explanatory diagrams of a scanning circuit. In the figure, 2 is a binarization circuit, 3 is a scanning circuit, 4 is a detection circuit,
5 is an identification circuit.

Claims (1)

【特許請求の範囲】[Claims] 方眼状に配列される画素毎に黒画素と白画素との何れか
の2値データとして表される画像を所定寸法の二重枠の
ウィンドーによって走査する走査回路と、前記ウィンド
ーの内枠と外枠とによって区切られる各領域内の黒画素
の数を検出する検出回路と、前記検出回路によって得ら
れる前記各領域内の黒画素の数によって帳票上の文字記
入領域を識別する識別回路とを備えることを特徴とする
文字記入領域判別回路。
A scanning circuit that scans an image expressed as binary data of either a black pixel or a white pixel for each pixel arranged in a grid pattern using a double frame window of a predetermined size, and an inner frame and an outer frame of the window. a detection circuit that detects the number of black pixels in each area separated by a frame; and an identification circuit that identifies a character entry area on the form based on the number of black pixels in each area obtained by the detection circuit. A character entry area discriminating circuit characterized by the following.
JP58186162A 1983-10-05 1983-10-05 Discriminating circuit of character entry area Pending JPS6077278A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP58186162A JPS6077278A (en) 1983-10-05 1983-10-05 Discriminating circuit of character entry area

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP58186162A JPS6077278A (en) 1983-10-05 1983-10-05 Discriminating circuit of character entry area

Publications (1)

Publication Number Publication Date
JPS6077278A true JPS6077278A (en) 1985-05-01

Family

ID=16183468

Family Applications (1)

Application Number Title Priority Date Filing Date
JP58186162A Pending JPS6077278A (en) 1983-10-05 1983-10-05 Discriminating circuit of character entry area

Country Status (1)

Country Link
JP (1) JPS6077278A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5048096A (en) * 1989-12-01 1991-09-10 Eastman Kodak Company Bi-tonal image non-text matter removal with run length and connected component analysis
US7894683B2 (en) 2004-04-30 2011-02-22 Xerox Corporation Reformatting binary image data to generate smaller compressed image data size

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5048096A (en) * 1989-12-01 1991-09-10 Eastman Kodak Company Bi-tonal image non-text matter removal with run length and connected component analysis
US7894683B2 (en) 2004-04-30 2011-02-22 Xerox Corporation Reformatting binary image data to generate smaller compressed image data size

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