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JPS6066830A - Manufacture of semiconductor device - Google Patents

Manufacture of semiconductor device

Info

Publication number
JPS6066830A
JPS6066830A JP58175794A JP17579483A JPS6066830A JP S6066830 A JPS6066830 A JP S6066830A JP 58175794 A JP58175794 A JP 58175794A JP 17579483 A JP17579483 A JP 17579483A JP S6066830 A JPS6066830 A JP S6066830A
Authority
JP
Japan
Prior art keywords
film
wafer
back surface
insulating film
semiconductor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP58175794A
Other languages
Japanese (ja)
Other versions
JPH0342507B2 (en
Inventor
Susumu Ichinose
一瀬 進
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Renesas Semiconductor Manufacturing Co Ltd
Kansai Nippon Electric Co Ltd
Original Assignee
Renesas Semiconductor Manufacturing Co Ltd
Kansai Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Renesas Semiconductor Manufacturing Co Ltd, Kansai Nippon Electric Co Ltd filed Critical Renesas Semiconductor Manufacturing Co Ltd
Priority to JP58175794A priority Critical patent/JPS6066830A/en
Publication of JPS6066830A publication Critical patent/JPS6066830A/en
Publication of JPH0342507B2 publication Critical patent/JPH0342507B2/ja
Granted legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Dicing (AREA)

Abstract

PURPOSE:To prevent the improper avec even if the metal layer on the back surface of a wafer is soft with small size of an element by providing a hard insulating film at the position corresponding to dicing position on the back surface of the wafer. CONSTITUTION:SiO2 films 8, 9 are formed on the front and back surfaces of N<+>N<-> type Si wafer 1, a window is opened only at the film 8 to form a P type layer, thereby forming many elements 2. electrode windows 10 are opened at the films 8, and the film 9 is allowed to selectively remain at the position corresponding to that between the elements 2. Au film 3 is deposited on the front surface, and an Au film 4a and an Ag film 4b are deposited and laminated on the back surface. A bonding tape is bonded and exfoliated, and the Au 3, 4a are selectively removed on the films 8, 9. Further, a bonding tape 5 is bonded to the back surface, it is diced from the front surface to form grooves 6, and 60 8mum are allowed to remain. The wafer 1 is disposed downside, and a rubber plate is placed on the wafer, it is broken at 11 from the bottom of the groove to the film 9 of the back surface by a roller to isolate into elements 2. According to this method, the film 9 can be readily and accurately broken to eliminate the improper avec.

Description

【発明の詳細な説明】 1女雨分野 この発明は半導体装置の製造方法に関し、より詳しく社
半導体ウェーハから多数の半導体ベレット全製造する方
法に関する。
DETAILED DESCRIPTION OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and more particularly to a method for manufacturing a large number of semiconductor pellets from a semiconductor wafer.

背景技術 トランジスタ、ダイオード等の−1へ心外装置1′1を
: ij+jl造する場合、第1図に示1ように、一枚
の丁尊体ウェーハlに多数の半導体素子2全形成し1.
ノ、四面に金属層3,4全形成したのち、各半導体素子
2.2間全切断分離して、多数の半導体ベレット全製造
する工程全経て製造する。こ\で、−1ζ間の金属層3
は各半導体素子2毎に独立しているか、裏面の釜属層4
は一様に形成されており連Ji+i: していることが
多い。また、各半導体素子2,2間に一切…1する場曾
、一般にダインレグ法によることか多い。ところが、層
間の釜属層4が銀等の11すζ質のものである場合、グ
インングソウで完/1zカットしようとすると・軟質の
銀がダインングブレードに目詰りして、ダイン〉・グが
不[J■能になる。この/こめ、第2図に示すように、
半導体ウェーハ]の裏ωJvc接層テープ5全貼リイ」
け、半導体つJ−−ノ・〕’−) 8 [tjから所定
の残り代tk設けてダイシング溝6全形成した後、半導
体ウェーハlに撓屈力全作多敗の、′i′−導体ペレッ
トに製造している。しかしながら、半導体女子2 +/
)寸法がl as”以下の小型のもσ)では、半導体ウ
ェーハlに大きな撓屈万全作用させることかできないこ
と、および裏[1’lJの金属に’i 4が1吠質であ
るために、イホ実にブレーキングが行なえず、俵故個の
半導体ペレットが金属層4で連結状態になった。いわゆ
るアベック不良が発生[〜やすかった。
BACKGROUND TECHNOLOGY When manufacturing extra-core devices 1'1 such as transistors, diodes, etc., as shown in FIG. ..
After fully forming the metal layers 3 and 4 on all four sides, each semiconductor element 2.2 is completely cut and separated, and a large number of semiconductor pellets are manufactured through the entire process. Here, the metal layer 3 between -1ζ
Is it independent for each semiconductor element 2, or is it independent for each semiconductor element 2?
are uniformly formed and often form a series Ji+i:. In addition, when there is no connection between the semiconductor elements 2, 2, the dyne leg method is generally used. However, if the metal layer 4 between the layers is made of 11-metal material such as silver, when you try to make a complete/1z cut with a cutting saw, the soft silver will clog the cutting blade, causing the cutting blade to be cut. Become incapacitated. As shown in Figure 2,
Apply all ωJvc adhesive tape 5 to the back of the semiconductor wafer.
After forming the entire dicing groove 6 with a predetermined remaining thickness tk from tj, the semiconductor wafer l is given a bending force, and the 'i'-conductor pellet is Manufactured. However, semiconductor girls 2 +/
) With dimensions smaller than l as'', it is impossible to apply a large bending effect to the semiconductor wafer l, and because 'i 4 is 1 barred in the metal on the back [1'lJ] However, the braking could not be properly performed, and the semiconductor pellets that had fallen into the bale became connected by the metal layer 4. So-called Abek failure occurred [~] easily.

’;C′:+υ■の1.iiJ示 〔1ゴ IIリ 〕 この光明け、千事体素子の寸法が小さくかっ裏It’l
+の〈1>属A’Zが銀箔の軟實拐料よりなる場合であ
つでもアヘ゛ソク不艮企生じない半導体装置の製造方法
′Xセ提供することをt=I I」’Jとする。
';C':+υ■1. II
It is assumed that t=II''J provides a method for manufacturing a semiconductor device which does not cause problems even when the <1> group A'Z of + is made of a soft conductive material of silver foil.

1’ 4if;成〕 こU)51′:明Qユ、半導体ウェーハil′c多液の
半導体素子?形成する工程と、半導体ウェーへの裏面の
IS半尊体素子間に対応する位置に絶縁1換?杉成する
工程と、半導体ウェーハの裏面の1)IJ記絶Aid 
II・超Iツ成部分以外に軟質金属層全形成する下+1
+1と、’l” 34;f f4<ウェー・・全前記絶
縁膜に’AI’ I+j;する位置からゲrンングする
工程と全zむことk ’4、+徴とするもい−(’ ;
c’・る。
1'4if;Ni U) 51': Ming Q Yu, semiconductor wafer il'c multi-liquid semiconductor device? Is there an insulation layer at a position corresponding to the forming process and between the IS half-solid elements on the back side of the semiconductor wafer? 1) IJ recording aid on the back side of the semiconductor wafer
Bottom+1 where the entire soft metal layer is formed except for the II/super I component part
+1 and 'l'34;ff4<way...The process of irradiating the entire insulating film from the position where 'AI'I+j;
c'・ru.

〔効果〕〔effect〕

この発明は、半導体ウェーハの裏面σ)ダインジグ対応
位置に硬質の絶縁膜7有するから、゛I′導体ウェーハ
をハーフカットしてブレーキングする場合に、1111
記絶縁膜が確実に破断するし、’l’ 16体つ工−ハ
全ダイシング法で完全カットしても、グイシンクフレー
ドのI3詰り7生しることlぐ(il+実にダイシング
できる。
This invention has a hard insulating film 7 on the back surface of the semiconductor wafer at a position corresponding to the die jig.
The insulating film will definitely break, and even if it is completely cut using the full dicing method, the I3 clogging of Guissinkfred will occur.

発明全実施するための11シ良の形態 以下に、この発明の実施例7図向全参114シて+i(
(’。
The following is a detailed description of 11 forms for carrying out the entire invention.
('.

明する。I will clarify.

第4図ないし第9図はこの発明による方法の各段階にお
ける半導体ウェーハの断面図を示ず、。
4 to 9 do not show cross-sectional views of the semiconductor wafer at each stage of the method according to the invention.

まずロ+I+N−半導体ウニー・S l ’fc用意し
、表裏両1flj K (冥11−膜等の絶縁膜8,9
全形成し、表面側の花A、’、! +1位、3のみに窓
3′1.全形威し、N−型領域内にP型イく純1(?り
を・i)仕III< 11八敗してP種領域に形成する
ことにより、多液の゛1′1体感イ2?形成する(第4
図9゜次に、周知のフォトエツチング法によって、表+
1+1ttlllの絶祷膜8にオーミック接触用の悪孔
10全形成するとともに、裏面の絶縁膜9全前記各半導
1本7□F2,2間に対応する位置のみに残す(第5図
)0 続いて・表10ノの絶縁膜8上および惑乱10に含むr
i= +1+ノl’c 8ン全蒸A”4して金属層3に
形成するととも&c、、9↓聞σ、)絶縁j摸9上を含
む全面に、金全蒸漸して釜層4 a 2 II醤成し、
さらにこの釜層4a上に銀を・7/> y7j Lでi
長潮41)全れIi曽することによって金属j・;・1
4全jし成する(第6図)。
First, prepare a + I + N - semiconductor unit S l 'fc, and coat both the front and back sides with insulating films 8, 9 such as
Fully formed, flower A on the surface side, ',! +1st place, window 3'1 only for 3. By forming a pure 1 (?riwo・i) class III < 118 and forming in the P type region, the P type is formed in the N- type region, resulting in a multi-liquid ``1'1 experience''. 2? form (fourth
Figure 9゜Next, the table +
All holes 10 for ohmic contact are formed in the 1+1ttll film 8, and the entire insulating film 9 on the back side is left only at the position corresponding to each of the semiconductors 7□F2 and 2 (Figure 5)0 Subsequently, r included on the insulating film 8 and in the confusion 10 in Table 10
i=+1+ノl'c 8-all vaporized A"4 to form metal layer 3 &c,, 9↓minσ,) Insulation j All-vaporized gold layer is formed on the entire surface including the upper surface 4 a 2 II seasoning,
Furthermore, silver is added on this pot layer 4a by 7/> y7j L and i
Long tide 41) Metal j・;・1 by all Ii
4 Complete all the steps (Figure 6).

次に、rl’導体ウェーハ1の表裏両面に接着テープに
貼り1・]け/このち剥離することにより、金属1・ご
3お・よび<lントjI4.Lのシリコンと絶縁膜8,
9上の1、1.・、ノ■ の ン’< ”5− A:I
I Iff l−で 、1tr+ r* la 8 −
 Q l σ]4孝B b2i3および金層4ak剥離
除去し、絶縁膜8σ):さこ孔10および絶縁膜9,9
間部分に、〈12 kJ’、 l胃3」Sよび4全形成
する(第7図)1、 きしに、半導体ウェー、・\1の裏[川(′C]メツ?
、iデー15全貼り(Jけて・表JJ“I)側から各半
導体素f2,2間&lS分?グイシンゲして、残り代が
60〜801ノ程度のダイシング溝6全形成する(第8
1文1)。
Next, by pasting adhesive tape on both the front and back sides of the rl' conductor wafer 1 and then peeling it off, the metals 1, 3, and 4. L silicon and insulating film 8,
1, 1 on 9.・、ノ■のの´< ”5− A:I
I If l-, 1tr+ r* la 8-
Q l σ]4 Takashi B b2i3 and gold layer 4ak peeled off, insulating film 8σ): hole 10 and insulating films 9, 9
In the middle part, 〈12 kJ', l stomach 3''S and 4 are completely formed (Fig. 7) 1, the semiconductor wafer, and the back of \1 [river ('C]metsu?
, from the i-day 15 complete pasting (JKET/Table JJ "I) side, dicing grooves 6 between each semiconductor element f2 and 2 &lS? are formed with a remaining thickness of about 60 to 801" (8th
1 sentence 1).

この半導体ウェーハ1とト側(t(してゴム板部の上V
c1或せ、m Nテープ5の−I−から%’li製ロー
クローラせず)全転動させて、)1′韓体つ、L−ハ]
に撓屈万全1′β用せしめ、ダイジングrf<f 6 
(/用氏r?lsからソJ 1fllσ〕絶縁膜9にか
けて破ill「l 1 k生じさせて、谷゛1′導体六
子2毎に分1〜1Fする(第9図)。
This semiconductor wafer 1 and
c1, m N tape 5 -I- to %'li low crawler) fully rolled,) 1' Korean body one, L-ha]
The bending is perfect for 1'β, and the dicing rf<f 6
(/R?ls to SOJ 1fllσ) A rupture is caused across the insulating film 9, and 1 to 1F is generated for each valley 1' of the conductor hexagon 2 (FIG. 9).

」二記の製造方法にしkがえば、ダイジングL:l’j
 6に対応する裏面に、硬質の絶縁膜9が形成さノ1て
いるので、ブレーキング時に絶縁膜9が容易かつ確実に
破断し、アベック不良に発生じない。
” According to the manufacturing method described in 2, dicing L: l'j
Since a hard insulating film 9 is formed on the back surface corresponding to 6, the insulating film 9 is easily and reliably broken during braking, and no abnormality occurs.

なお、」−記実施例は半導体つj−−ハコ全所定の残り
代全設けてバー)′カットシ、たのっブレー−−1−ン
グする場合について説明し、/こが、絶縁膜9 i’L
II ’:JJを・てλ−んで完全カントするようにし
てもよい。この場合、絶縁膜9が有史′改なので、グイ
シングソウが目詰りすることなく、容易かつ確実に完全
カットできる。
In addition, the embodiment described in ``-'' describes the case where the entire semiconductor layer 9 is provided with a predetermined remaining space, and the insulating film 9 'L
II': JJ may be completely canted with λ-. In this case, since the insulating film 9 is made of historical material, the cutting saw can be easily and reliably completely cut without clogging.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図ないし第3図は従来方法について説明する/こめ
の各段階の半導体つ1−ハの断面図である。 第4図ないし第9図はこの光1iJIによる方法につい
て説1.lJJするだめの各段階の半導体ウェーハの+
=血はITある。 〕−・・ご14導体ウェーハ、 2・−!1′−導体素子、 3.4・・ 位属層、 5 接ン11テーフ゛、 6−・ ダインン′グ(flj、 8.9・ 絶4隊膜、
1 to 3 are cross-sectional views of a semiconductor device at each stage of the conventional method. Figures 4 to 9 illustrate the method using this light 1iJI. + of semiconductor wafers at each stage of lJJ
= IT is in my blood. ]-...14 conductor wafer, 2-! 1'-conductor element, 3.4... layer, 5 contact 11 tape, 6--dying (flj), 8.9- 4-layer film,

Claims (1)

【特許請求の範囲】 」−半導体ウェーハに多数の牛尋体素子全形成する−に
程と、 半!!7体ウェーハの裏面の各半4体素子間に対応する
位置に絶縁膜全杉成する工程と、 l“′尋体ウェーハの裏111jの前記絶縁膜形成部分
以外に11大質金属層全形成する工程と、+iiJ記絶
縁膜に幻j心する位1′uから半導体ウェーハをダイソ
ングすゐ工程と?含む半導体装置の製造方法。 Z 前記り中質金属層全ステンシル法で形成する、特寥
:’11ilj求の15氾囲第1項記戦の半導体装置の
製造方法。
[Claims] ``-To form a large number of cylindrical elements on a semiconductor wafer--about half a minute! ! forming an insulating film on the back surface of the 7-body wafer at positions corresponding to each half of the 4-body wafer; and forming 11 high-quality metal layers on the back side 111j of the 7-body wafer except for the insulating film forming portion. A method for manufacturing a semiconductor device including a process of die-song a semiconductor wafer from 1'u to 1'u to form an insulating film. : A method for manufacturing a semiconductor device according to Item 1 of the '11 Ilj Request for 15 Floods.
JP58175794A 1983-09-22 1983-09-22 Manufacture of semiconductor device Granted JPS6066830A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP58175794A JPS6066830A (en) 1983-09-22 1983-09-22 Manufacture of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP58175794A JPS6066830A (en) 1983-09-22 1983-09-22 Manufacture of semiconductor device

Publications (2)

Publication Number Publication Date
JPS6066830A true JPS6066830A (en) 1985-04-17
JPH0342507B2 JPH0342507B2 (en) 1991-06-27

Family

ID=16002360

Family Applications (1)

Application Number Title Priority Date Filing Date
JP58175794A Granted JPS6066830A (en) 1983-09-22 1983-09-22 Manufacture of semiconductor device

Country Status (1)

Country Link
JP (1) JPS6066830A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH02220811A (en) * 1989-02-23 1990-09-04 Nippon Inter Electronics Corp Production of semiconductor device
US20140346642A1 (en) * 2011-09-06 2014-11-27 Vishay Semiconductor Gmbh Surface mountable electronic component

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5158862A (en) * 1974-11-19 1976-05-22 Matsushita Electronics Corp Handotaisoshino bunkatsuho
JPS5386570A (en) * 1977-01-10 1978-07-31 Mitsubishi Electric Corp Production of semiconductor device

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5158862A (en) * 1974-11-19 1976-05-22 Matsushita Electronics Corp Handotaisoshino bunkatsuho
JPS5386570A (en) * 1977-01-10 1978-07-31 Mitsubishi Electric Corp Production of semiconductor device

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH02220811A (en) * 1989-02-23 1990-09-04 Nippon Inter Electronics Corp Production of semiconductor device
US20140346642A1 (en) * 2011-09-06 2014-11-27 Vishay Semiconductor Gmbh Surface mountable electronic component
US10629485B2 (en) * 2011-09-06 2020-04-21 Vishay Semiconductor Gmbh Surface mountable electronic component

Also Published As

Publication number Publication date
JPH0342507B2 (en) 1991-06-27

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