JPS6060743A - Lead frame - Google Patents
Lead frameInfo
- Publication number
- JPS6060743A JPS6060743A JP58169653A JP16965383A JPS6060743A JP S6060743 A JPS6060743 A JP S6060743A JP 58169653 A JP58169653 A JP 58169653A JP 16965383 A JP16965383 A JP 16965383A JP S6060743 A JPS6060743 A JP S6060743A
- Authority
- JP
- Japan
- Prior art keywords
- frame
- lead
- lead frame
- heat
- wire
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/495—Lead-frames or other flat leads
- H01L23/49541—Geometry of the lead-frame
- H01L23/49558—Insulating layers on lead frames, e.g. bridging members
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/0555—Shape
- H01L2224/05552—Shape in top view
- H01L2224/05554—Shape in top view being square
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/484—Connecting portions
- H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
- H01L2224/48465—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond the other connecting portion not on the bonding area being a wedge bond, i.e. ball-to-wedge, regular stitch
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4899—Auxiliary members for wire connectors, e.g. flow-barriers, reinforcing structures, spacers, alignment aids
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/491—Disposition
- H01L2224/4912—Layout
- H01L2224/49171—Fan-out arrangements
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01082—Lead [Pb]
Landscapes
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Wire Bonding (AREA)
- Lead Frames For Integrated Circuits (AREA)
Abstract
Description
【発明の詳細な説明】
産業上の利用分野
本発明は、半導体パッケージに適用するリードフレーム
のインナーリード部の先端部もしくはグイアタッチメン
トの一部を含む部分にセラミックや耐熱有機物からなる
枠を有する構造のリードフレームである。DETAILED DESCRIPTION OF THE INVENTION Field of Industrial Application The present invention relates to a structure having a frame made of ceramic or a heat-resistant organic material at the tip of the inner lead part of a lead frame applied to a semiconductor package or at a part including a part of the wire attachment. This is a lead frame.
従来ｆ５の構成とその問題点
従来のリードフレームは、第１図の外観斜視図に示すよ
うに、リードフレーム１のダイアタッチメント部分２に
半導体チップ３を金−シリコン共晶、導電性ペースト、
錫−鉛ハンダ等の方法で固着していた。さらにこの半導
体チップ３は、チップ上のポンディングパッドと、リー
ドフレームのインナーリード部４を、金もしくはアルミ
ニウム細線（ワイヤー）５で接続することで半導体パン
ケージのアウターリード６と半導体チップ３間の電気的
接続を行っていた。Structure of conventional f5 and its problems In the conventional lead frame, as shown in the external perspective view of FIG.
It was fixed using methods such as tin-lead solder. Furthermore, this semiconductor chip 3 can be electrically connected between the outer leads 6 of the semiconductor pancage and the semiconductor chip 3 by connecting the bonding pads on the chip and the inner lead portions 4 of the lead frame with gold or aluminum thin wires (wires) 5. connection was made.
ところがチップ上ポンディングパッドとインナーリード
を接続する金もしくはアルミニラのリード線は細線であ
るために、径間の長いワイヤーを張った場合、第１にワ
イヤーボンディング中にワイヤーのループ形状が乱れて
、チップエッヂやダイアタッチメントのエッヂにワイヤ
ーの接触が生じたり、隣りのワイヤーとの間で接触が生
じ、組立規則に、過大な制約を与えるという問題があっ
た。また第２に、ワイヤーボンディング後に異常が生じ
てなくても、樹脂封止工程での樹脂注入の際に、樹脂注
入圧によってワイヤーが変形し、上述の接触不良が生じ
るという問題があった。However, since the gold or aluminum lead wires that connect the bonding pads on the chip and the inner leads are thin wires, when a long wire is stretched, the first problem is that the loop shape of the wire becomes disordered during wire bonding. There is a problem in that wires come into contact with the chip edge or the edge of the die attachment, or with adjacent wires, which places excessive constraints on the assembly rules. Second, even if no abnormality occurs after wire bonding, there is a problem in that the wire is deformed by the resin injection pressure during resin injection in the resin sealing process, resulting in the above-mentioned poor contact.
発明の目的
本発明は従来例にみられた上述の問題点を−挙に解消す
るとともに、一種類のリードフレームで広範囲のサイズ
の半導体チップを処理することの出来るリードフレーム
を提供せんとするものである０
発明の構成
本発明は要約すると、リードフレームのチップ搭載側の
インナーリード先端部もしくは、ダイアタッチメントの
一部を含む部分に、セラミックもしくは耐熱性有機物か
らなる枠体を接着固定したもので、これにより径間の細
線の一部を支えることができ、上述の目的が確実に達成
される。OBJECTS OF THE INVENTION The present invention aims to solve all of the above-mentioned problems seen in the conventional example, and to provide a lead frame that can process semiconductor chips of a wide range of sizes with one type of lead frame. 0 Structure of the Invention To summarize, the present invention is a lead frame in which a frame made of ceramic or a heat-resistant organic material is adhesively fixed to the tip of the inner lead on the chip mounting side of the lead frame or to a part including a part of the die attachment. , which makes it possible to support a portion of the narrow wire in the span, ensuring that the above-mentioned objective is achieved.
実施例の説明 以下、本発明を図面の実施例を参照して詳しくのべる。Description of examples Hereinafter, the present invention will be described in detail with reference to embodiments of the drawings.
第２図は本発明のリードフレームのインナーリード付近
の拡大斜視図である。FIG. 2 is an enlarged perspective view of the vicinity of the inner leads of the lead frame of the present invention.
本発明のリードフレーム１のアウターリード部６とイン
ナーリード部４は従来のままである。しかし本発明では
、インナーリード４の先端部分に、セラミックもしくは
耐熱有機物でなる枠体７を設け、半導体チップ３をその
枠内に配し、ワイヤ〜５は、ダイアタッチメント２を囲
むように、耐熱接着剤８で固定された前記枠体７を越し
てワイヤボンドする。この枠体７の高さは、半導体チッ
プ３の厚みにより異るが、一般に４００〜５００μｍと
する。この枠体７の取り付けは、ダイボンド工程の前後
どちらでも良いが、高温条件を避ける場合は、ダイボン
ド工程後に取り付ける。この状態でワイヤーボンドを行
うが、この時ワイヤー６は、チップポンディングパッド
９からインナーリード４まで、枠体７越しに張る〇
こうすることでワイヤー５の、ダイアタッチメント部分
２のエッヂや、半導体チップ３のエッチへの接触不良が
解消される。すなわち、枠体７がショート防止の作用を
なす。The outer lead portion 6 and inner lead portion 4 of the lead frame 1 of the present invention remain the same as the conventional ones. However, in the present invention, a frame 7 made of ceramic or a heat-resistant organic material is provided at the tip of the inner lead 4, the semiconductor chip 3 is arranged within the frame, and the wires 5 are arranged so as to surround the die attachment 2. Wire bonding is performed across the frame 7 fixed with adhesive 8. The height of this frame 7 varies depending on the thickness of the semiconductor chip 3, but is generally 400 to 500 μm. The frame body 7 may be attached before or after the die bonding process, but if high temperature conditions are to be avoided, it should be attached after the die bonding process. Wire bonding is performed in this state. At this time, the wire 6 is stretched from the chip bonding pad 9 to the inner lead 4 over the frame 7. By doing this, the edge of the die attachment part 2 of the wire 5 and the semiconductor Poor contact with the etch of the chip 3 is eliminated. That is, the frame body 7 functions to prevent short circuits.
寸た、ダイアタッチメント２やインナーリード部４の一
部は、半導体チップ３の取９付は方法によって、表面の
メッキ材料に、金や銀を用い、リードフレーム１の材料
も、鉄系や銅系合金等を用いることが出来る。In addition, the die attachment 2 and part of the inner lead part 4 are plated with gold or silver depending on the mounting method of the semiconductor chip 3, and the material of the lead frame 1 is also iron-based or copper. A series alloy etc. can be used.
発明の効果
本発明によれば、長径間ワイヤーが適用可能と々るため
、大きなダイアタッチメントのリードフレーム１種類で
同一外形の半導体パッケージ中に広範囲のサイズの半導
体チップが収納でき、工程標準化が図れる。さらに近年
の大電力半導体の開発に伴い、放熱性の良い半導体パッ
ケージ開発の要望が強く、このパッケージ開発を達成す
るために、通常封止樹脂中に混ぜられている充填剤の量
が増やされる。これによって樹脂注入時に生じる長径間
ワイヤーの変形を、本発明を適用することで解消できる
。Effects of the Invention According to the present invention, since long span wires can be applied, semiconductor chips of a wide range of sizes can be housed in a semiconductor package of the same external shape using one type of large die attachment lead frame, and process standardization can be achieved. . Furthermore, with the recent development of high-power semiconductors, there is a strong demand for the development of semiconductor packages with good heat dissipation, and in order to achieve this package development, the amount of filler mixed in the sealing resin is usually increased. As a result, deformation of the long span wire that occurs during resin injection can be eliminated by applying the present invention.
第１図は従来例斜視図、第２図は本発明実施例要部拡大
斜視図である。
１・・・・・・リードフレーム、２・・・・・・ダイア
タッチメント部分、３・・・・・・半導体チップ、４・
・・・・・インナーリード部、６・・・・・・細線（ワ
イヤー）６・・・・・・アウターリード、了・・・・・
・枠体、８・・・・・・接着剤、９・・・・・・ボンデ
ィングパヮド。FIG. 1 is a perspective view of a conventional example, and FIG. 2 is an enlarged perspective view of essential parts of an embodiment of the present invention. 1...Lead frame, 2...Die attachment part, 3...Semiconductor chip, 4...
...Inner lead part, 6...Thin wire (wire) 6...Outer lead, completed...
-Frame body, 8...adhesive, 9...bonding pad.
Claims (1)
部もしくはグイアタッチメントの一部を含む部分に、セ
ラミックもしくは耐熱有機物がら寿る枠体を接着固定し
た構造のリードフレーム。A lead frame with a structure in which a frame made of ceramic or heat-resistant organic material is adhesively fixed to the tip of the inner lead on the chip mounting side of the lead frame, or to the part that includes a part of the lead attachment.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP58169653A JPS6060743A (en) | 1983-09-14 | 1983-09-14 | Lead frame |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP58169653A JPS6060743A (en) | 1983-09-14 | 1983-09-14 | Lead frame |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS6060743A true JPS6060743A (en) | 1985-04-08 |
Family
ID=15890453
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP58169653A Pending JPS6060743A (en) | 1983-09-14 | 1983-09-14 | Lead frame |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6060743A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0287636A (en) * | 1988-09-26 | 1990-03-28 | Nec Corp | Semiconductor device |
| JP2006027842A (en) * | 2004-07-16 | 2006-02-02 | Fuji Xerox Co Ltd | Paper feeding device and image forming device |
-
1983
- 1983-09-14 JP JP58169653A patent/JPS6060743A/en active Pending
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0287636A (en) * | 1988-09-26 | 1990-03-28 | Nec Corp | Semiconductor device |
| JP2006027842A (en) * | 2004-07-16 | 2006-02-02 | Fuji Xerox Co Ltd | Paper feeding device and image forming device |
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