JPS6054538A - Signal transmitting system - Google Patents

Abstract

PURPOSE:To improve transmission accuracy by finding differential data and the maximum value for every block formed by dividing PCM data at a scheduled time and using higher order bits as effective ones and cutting off lower order bits when high level signals exceed a scale value corresponding to the maximum value. CONSTITUTION:An analog original signal is AD-converted and, for example, a PCM signal of 15 bits is obtained. The PCM signal is then delayed by one sample time at a delay circuit 2 and inputted into a differentiator 3 together with 15-bit data. The PCM signal and 15-bit data are sent out to a transmission system as a differentiated signal DPCM of 16 bits. The DPCM is given to an adder 4 and added to the last output of the adder which is delayed by one sample time at another delay circuit 5 and accumulated (integrated). The accumulated data are DA-converted as 15-bit data and outputted as analog signals. In the course of encoding the DPCM, differential data between two samples adjacent to each other in time are transmitted and, therefore, the mean value becomes smaller. When a high level signal exceeds a scale value, higher order one is used as an effective one and lower order one is cut off. By transmitting the number of cut off bits to the receiving side, the transmission accuracy is improved with less number of bits.

Description

Detailed Description of the Invention [Technical Field of the Invention] The present invention relates to signal transmission using PCM (Pulse Code Modulation), and in particular to differential PCM or DPCM (diHere
ntial PCM) is known. In normal PCM encoding, values obtained by sampling an analog original signal such as an audio signal every moment are converted into digital data, that is, PCM? In contrast, in DPCM, only the difference from the previous value, that is, the difference between two samples, is transmitted as digital data.

FIG. 1 shows an example of a transmission system using DPCM encoding.

In the system shown in FIG. 1, the difference is not taken in the state of absolute log values, but in digital values. In other words, an analog original signal, for example an audio signal, is A
For example, 15 in ID (analog-digital) converter 1
It is converted into digital data of bits 1~, and is given to the difference unit 3 together with the data delayed by one sample in the delay circuit 2 using a register etc., and the difference data between the two, that is, the OPCM code, is transmitted in, for example, 16 bits 1~. sent to the system. Here, the term "transmission system" refers to a transmission line such as a simple connection line or a communication line (sometimes using radio waves, light, etc. as a medium) via a modulation/demodulation system, as well as a recording/reproduction system (where the recording medium is Refers to the so-called transmission system in a broad sense, including the transmission media (transmission medium). In this case, the difference data to 16 bits 1 transmitted by the transmission system is given to the adder 4, and is added to the previous adder 4 output delayed by one sample at the delay port Fδ5, and is accumulated (integrated), for example, 15 bits. The bit data is applied to the UD/A <digital-to-analog) converter 6, and an analog audio signal is output.

In DPCM encoding, the difference data between two temporally adjacent samples is transmitted. Although the transmitted data value is small on average, the rarely occurring maximum level data is almost the same data value as in PCM. (level).

In other words, the two characteristics of DPCM are (a) the average level of transmitted data is very small, and (b) the maximum level of transmitted data is the same as ordinary PCM, but the probability of its occurrence is very low. be.

As a method for effectively transmitting all data with a small average level and a low probability of occurrence of a high-level signal, normal transmission is performed using a predetermined number of bits that is smaller than the original data, and the range that can be expressed with this predetermined number of bits is It is conceivable that a high-level signal exceeding the above-mentioned value is transmitted by using only the predetermined number of upper effective bits as transmission data and discarding the lower bits. In this case, for the lower bits that were truncated, only the number of truncated bits is transmitted to the receiving side (the contents of the truncated bits are not sent)
This allows the receiving side to restore the correct number of digits, allowing for more accurate playback. In reality, the maximum level value of the samples in the block is detected for each data block consisting of a plurality of samples, and the data in the block is converted into digit shift information based on the data in the upper predetermined number of pixels. The main transmission data and scale information are transmitted as transmission data, and the digit shift information is used as scale information corresponding to the number of cut-off bits. In this way, it becomes possible to transmit almost sufficient information by simply transmitting 1 hour scale information of 1 WJ for each data block consisting of a large number of sample data.

A specific example of such a method will be explained in detail. The example described here is for reducing the number of transmission data to 1 by the above method in normal PCM transmission, and the configuration is shown in FIG.

In this case, the transmitting side converts an input analog signal, for example, an audio signal, into digital preliminary conversion data of a sufficient number of bits, for example, 15 bits, using the Δ/D converter 7 at scheduled time intervals, and then converts it into digital pre-converted data using the digital level detecting means 8. The maximum level within the scheduled period or a level approximately equivalent thereto is detected to obtain, for example, 4-bit scale information data, and the digital level variable control means 9 constituting the data compression section adjusts the above A based on the scale information data. The output preliminary conversion data of the /D converter 7 is digitally level-controlled and compressed to obtain, for example, 8-pips 1- main data, and this main data and the scale information data are combined by the synthesizing means 10 into a large number of main data. The data is sent to the transmission system so that one piece of scale information data corresponds to the data.

On the other hand, on the receiving side, a separation means 11 separates and extracts the main data and scale information data from the transmission signal received from the transmission system, and a digital level variable control means 12 constituting a data expansion section converts the main data into the scale information data. Based on this, digital level variable control (data expansion) is performed with control characteristics opposite to those on the transmitting side, and the data is converted into an analog signal by the D/A converter 13 to obtain an output analog signal.

The digital level detection means 8 detects the digital level by detecting the number of effective bits in the preliminary conversion data, that is, the most significant bit position of the effective bits 1 to 1 excluding the sign bit,
The digital level variable control in the digital level variable control means 9 is performed by extracting a pill position portion approximately corresponding to the most significant effective bit position from the preliminary conversion data to create main data.

For example, if the shaded part in the 15-bit preliminary conversion data is the effective filler 1- as shown in FIG. It occupies 6 bits of the data, and in order to take 8 bits of main data, the lower 8 bits ~ can be used as the main data.At this time, the position where the main data is taken is the lower 8 bits 1.
. . . Therefore, this corresponds to extracting only the lower 8 hits from the preliminary conversion data without any bit shift, and the control level 1 at this time, that is, the scale information becomes the shift amount "0". As can be seen from this example, the shift stone has the smallest O pitch j-, so when the number of effective bits is 8 or less, rOJ is uniformly selected as the scale information. In addition, in the case of (b) in the same figure, the effective number of bits is 9 bits, so
As is clear from the figure, the main data extraction position is shifted to the upper (left) by 1 bit, and the scale information is “1”.
'', and if 8 pi 1- is taken as the main data, the least significant bit, that is, the LSB (least significant bit) of the preliminary conversion data is ignored, and this portion becomes an error. (At this time, it can be considered that the preliminary conversion data is shifted one bit lower (to the right) with respect to the extraction position of the 8-bit main data, and the lower one bit is discarded.) In the case of (C) in the same figure, the effective number of bits is It is 15 bits, and the scale information is "7", and in this case, the lower 7 bits 1- of the preliminary conversion data are ignored. That is, in this case, the scale information corresponds to the number of truncated bits. In this way, when the number of effective bits is large, the effective bits that are ignored and truncated become errors, but
This is a sufficiently small value compared to the value of the main data. In this case, the maximum level of scale information is 8 (= 2, 3f types), so the scale information data only needs 3 bits.In reality, the scale information data corresponds to one data for each large number of preliminary conversion data. , Detect and set scale information by measuring or predicting the maximum value in a large number of corresponding pre-converted data in advance, and set common scale information (shift amount) for a large number of corresponding pre-converted data;
This scale information is detected and updated for each of the large number of preliminary conversion data.

In addition, in the above, the main data consists only of the data extracted from the preliminary conversion data by bit shifting (~), but this is because the analog signal handled is a unipolar signal with only one positive or negative sign (polarity) pitch in the preliminary conversion data. 1 or not, or even if a sign bit is included, there is no need to transmit it.On the other hand, if the input analog signal is a bipolar signal such as an audio signal, in which both positive and negative signals are mixed, In a signal, the preliminary conversion data itself usually includes a sign bit or a bit equivalent to it as at least the MSB (most significant bit), and this is also essentially an important valid bit, so this sign bit and the above Of course, the data obtained by bit shift 1- is used as main data.In other words, if the main data is 8 bits, 1 bit of it is used as a sign bit, so this code bit 1- and 7 obtained by bit shift are used as main data. Base the main data with bit data.

By the way, in this case, the digital level variable control means 9 on the receiving side shifts the main data separated from the transmission signal with the same shift indicated by the similarly separated scale information data, so that it is equal to the pre-transformed data. This means that the number of bits of playback data will be obtained. That is, Fig. 3(a)
In the example shown in , the 8-bit main data is used as the lower 8 bits, and the data is equal to 1, which is the same as the original pre-value conversion data.
Obtain 5-bit playback data. In the example shown in Figure (b), the 8-bit main data is similarly shifted to the upper (left) by 1 bit, and 1 bit of additional data is added to the lower part to create 15-bit playback data, and in the example shown in Figure (C), the The main bit data is shifted to the upper part by 7 bits, and the 7 bits of additional data are added to the lower part to create 15-bit playback data. Here, as the data added to the lower order, data uniquely determined in advance, such as O data or average value data, is used. That is, suppose, for example, that the 15-bit preliminary conversion data is data as shown in FIG. 4('a). When transmitting 8-bit main data based on this (here, we are considering the case where the code bits 1 to 1 are not considered), the upper 8 bits of the valid hits are extracted as main data as shown in the figure, and the lower 4 bits are truncated. The receiving side receives the main data and shifts the main data by 1 pitch according to the scale information corresponding to the pick 1 position from which the 8-bit main data in the preliminary conversion data is extracted, and converts the main data into 15-bit main data. make.

At this time, basically as shown in M4 diagram (b), '°O
0 corresponding to the number of bits shifted from 1 to 0, such as "o o o"
Add data. In addition, in order to reduce the error from the original data on average, it is necessary to set a value that approximately corresponds to the average value of the data that can be expressed by the corresponding number, for example, "'0111" as shown in Figure 4 (C). It is effective to use average value data such as `` as additional data.

Even if the additional data is data other than these 0 data or average value data, there is often no practical problem as long as it is a constant value for each number. It goes without saying that when these additional data take values other than O data, the difference between the value indicated by the lower bits of the original data, that is, the preliminary conversion data, and the additional data is essentially truncated data.

By the way, although a method such as the example shown in FIG. 2 above can be used when transmitting ordinary PCM, that is, PCM coded data as is, it is difficult and desirable to apply it as is to DI]CIvl. do not have.

The main reason for this is that, as shown in Figure 1, DPCM reception requires decoding by accumulating and integrating the received data, and errors caused by truncation on the transmitting side are added up on the receiving side, resulting in large errors. This is because it becomes .

For this reason, even if the average level of transmission data was lowered by DPCM, it was not possible to reduce the number of actual transmission data to 1.

In addition, for example, HAAD PCN3(adapNve D
It is also possible to lower the number of transmission pins by predetermining a fixed rule between transmission and reception, such as PCM (adaptive differential PCM), and performing nonlinear transmission and reception while lowering the level resolution on the receiving side. Such ADPCM etc. cannot be said to have very high precision, and have had many problems such as not only being unable to perform good reproduction on the receiving side, but also making the device complicated.

On the other hand, the following transmission method can be considered as a transmission method that takes advantage of the effect of reducing the average level of transmitted data by DPCM and enables high-precision transmission with a small number of bits.

That is, a first process of successively converting PCM code data into DPCM data, and testing the size of the DPCM code data based on the DPCM code data and converting a predetermined number of samples into one block within the data block. In order to be able to send the maximum data, the upper effective bits 1 to 1 are selected sequentially. The second process extracts the pill position as scale information, and if there is lower-order data that is substantially truncated when converting the main data, the truncated data is converted in the first process. subsequent OPCM
A third process in which the DPCM code data obtained in the first process is added to the code data and used in the second process, and the result of the first to third processes is added to the DPCM code data obtained in the second process. The fourth part sends the main data and scale information to the transmission system.
and in this fourth process, the transmission data transmitted is received, and based on the received data, the received main data is converted to DPCM data using a bit shift according to the reception scale information, and the DPOM code is decoded and demodulated. This method performs the fifth process.

'By the way, in such a system, the above-mentioned second . Specifically, in the data compression unit which is the main part of the third process, for example, the accumulator is operated as follows.

That is, for example, 16-bit input DPCM code data is added to the lower residual data (i.e., truncated data) remaining in the accumulator without being extracted or transmitted due to the previous extraction of main transmitter data, and the upper valid data of the data after this addition is A bit portion, for example 8 bits, is extracted and transmitted as main data. As a result, the lower residual data remains in the accumulator again. Here, the bit positions from which the main data is extracted (the upper effective bit positions) are the same within the same data block, and information indicating the positions of pins 1 to 1 is transmitted as a scale value for each block.

In this case, as a result of adding the input DPCM code data to the lower residual data in the accumulator, a carry exceeding the transmission range of the main data may occur, resulting in an overflow. The number of effective digits of the input DPCM code data is checked in advance in each block before addition in the accumulator, and the difference between the maximum value in the block and the number of digits of the main transmission data becomes the scale value (≧0). Therefore, if the above-mentioned overflow occurs, the most important upper bits of the valid bits are not transmitted, resulting in a large error.

Referring to FIG. 5, an example will be described in which a 2-S combination is used for the DPCM code and the scale value is constant at 6.

Due to the previous main data extraction, the lower residual data remaining in the accumulator is 1iooo as shown in Figure 5(a).
oo'', as shown in Figure (b).
0001111111011101 "When the DPCM code data is input, both are added in the accumulator, and as shown in the same figure (C)" OO100000
The data “00001101” is obtained. Since the scale value is 6, the main transmission data in this case is as shown in (d) in the same figure.
As shown in , it becomes '10000000''.

In this case, even though the data is positive, the most significant sign bit in the original data is not O'', which indicates positive, but 1'', which indicates negative, due to the above-mentioned carry, resulting in a large error.

In order for this inconvenience to occur, (a) there must be seven or more consecutive "1"s in positive input data, and (b) the contents of the accumulator (i.e., the previous lower residual data) must be the same. Two conditions must be satisfied: the result of addition with the lower digits of the input data must carry beyond the transmission bit position from which the transmission main data is extracted. Therefore, although the probability of its occurrence is generally as low as approximately 1 in 2 to the 9th power = 1 in 512, it is not desirable. .

If the scale value is significantly lower than the previous data block, an overflow similar to that described above may occur, and the probability of this type of overflow occurring becomes extremely high.

The occurrence of this type of overflow will be described in detail with reference to FIG. In this case, it is assumed that the DPCM code is still a 2-S combination, and the scale value changes from 6 to 1.

The lower residual data remaining in the Akicomulator due to the previous main data extraction is '1100' as shown in Figure 6(a).
00” and the scale value changes from 6 to 1.
and at the same time, '00000000' as shown in the same figure (b).
If the input data ``11011101'' is given, the two are added together in the accumulator.
You can get evening. Since the scale value is '1', the main transmission data in this case is '1' as shown in Figure (d).
0000110'', and the most significant sign bit becomes II II II which means a negative value due to carry.

The probability of such a case occurring is generally very high, approximately once in 2 to the 4th power - 16 times, and this poses a serious problem.

In this way, when an overflow occurs in the transmission main data during signal transmission using data compression as described above, a large error occurs between the transmitter and the receiver, such as positive data becoming negative data.

A method to prevent the overflow error (occurrence of carry to the most significant digit of the transmission main data) that occurs when the lower residual data (contents of the accumulator described above), which is a digit loss part, is added to the original data as described above. There are several possibilities. However, if errors are prevented between transmission and reception in this way, and the cumulative value of data is not changed between transmission and reception, another problem arises.

For example, if the above-mentioned overflow occurs, there is a method of adding and accumulating only the missing part in the accumulator without adding the new original data and the lower residual data in the accumulator. is possible.

In this case, if the next original data is J3 and it becomes possible to add the contents of the accumulator (if no overflow occurs due to addition), the intended result will be obtained, but if this original data (original data of the above method), if the above addition is not allowed, only the contents of the accumulator will increase. Thus, the larger the contents of the accumulator, the greater the probability that the above addition will overflow, until it even becomes impossible to add the contents of the accumulator to the supplied raw data (this amount is This tends to occur when the number of bits of the main data is small, such as 3 to 4 bits). In addition, even if the addition is postponed for several consecutive months and it is finally possible to add it afterwards, there will be a large time delay, and if the contents of the accumulator are transmitted at this point, it is meaningless, and in fact, There is even the risk of causing negative effects. In addition, even though the contents of the 7 cumulator are carried into the transmission bits in this way, the transmission is not performed (addition is reserved), and the digit loss part, that is, the lower residual data is added, and this If it is not clear how long such a state will last, and if hardware is designed to perform the planned processing, the hardware may become extremely complex.

[Objective of the Invention] The object of the present invention is to sufficiently suppress the occurrence of overflow errors in the transmitted data in transmitting PCM encoded data with a small number of bits with high precision, and to further improve the transmission precision so as to be practical. It is an object of the present invention to provide a signal transmission method which can obtain sufficient measurement results and does not cause new problems such as complication of hardware.

[Summary of the Invention] The present invention detects the maximum value within a block of PCMm@original data in units of data blocks consisting of data groups for each scheduled time, determines a scale value based on the detected value, and calculates the maximum value of the original data. Scheduled pick 1 from the bit position corresponding to the scale value
-μ data is sequentially extracted and it is determined whether or not overflow will occur in the data of the above scheduled number of bits when the substantial lower residual data is added to the subsequent original data, and it is determined that no overflow will occur. If it is determined that an overflow will occur, the above addition is performed, and if it is determined that an overflow will occur, the above addition is not performed and processing is performed using a predetermined logic that does not substantially cause an overflow, and the number of pins is smaller than the original data. Then, obtain the main data in which the upper valid pins 1 to 1 of the original data are generally prioritized, transmit this main data and scale information indicating the scale value through the transmission system, and receive this to receive the received main data. The present invention is characterized in that reproduction data having the same number of hits as the original data is obtained by performing filler 1 to shift 1 in accordance with scale information.

[Embodiments of the Invention] Prior to specific explanations of embodiments of the present invention, the principle of the present invention will first be explained.

The above-mentioned PCM (upper)'1. If the compressed transmission method (explained in the case of DPCM) is adopted, that is, the method in which PCM transmission is performed by performing cumulative carry correction of lower residual data by accumulator operation for compressed data transmission on the transmitting side. ) has the following advantages:

(a) Since the quantization noise that occurs with PCM encoding becomes white, it becomes audibly more natural (less harsh) noise than the original quantization noise, making it easier to hear, especially when targeting audio signals. Become.

(t)) By whitening the quantization noise, the quantization noise is uniformly distributed up to high frequencies, so (when emphasis is performed) the measurement S/N is also improved by the de-emphasis circuit on the receiving side. .

(C) Whitening of quantization noise results in THD(t.

tal harmonic distortion ~
total harmonic distortion) decreases.

(d) In D''-PCM, the whitened noise is attenuated by the integrator on the receiving side, so the S
/N is obtained.

(e) In DPCM, 1. Even if there is an error in the individual values of the difference data, the cumulative value is transmitted and received without any deviation, so the integrator (accumulator) on the receiving side approaches the correct data, making it possible to obtain good THD characteristics. can.

(f) Since the cumulative value of the received data does not change during transmission, even if the DPCM code is compressed and transmitted, for example, a DC component may be generated on the receiving side, or the DC component may fluctuate, resulting in noise or overturning. No problems will occur.

These advantages do not suddenly disappear even if the operation of the above-mentioned Akicom rake is instantaneously stopped or the processing logic of the accumulator is instantaneously changed.

In other words, the effect of the above-mentioned accumulator rake process changes depending on the probability of occurrence of a situation in which the accumulator stops, that is, a situation in which the accumulator must be stopped.If the probability is small, it is possible to stop the accumulator instantly. There is no problem even if the processing logic of Akicom Lake is changed momentarily. (Hereinafter, making the processing logic of the accumulator different from the above, including stopping the operation of the accumulator, will be expressed as "making the logic of the accumulator different.") Therefore, in the present invention, as described above, the transmission Overflow of moisture transfer data is avoided by varying the accumulator logic only when data overflow would occur.

There are various ways to change the accumulator logic in the present invention.

First, a first embodiment will be described with reference to FIG.

This first embodiment does not actively differ in the accumulator logic with respect to the first overflow, but merely changes the supplied raw data (DPCM in the previous example).
This is handled by not adding the code data) and the contents left in the accumulator. A different accumulator logic is then used for the second consecutive overflow.

That is, in the case of FIG. 7, the scale value is "4" and the contents of the accumulator, that is, the accumulated lower residual data are 11011'' as shown in FIG. 7(a).In other words, the contents of the accumulator are Since it is 5 digits,
The most significant bits 1~ must be added to the next original data to retrieve the transmitted data. However, these days the original data given is, for example, 00 as shown in Figure (b).
00011111111101", adding to the accumulator will cause an overflow in the transmitted data, so the addition is not performed and
The compressed transmission digit position data of the given original data is '01111111°.

is used as the transmission data as is. At this time, without actively modifying the logic of the accumulator, the digit loss of the original data (during compression) is ``1101''.
" is added to the contents of the previous accumulator and the same figure (C1
), the value becomes '101000'.The content of this accumulator is a large value of 6 digits.Furthermore, the next original data is also '0000' as shown in Figure (e).
011111101010'', which is a large value that cannot be added without overflowing.In this way, if the original data that cannot be added without overflowing to the transmission digits happens to be given consecutively. In this case, without adding the original data to the accumulator,
As shown in (f) of the same figure, it is possible to transmit the data "'01111110" at the transmission digit position determined by the scale value of the original data, and also to transmit the data "'01111110" at the transmission digit position determined by the scale value of the original data. By replacing the contents with "1111" with the zero-digit bit set to 1111+, the next time the process will be performed using normal accumulator logic.

Even if this is done, the 8-bit transmission system will not be impaired in any way, and the function of the 7 cumulator, which is required to obtain a level of 8 bits or more, will only momentarily stop, resulting in an extreme case of overflow. It is possible to avoid the occurrence of inconvenient situations.

In addition, in the above, in order to actively vary the logic of the accumulator, 7111 I
The data containing I is stored in the accumulator instead of the original cumulative value of the digit loss, and is used for subsequent processing. It may be another preset specific pattern (not carried into the transmission bit), or it may be carried into the transmission bit in the accumulator at that point to simplify the hardware configuration. (for example, the 7th part is removed)
The upper '10' in figure (d) is removed and '10' is removed.
00'' as the contents of the accumulator).

Next, a second embodiment will be described with reference to FIG.

This second embodiment prevents addition when given raw data that cannot be added to the contents of the accumulator without overflowing into the transmitted data, and
This immediately makes the accumulator logic positively different.

That is, when the scale value is "4" and the content of the accumulator is 11011'' as shown in FIG.
Suppose that original data of 11101°' is given. In this case, an overflow will occur due to the addition, so instead of adding to the accumulator, the original data will be directly converted to '011' + 1111° as shown in the same figure (c').
'' is retrieved and transmitted, and the contents of the accumulator are immediately transferred to 1111 as shown in (d) of the same figure.
, and use it for subsequent processing.

A third embodiment will be described with reference to FIG.

Similar to the second embodiment, in this third embodiment, when original data that cannot be added to the contents of the accumulator without overflowing to the transmitted data is given, the addition is stopped, and This method immediately actively changes the accumulator logic, and instead of setting the data in the accumulator that will be used for subsequent processing to a ``1'' to ensure a zero digit, it simply changes the carry digit in the accumulator to ``1''.
This is to delete the minutes.

That is, when the scale value is "14" and the contents of the accumulator are "11011" as shown in FIG. 9(a), "0000011111" as shown in FIG. 9(b).
Suppose that the original data 111101'' is given.In this case, since an overflow may occur due to addition, the original data is directly converted to °'01111111°' without addition to the accumulator as shown in the same figure (C). The transmission data is retrieved and transmitted, and the same figure (
As shown in d), the most significant bit of the contents of the accumulator is removed as '1011' and used for subsequent processing.

In this case, instead of the missing part of the accumulator, the missing part of the newly given original data may be used as data to be left in the accumulator for subsequent processing.

In the above, it was basically explained that the data at the bit position according to the scale value is extracted from the result of adding the contents of the accumulator, that is, the cumulative data with digit loss, and the given original data, and is used as the transmission (main) data. , once extract the part of the original data that corresponds to the transmission digit position as compressed data, add the digit loss to the accumulator, and add it to the compressed data only when a carry occurs in the accumulator. Even if the basic processing logic is to obtain transmission data substantially similar to that described above, the present invention can be implemented in substantially the same manner as described above.

An embodiment in such a case is a fourth embodiment of the present invention, and details of the processing are shown in FIG.

That is, when encoding, first add the data for the digit loss of the given original data to the contents of the accumulator,
Store the result in an accumulator. At this time, it is determined whether or not a carry occurs in the accumulator. If a carry does not occur, it corresponds to the transmission digit position of the original data (the compressed data at the digit position according to the scale value is treated as the transmission data as it is). If a carry occurs, it is determined whether an overflow or low occurs in the compressed 8 bits 1 to 1 data by adding this carry, and if no overflow occurs, the above compressed 8 bits 1 is added.
~The data plus the carry is set as the transmission data. The processing when data overflows to the compressed 8-bit data due to the carry addition described above is a unique processing part of the present invention. and save it for further processing. '' As the process for correcting the contents of the accumulator, various methods such as those shown in the first to third embodiments can be applied.

FIG. 11 and FIG. 12 show a fifth embodiment of the present invention, which is an embodiment in which a device is specifically configured using the present invention.

FIG. 11 shows the configuration of the transmitting side of this embodiment, and FIG. 12 shows the configuration of the receiving side of this embodiment.

In FIG. 11, the same parts as in FIG. 1 are given the same reference numerals, and detailed explanation thereof will be omitted.

That is, 1 is an A/D converter that converts an analog original signal input such as an audio signal into digital data, and 2 is an A/D converter.
A sample delay circuit that delays D-converted PCM code data by one sample, 3 is a sample delay circuit that delays two consecutive PCM code data.
This is a subtractor that takes the difference between samples, and for example, 16-bit DPCM code data is obtained as the output of the subtractor 3. Reference numeral 14 denotes a block delay circuit constructed using, for example, a memory, which delays the DPCM code data outputted from the differentiator 3 by one digital block. 15 is a scale detection circuit, which detects the maximum absolute value of sample data in each data block from all the data for one block of DPCM code data output from the subtractor 3, and calculates the maximum value based on the detected value. A scale value is set for each block, and the set scale value is output as data of 4 pits 1, including cases where digit shift is not required.

Note that the above description assumes that a 2'-s combination is used, where the sign has a positive or negative sign, and the scale value is determined by the maximum absolute value of the sample data. When using a code, it may be necessary to detect the scale value using another method depending on the code.

16 is a compression encoder equipped with an accumulator, and 17 is an accumulator correction circuit, both of which realize the functions of the data compression section described above.

That is, the compression encoder 16 has a built-in accumulator and operates as follows. Scale detection circuit 15
Based on the scale value detected and set by the block delay circuit 14, compressed data of 8 bits 1 to (the bit length of the transmission main data) at the bit position corresponding to the scale value is obtained from the DPCM code data, in this case 16 bits, given from the block delay circuit 14. is taken out, temporarily held, and given to the accumulator correction circuit 17. Positive i which extracted the above compressed data at the same time
If a carry into the transmission digit occurs, the carry information is given to the accumulator correction circuit 17. If the accumulator correction pattern described above is not input from the accumulator correction circuit 17, the carry of the accumulator is added to the compressed data and output as main transmission data. When an accumulator correction pattern is input, the accumulator correction pattern is replaced with the content held in the accumulator at that time and is held in the accumulator, and the compressed data held at that time is output as is as the main transmission data. do.

The accumulator correction circuit 17 operates as follows. Based on the compressed data given from the compression encoder 16, the carry of the accumulator, and the scale value given from the scale detection circuit 15, it is detected whether a condition that causes an overflow in the transmitted main data is satisfied. If it is determined that the overflow condition is not satisfied, the accumulator correction circuit 17 does nothing.

If it is determined that the overflow condition is satisfied, an accumulator correction pattern having a preset number of bits corresponding to the loss of digits is provided to the compression encoder 16.

For example, if the compressed data extracted by the compression encoder 16 is 0
1111111'', and if there is a carry in the accumulator, the above-mentioned overflow will occur, so the above accumulator correction pattern is given to the compression encoder 16.The compression encoder 16 applies the accumulator correction pattern to the accumulator at that point. The compressed data held at that time is replaced with the contents held in the accumulator and output as the main transmission data.

This 8-bit transmission main data and the scale information data of 4 bits 1 to 1 for each block outputted from the scale detection circuit 15 are supplied to the transmission circuit 18, where both data are converted from parallel data to serial data and time It is multiplexed in sections and sent out serially to the transmission system.

Further, 19 is a control sequencer section, which operates based on the clock signal of the built-in clock generator, and includes the above-mentioned components, namely the A/D converter 1, sample delay circuit 2, difference unit 3, block delay circuit 14, and scale detection circuit. 15, the compression encoder 16, the accumulator correction circuit 17, and the transmission circuit 18 are each provided with a control signal in order to operate in a predetermined manner at a predetermined timing.

The above is the configuration of the transmitting side in this embodiment. Next, the configuration of the receiving side in this embodiment will be explained.

' In Fig. 12, 20 separates 8-bit main data and 4-bit scale information data from the transmission signal input from the transmission system, and converts both data from serial data to parallel data. This is a receiving circuit for

Reference numeral 21 denotes a shift clock generating section, which outputs shift 1 to clocks corresponding to the number of bits to be shifted based on the scale information data inputted from the receiving circuit 20. 22
is a data decompression circuit using a shift register, for example, and the main data inputted from the receiving circuit 20, that is, the compressed D
In this case, the PCM code data (8 bits) is shifted to the upper bit by the shift clock given from the shift-me clock generator 21, and expanded into 16-bit DPCM reception data. Note that if the data is expanded so that the entire operation is performed using the 2'S combination code, the main data (
The polarity code (0 or 1) that is the same as the MSB of the compressed DPCM code (compressed DPCM code) is processed so that it is consecutively located in the upper part of the shift register. That is, in this data expansion circuit 22, the 8-bit main data is subjected to processing 71 to 71 according to the scale information of the block to which the data belongs, and is converted into DPCM reception data. In this case, 23 is an addition circuit consisting of a 16-bit full adder, which corresponds to the adder 4 in FIG. Output the data. Reference numeral 24 denotes a data bold register, which roughly corresponds to the delay circuit 5 in FIG. and is used for addition with the latest data expansion circuit output (DPCM received data). Note that this integration system using addition is more efficient than using a complete integrator configuration.
It is often preferable to use an imperfect integrator configuration.

This is because, if the contents of the accumulator are modified as in the present invention, a slight DC error caused by the modification will remain in the integral-addition system forever. In order to eliminate this inconvenience, the gain of the feedback system (from the data hold register 24) to the adder circuit 23 may be made slightly smaller than flj to provide incomplete integration. 25 is D, which approximately corresponds to the D/A converter 6 in FIG.
/A converter, which returns the 15-bit PCM received data held in the data hold register 24 to an analog value. A low-pass filter 26 removes unnecessary high-frequency components from the output of the D/A converter 25, and an analog signal such as an audio signal is obtained as the output.

Further, 27 is a control sequencer section, which includes the above-mentioned sections, ie, the receiving circuit 20 and the shift clock generating section 21.
, the data decompression circuit 22, the data hold register 24, etc., in order to operate each part in a predetermined manner at a predetermined timing, a control signal is given to each part, and the number of pins 1 to 1 when separating the main data of the receiving circuit 20 described above is applied. control.

Next, the operation in the above-described configuration will be explained.

First, on the transmitting side, an analog original signal (for example, an audio signal) is converted into PCM code data (15 bits) by an A/D converter 1, and then delayed by a sample delay circuit 2.
The difference with the data before the sample is calculated by the subtractor 3 and the DP
It is converted into CM code data (16 bits).

This data is given to the scale detection circuit 15, and the maximum difference is determined from one block of DPCM code data consisting of a predetermined number of samples.Differences can be positive or negative, so to be precise, the absolute value of the difference, that is, the value with the largest difference) is the maximum difference. The scale value (digit shift information) data (4 bits) corresponding to the maximum difference is output from the scale detection circuit 15.

The set scale (direct output) of this scale detection circuit 15 is updated for each block and becomes scale value data common to one block of DPCM code data.

In order to correct this time lag in scale information detection, the DPCM code data delayed by one block in the block delay circuit 14 is sequentially compressed in the compression encoder 16 and the accumulator correction circuit 17 according to the scale value.

That is, in the compression encoder 16, the data corresponding to the transmission digits of the DPCM code data delayed by one block in the block delay circuit 14, that is, the data in the transmission bit length portion at the Hr position corresponding to the scale value set in the scale detection circuit 15. The compressed data is extracted, and the lower digits at this time are added to the accumulator. The compressed data and the carry information of the accumulator are given to the accumulator correction circuit 17, and only when it is determined that the compressed data and the carry information cause an automatic flow in the transmission digit, a preset accumulator correction circuit 17 is applied. - is given from the accumulator correction circuit 17 to the compression encoder 16.Compression encoder 1
6, when an accumulator correction pattern is given, replaces the accumulator correction pattern with the contents held in the accumulator at that time and stores it in the accumulator, and outputs the compressed data held at that time as the transmission main data. If the accumulator correction pattern is given and 1t is 0, the compression encoder 16 adds the carry to the compressed data as transmission main data if there is a carry within the (transmission 1tr) of the accumulator. If not, the compressed data is output as is as the transmission main data.

This main data and scale information data are sent to the transmission system via the transmission circuit 18. It goes without saying that the main data string may be subjected to time axis compression or other processing as necessary in order to insert scale information data during verse division and synthesis in the transmission circuit 18.

While PCM transmits a value that includes a code from a reference level, such as the O level, DPCM transmits the difference between samples, so if the frequency of the audio signal is very high compared to the sampling period, it may not be correct. The difference between the vicinity of the peak value and the vicinity of the negative peak value may become the DPCM code. Therefore, the maximum pitch 1 to number of DPCM code data is
One bit more is required than the M code data. Therefore, in the above, 16-bit DPCM code data is obtained from 15-bit PCM code data, and the scale values for transmitting this as 8- and 9-bit main data are 9 types, including cases where digit shift is not required, and 4-bit This is scale information data.

The operation of the receiving side that receives the transmission data sent to the transmission system in this manner will be explained.

In this case, the transmission signal given from the transmission system is 8-bit main data consisting of compressed DPCM codes that are serialized and time-division multiplexed, and 4-bit I-bit data for each data block.
It consists of scale information data. In the receiving circuit 20 to which this transmission signal is applied, the received signal is separated into information data and main data, and both of these data are parallelized and outputted respectively. Specifically, for example, scale information is first separated and extracted from the received signal for each block (for example, based on synchronization data added as necessary), and then 8-bit data following the scale information data is extracted. is sequentially extracted as main data during the period of that block, that is, until the next separate extraction of scale information.

These reception main data and reception scale information data are inputted from the reception circuit 20 to the data expansion circuit 22 and shift 1-clock generation section 21, respectively. Shift] - The clock generator 21 outputs a shift clock corresponding to the received scale information data, and these shift clocks are given to the data decompression circuit 22 to perform digit shift l on the 8-bit received main data.
-(A bit shift (-) is applied, and in the case of a 2-s complement I~ code, the upper bits are filled with polarity bits, and the data is converted into 16-bit DPCM reception data.

At this time, 0 data, for example, is added to the lower blank pix generated by the digit shift. This DPCM reception data is given to the adder circuit 23, and the data bold register 2
It is added to the output data of the adder circuit 23 one sample before, which is held at 4. That is, the output data of this adder circuit 23 is the cumulative (integrated) value of the DPCM reception data, that is, 15-bit PCM reception data. This PCM reception data is sequentially D/A converted by a D/A converter 25 via a data hold register 24, and unnecessary high frequency components are removed by a low pass filter 26, and output as an analog signal such as an audio signal. .

In this way, the transmitting side can accumulate the truncation part, that is, the digit loss part, and transmit the transmission data that is almost reflected in the subsequent transmission data, and the receiving side can receive this data and perform effective decoding and demodulation. Therefore, by simply transmitting 8-bit main data, it is possible to achieve an accuracy equivalent to reception at 9 bits or more.

As mentioned above, when compressing data, for example, transmission data is 2'
By temporarily changing the logic of the accumulator, we can prevent an extremely undesirable overflow (in which case the polarity will not be reversed in the case of completion).
This can be extremely effectively and completely prevented without complicating the hardware, and high-efficiency PCM transmission that can be transmitted using a small number of bits can be effectively realized 1'.

It should be noted that the present invention is not limited to the embodiments described above and shown in the drawings, but can be implemented with various modifications without changing the gist thereof.

Furthermore, the present invention is not limited to DPCM, but may be used for normal PCM compression, and may use substantially the same accumulator operation as the above embodiment on the transmitting side. Needless to say, it can be applied to any system.

That is, the present invention exhibits the greatest effect when used in the DPCM system. Because D P C'M
This is because an integrator is required for reception, and the present invention uses an accumulator operation to ensure that the integrated value is approximately correct during transmission.

However, even when data compression transmission is performed using the present invention in a normal PCM system, the de-emphasis circuit on the receiving side performs an operation almost equivalent to an integrator to bring the data closer to the correct value. In addition to improving transmission accuracy by reducing overflow errors, important effects such as whitening of noise based on data being sent so that the integral value is correct can be obtained.

Furthermore, some or all of the digital processing functions described above may be replaced with other equivalent 48 functions, or may be realized using a computer.

Furthermore, the scale information is set by setting the standard of the bit position for main data retrieval (reversely, based on the upper 8 digits) as shown in Fig. 5 (a).
) is scale information "7", the same figure (b) is "6", the same figure (
c) may be set to "0" to make it into 2 brigadier generals.

Note that when the present invention is used to transmit stereo audio signals, various techniques used in ordinary digital audio techniques, such as alternately transmitting left and right channel transmission data to achieve time division multiplexing, can be used in conjunction with the present invention. Of course, it is okay to do so.

[Effects of the Invention] According to the present invention, when transmitting PCM code data with high precision using a small number of bits, the occurrence of overflow errors in the transmitted data is sufficiently suppressed, the transmission precision is further improved, and it is possible to achieve practical and measurement advantages. It is possible to provide a signal transmission method that provides satisfactory results and does not cause new problems such as complication of hardware.

[Brief explanation of the drawing]

FIG. 1 is a system block diagram for explaining an example of differential PCM, FIG. 2 is a system block diagram for explaining an example of data compression in PCM, and FIGS. 3 and 4 are diagrams for explaining the same example. , Figures 5 and 6 are diagrams for explaining the occurrence of an overflow error in the same example, and Figure 7 is a diagram for explaining the occurrence of an overflow error in the same example.
9 to 9 are diagrams for explaining the principles of the first to third embodiments of the present invention, respectively, FIG. 10 is a flowchart of processing in the fourth embodiment of the present invention, and FIGS.
FIG. 2 is a block diagram showing the configurations of the transmitting side and the receiving side, respectively, in J3 according to the fifth embodiment of the present invention. 1... A/D converter, 2... Sample delay circuit, 3
...Differentiator, 14...Block delay circuit, 15...
・Scale detection circuit, 16... Compression encoder, 1
7... Accumulator correction circuit, 18... Transmission 0 time mark, 20... Receiving circuit, 21... Shift clock generation section, 22... Data expansion circuit, 23... Adding circuit, 24 ...Data hold register, 25...D/
A converter, 26...low pass filter. Applicant's agent Patent attorney Takehiko Suzue

Claims (5)

[Claims] (1) Detect the maximum value in the block of the PCM code original data in units of data blocks consisting of data groups for each scheduled time, determine the scale value based on the detected value, and calculate the pitch corresponding to the scale value of the original data. Sequentially extracting the data of the scheduled number of bits from the 1st bit position, and determining whether overflow occurs in the data of the scheduled number of bits when adding the substantial lower residual data to the subsequent original data, If it is determined that no overflow will occur, the above addition is performed, and if it is determined that an overflow will occur, the above addition is not performed and processing is performed using a predetermined logic that does not substantially cause overflow, and the above original data is processed. Obtain main data that has a smaller number of pitches and generally prioritizes the upper effective pitches of the original data, transmit this main data and scale information indicating the scale value above through a transmission system, and receive it. A signal transmission method characterized in that received main data is transferred from pins 1 to shift l-L according to reception scale information to obtain reproduced data with the same number of bits as the original data. (2) When it is determined that an overflow will occur due to the addition, the predetermined logic that is performed in place of the above-mentioned fraud and does not substantially cause an A-buffer is to replace the lower residual data with a scheduled value and use it for subsequent processing. The signal transmission system according to claim 1, characterized in that: (3) When it is determined that an overflow will occur due to the addition, the predetermined logic that does not substantially cause an overflow, which is performed instead of the above addition, deletes the carry equivalent to the transmittance of the lower residual data and 2. The signal transmission method according to claim 1, wherein the signal transmission method is used for processing. (4) When it is determined that an overflow will occur due to the addition, the predetermined logic that is performed in place of the above addition and which does not substantially cause an A-H flow is to clear the previous lower-order residual data and 7. 2. The signal transmission system according to claim 1, wherein the remaining data digits are used for subsequent processing. (5) The signal transmission method according to any one of claims 1 to 4, wherein the PCM code original data is DPCM code data.