JPS6046525A - Active matrix panel with built-in drive circuit - Google Patents
Active matrix panel with built-in drive circuitInfo
- Publication number
- JPS6046525A JPS6046525A JP15545783A JP15545783A JPS6046525A JP S6046525 A JPS6046525 A JP S6046525A JP 15545783 A JP15545783 A JP 15545783A JP 15545783 A JP15545783 A JP 15545783A JP S6046525 A JPS6046525 A JP S6046525A
- Authority
- JP
- Japan
- Prior art keywords
- active matrix
- drive circuit
- thin film
- built
- matrix panel
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000011159 matrix material Substances 0.000 title claims description 28
- 239000010409 thin film Substances 0.000 claims description 22
- 239000010408 film Substances 0.000 claims description 16
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 13
- 229910052710 silicon Inorganic materials 0.000 claims description 13
- 239000010703 silicon Substances 0.000 claims description 13
- 239000000758 substrate Substances 0.000 description 12
- 239000010410 layer Substances 0.000 description 9
- 239000012535 impurity Substances 0.000 description 8
- 230000000295 complement effect Effects 0.000 description 7
- 229910052751 metal Inorganic materials 0.000 description 6
- 239000002184 metal Substances 0.000 description 6
- 239000004973 liquid crystal related substance Substances 0.000 description 5
- 238000010586 diagram Methods 0.000 description 4
- 239000011229 interlayer Substances 0.000 description 4
- 238000004519 manufacturing process Methods 0.000 description 3
- 239000003990 capacitor Substances 0.000 description 2
- 238000009413 insulation Methods 0.000 description 2
- 238000000034 method Methods 0.000 description 2
- 230000001681 protective effect Effects 0.000 description 2
- 229910000838 Al alloy Inorganic materials 0.000 description 1
- 239000003795 chemical substances by application Substances 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- AMGQUBHHOARCQH-UHFFFAOYSA-N indium;oxotin Chemical compound [In].[Sn]=O AMGQUBHHOARCQH-UHFFFAOYSA-N 0.000 description 1
- 229910044991 metal oxide Inorganic materials 0.000 description 1
- 150000004706 metal oxides Chemical class 0.000 description 1
- 150000002739 metals Chemical class 0.000 description 1
- 229910021421 monocrystalline silicon Inorganic materials 0.000 description 1
- 238000004904 shortening Methods 0.000 description 1
- 238000002834 transmittance Methods 0.000 description 1
Classifications
-
- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
- G02F1/1362—Active matrix addressed cells
- G02F1/1368—Active matrix addressed cells in which the switching element is a three-electrode device
-
- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/1333—Constructional arrangements; Manufacturing methods
- G02F1/1345—Conductors connecting electrodes to cell terminals
- G02F1/13454—Drivers integrated on the active matrix substrate
Landscapes
- Physics & Mathematics (AREA)
- Nonlinear Science (AREA)
- Liquid Crystal (AREA)
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Mathematical Physics (AREA)
- Chemical & Material Sciences (AREA)
- Crystallography & Structural Chemistry (AREA)
- General Physics & Mathematics (AREA)
- Optics & Photonics (AREA)
- Liquid Crystal Display Device Control (AREA)
Abstract
(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.
Description
【発明の詳細な説明】
本発明は、アクティブマトリクス液晶パネル、特にシフ
トレジスタ等の駆動回路を内蔵した透明基板より成るア
クティブマトリクス液晶パネルに関する。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an active matrix liquid crystal panel, and particularly to an active matrix liquid crystal panel comprising a transparent substrate incorporating a drive circuit such as a shift register.
近年、単結晶シリコン基板や透明基板にスイクチングト
ランジスタアレイを形成して成るアクティブマトリクス
パネルが開発され実用化されつつある。従来のアクティ
ブマトリクスパネル、特に薄膜トランジスタによる透明
形アクティブマトリクスパネルは、第1図(α)に示す
ごとく、スイクチングトランジスタアレイ104が形成
されたアクティブマトリクス基板101.対向電極10
3、及び、該アクティブマトリクス基板101と該対向
電極106との間に封入された液晶102とから成って
おり、シフトレジスタ等の駆動回路はすべてアクティブ
マトリクスパネルの外部に形成されていた。通常、画像
表示を前提としたアクティブマトリクス基板は、第1図
Ch)に示すごとくM本のゲート線i 、05 、 M
本のデータ線106、及び、それらの交点に形成された
MX11個の画素107,108,109,110.・
・・・・・より成り、ゲート線の本数Mは200本〜2
50本。In recent years, active matrix panels in which a switching transistor array is formed on a single crystal silicon substrate or a transparent substrate have been developed and are being put into practical use. A conventional active matrix panel, particularly a transparent active matrix panel using thin film transistors, has an active matrix substrate 101 on which a switching transistor array 104 is formed, as shown in FIG. 1(α). Counter electrode 10
3, and a liquid crystal 102 sealed between the active matrix substrate 101 and the counter electrode 106, and all drive circuits such as shift registers were formed outside the active matrix panel. Usually, an active matrix substrate intended for image display has M gate lines i, 05, M as shown in Fig. 1 (Ch).
Book data line 106 and MX11 pixels 107, 108, 109, 110 . . . formed at their intersections.・
..., and the number of gate lines M is 200 to 2.
50 bottles.
データ線の本数Nは100本〜250本程反である。従
って、アクティブマトリクスパネルには少なくともM+
N個の入力端子が必要であり、外部駆動回路との接続も
同数必要となる。従って、従来方式によると、アクティ
ブマトリクスパネルと外部駆動回路との接続部の占有体
積が大きくなり一パネルユニットの小型化・薄型化を妨
げる。また、外部駆動回路用LSIのチップコスト、実
装コストに起因して、パネルユニットのコスト増大を招
く。The number N of data lines is about 100 to 250 lines. Therefore, an active matrix panel has at least M+
N input terminals are required, and the same number of connections to external drive circuits are also required. Therefore, according to the conventional method, the volume occupied by the connection portion between the active matrix panel and the external drive circuit becomes large, which hinders miniaturization and thinning of one panel unit. Furthermore, the cost of the panel unit increases due to the chip cost and mounting cost of the LSI for the external drive circuit.
本発明は、前述のごとき、従来の薄膜アクティブマトリ
クスパネルが有していた欠点を解消し、小型かつ薄型で
しかも安価な、薄膜トランジスタによる、駆動回路内蔵
アクティブマトリクスパネルを提供することを目的とす
る。更に、本発明は、駆動回路を内蔵したことによる製
造工程の複雑化を排除し、画素アレイ部分と完全に同一
の工程で製造された駆動回路をアクティブマトリクス基
板内に内蔵することを目的とする。An object of the present invention is to eliminate the drawbacks of conventional thin film active matrix panels as described above, and to provide a small, thin, and inexpensive active matrix panel with a built-in drive circuit using thin film transistors. Furthermore, it is an object of the present invention to eliminate the complication of the manufacturing process due to the built-in drive circuit, and to incorporate the drive circuit manufactured in the completely same process as the pixel array part into the active matrix substrate. .
以下、実施例に基づいて、本発明の特徴、構成及び作用
を詳述する。Hereinafter, the features, configuration, and operation of the present invention will be explained in detail based on Examples.
第2図(α)に、本発明の駆動回路内蔵アクティブマト
リクスパネルの構成の一例を示す。同図において、G1
.G2.G3.・・・・・・、GMはゲート線でその本
数はM本であり、DI、D2.D5、・・・・・・、D
Nはデータ線でその本数はM本である。また、201.
202,203.:204等は、第2図Cb)に示すご
とく、簿膜トランジスタ(以下、薄膜トランジスタをT
PTと略記する。)251、液晶容M252等より成る
画素であり、画素がマトリクス状に配列されて表示部2
05が形成される。206,207はアクティブマトリ
クス基板208上に形成された駆動回路である。FIG. 2 (α) shows an example of the configuration of an active matrix panel with a built-in drive circuit according to the present invention. In the same figure, G1
.. G2. G3. . . . GM is a gate line, the number of which is M, and DI, D2 . D5,...,D
N is a data line, the number of which is M. Also, 201.
202, 203. :204 etc. are thin film transistors (hereinafter referred to as thin film transistors) as shown in Figure 2Cb).
It is abbreviated as PT. ) 251, a liquid crystal container M252, etc., and the pixels are arranged in a matrix to form the display section 2.
05 is formed. 206 and 207 are drive circuits formed on the active matrix substrate 208.
206はゲートat駆動回路であり、その具体的な回路
構成例を第3図(α)及び同図Cb)に示す。第6図(
α)は、P型TFTのみ又はN型TFTのみを構成要素
とするダイナミックシフトレジスタであり、同図におい
て、301.502はクロックライン、303はコモン
電位を与えるライン、304,305,306,307
,308はいずれも同一極性のTPTである。声だし、
308はソースとドレインが接続されたMO8容量とし
て動作する。第3図Ch)は、相補型ダイナミックシフ
トレジスタであり、同図において、311.312はク
ロックライン、313はデータ入力端子を示す。また、
P W T I’ T 314とN型TFT315は相
補型アナログスイッチを形成し、316は相補型インバ
ータである。一方、第2図において、207はデータ線
駆動回路であり、その具体的な回路構成例を第4図(α
)、及び同図Ch)に示す。データ線駆動回路は、シフ
トレジスタとアナログスイッチとから成り映像信号のサ
ンプルホールドを行なう。第4図(α)+[1tl−t
i性のTIFTにより構成されたダイナミックシフトレ
ジスタであり、同図において、401及び402はクロ
ックライン、403はデータ入力端子、404はコモン
電位を与えるライン、405,406及び407は映像
信号ライン、408,409.410,411.412
は同一極性のTPTである。ここで、ZFT411はソ
ースとドレインが接続されたMOB容量として動作し、
TFT412はアナログスイッチとして動作する。第4
図Cb)は、相補型ダイナミックシフトレジスタと相補
型アナログスイッチとから成る。同図において、421
.422はクロックライン、423はデータ入力端子、
424,425及び426は映像信号ラインである。P
型T Il”T 427及びN型TFT428は相補型
アナログスイッチを形成し、429及び430は相補型
インバータであり、P型TFT431とN型TFT45
2とでサンプルホールド用アナログスイッチを形成して
いる本発明の第一の特徴は、上述のごとく、駆動回路を
薄i%積回路としてアクティブ寸トリクス基板内に作り
込むことにあるが、更に、第二の特徴は、前記薄膜集積
回路内のすべての配線をシリコン薄膜及び透明導電膜例
えば、’x T O(インジウム・ティン・オキサイド
) を用いて形成することにある。第5図は、配’tm
P?jとしてシリコン薄膜及び透明導電膜の他に金属−
例えばアルミニウム合金−を用いた薄膜集積回路の構造
の一例を示す図である。同図において、501は絶縁基
板、502は不純物ドープされた第一のシリコン簿膜、
503は不純物ドープされていないか、502の逆極性
に不純物ドープされた第一のシリコン薄膜、504はゲ
ート酸化膜、505は不純物ドープされた第二のシリコ
ン薄膜であり、512の部分にTPTが形成されている
。506は第一の層間絶縁膜、507は第一のコンタク
トホール、508は金属配線層、509は前記金属配線
層の保護膜を兼ねた第二の層間絶縁力庭、510は第二
のコンタクトホール、511は透明導電膜である。透明
導電膜511は液晶を駆動する駆動電極であり、アクテ
ィブマトリクスパネルに不可欠のものである。透明導電
膜は、金属層に比べ層間絶縁j腐との密着性に優れ、簡
つきにくいため、機械的な配向処理工程にも耐えられ、
保護膜を必要としない。本発明の駆動回路内蔵アクティ
ブマトリクスパネルは、第5図のごとき構造にて形成し
ても構わないが、第6図のごとき構造にて形成すること
により、一層少ない工程数で安価に製造される。第6図
において、601は絶縁基板、602は不純物ドープさ
れた第一のシリコン薄膜、603は不純物ドープされて
いないか602と逆極性に不純物ドープされた第一のシ
リコン薄膜、604はゲート酸化膜、605は不純物ド
ープされた第二のシリコン薄°膜であり、609の部分
にTPTが形成されている。606は層間絶縁膜、60
7はコンタクトホール、608は透明導電j莫である。Reference numeral 206 denotes a gate AT drive circuit, and a specific example of the circuit configuration thereof is shown in FIG. 3(α) and FIG. 3Cb). Figure 6 (
α) is a dynamic shift register that includes only P-type TFTs or only N-type TFTs, and in the figure, 301.502 is a clock line, 303 is a line that provides a common potential, and 304, 305, 306, 307
, 308 are TPTs of the same polarity. It's a voice,
308 operates as an MO8 capacitor whose source and drain are connected. Fig. 3 (Ch) shows a complementary dynamic shift register, in which 311 and 312 indicate a clock line, and 313 indicates a data input terminal. Also,
P W T I' T 314 and N-type TFT 315 form a complementary analog switch, and 316 is a complementary inverter. On the other hand, in FIG. 2, 207 is a data line drive circuit, and a specific example of its circuit configuration is shown in FIG.
) and Ch) in the same figure. The data line drive circuit includes a shift register and an analog switch, and samples and holds the video signal. Figure 4 (α) + [1tl-t
This is a dynamic shift register composed of i-type TIFTs. In the figure, 401 and 402 are clock lines, 403 is a data input terminal, 404 is a line that provides a common potential, 405, 406, and 407 are video signal lines, and 408 ,409.410,411.412
are TPTs of the same polarity. Here, the ZFT411 operates as a MOB capacitor whose source and drain are connected,
TFT 412 operates as an analog switch. Fourth
Figure Cb) consists of a complementary dynamic shift register and a complementary analog switch. In the same figure, 421
.. 422 is a clock line, 423 is a data input terminal,
424, 425 and 426 are video signal lines. P
Type T Il"T 427 and N type TFT 428 form a complementary analog switch, 429 and 430 are complementary inverters, and P type TFT 431 and N type TFT 45
2 to form a sample and hold analog switch.As mentioned above, the first feature of the present invention is that the drive circuit is built into the active matrix board as a thin i% product circuit. A second feature is that all wiring within the thin film integrated circuit is formed using a silicon thin film and a transparent conductive film, such as 'xT O (indium tin oxide). Figure 5 shows the layout
P? In addition to silicon thin films and transparent conductive films, metals are used as j.
1 is a diagram showing an example of the structure of a thin film integrated circuit using, for example, an aluminum alloy. In the figure, 501 is an insulating substrate, 502 is a first silicon film doped with impurities,
503 is a first silicon thin film that is not doped with impurities or is doped with impurities of the opposite polarity to 502, 504 is a gate oxide film, 505 is a second silicon thin film that is doped with impurities, and TPT is provided in the portion 512. It is formed. 506 is a first interlayer insulating film, 507 is a first contact hole, 508 is a metal wiring layer, 509 is a second interlayer insulation film that also serves as a protective film for the metal wiring layer, and 510 is a second contact hole. , 511 is a transparent conductive film. The transparent conductive film 511 is a drive electrode that drives the liquid crystal, and is essential for an active matrix panel. Transparent conductive films have superior adhesion to interlayer insulation layers compared to metal layers, and are difficult to manipulate, so they can withstand mechanical alignment processes.
Does not require a protective film. The active matrix panel with a built-in drive circuit of the present invention may be formed with the structure shown in FIG. 5, but by forming it with the structure shown in FIG. 6, it can be manufactured at a lower cost with fewer steps. . In FIG. 6, 601 is an insulating substrate, 602 is a first silicon thin film doped with impurities, 603 is a first silicon thin film that is not doped with impurities or is doped with impurities of opposite polarity to 602, and 604 is a gate oxide film. , 605 is a second silicon thin film doped with impurities, and TPT is formed in a portion 609. 606 is an interlayer insulating film, 60
7 is a contact hole, and 608 is a transparent conductor.
第6図において、’ T P Tは第一のシリコン薄膜
層中にソース・ドレインが形成される。また、同図にお
いて、いかなる配線も、シリコン薄膜層又は透OA導電
族層により形成されている。アクティブマトリクス基板
を第6図のごとく、金属を用いずに形成することにより
、製造工程の短縮による低コスト化、パネルの透過率の
向上、各層間のコンタクト特性の向上がもたらされる。In FIG. 6, a source/drain is formed in the first silicon thin film layer. Further, in the figure, any wiring is formed of a silicon thin film layer or a transparent OA conductive group layer. By forming the active matrix substrate without using metal as shown in FIG. 6, it is possible to reduce costs by shortening the manufacturing process, improve the transmittance of the panel, and improve the contact characteristics between each layer.
(第5図の構造によると金属層の表面に金属酸化物、例
えばAL。(According to the structure shown in FIG. 5, a metal oxide such as AL is formed on the surface of the metal layer.
0、が形成されやすく、透明導電膜とのコンタクト特性
が良好ではない。)第6図の構造をもつ薄膜集積回路は
、以上のごとき長所を有する反面、第3図(α)、Ch
)#第4図(α) l (iのクロックライン、映像信
号ライン、電源ラインをもシート抵抗の高いシリコンN
膜、透明導電膜で形成しなくてはならないという欠点を
有する。しかしながら、アクティブマトリクス基板の周
辺には配線スペースが十分に広く存在するため、パター
ン上において配線幅を大きく取ることが可能であり前述
の欠点は完全に解消される。0 is likely to be formed, and the contact characteristics with the transparent conductive film are not good. ) Although the thin film integrated circuit having the structure shown in Fig. 6 has the above-mentioned advantages, it has the disadvantages of Fig. 3 (α), Ch
) #Figure 4 (α) l (The i clock line, video signal line, and power supply line are also made of silicon N with high sheet resistance.
It has the disadvantage that it must be formed of a transparent conductive film. However, since there is a sufficiently wide wiring space around the active matrix substrate, it is possible to have a large wiring width on the pattern, and the above-mentioned drawbacks are completely eliminated.
以上に述べたごとく、本発明を適用することにより、小
型かつ薄型で高性能の駆動回路内蔵アクティブマトリク
スパネルが簡単なfM造工程で得られる。このようにし
て得られた駆動回路内蔵アクティブマトリクスパネルは
、映像信号と同期信号を与えるだけで任意の映像を表示
することが可能な超小型パネルユニットへの応用が期待
される。As described above, by applying the present invention, a small, thin, and high-performance active matrix panel with a built-in drive circuit can be obtained through a simple fM manufacturing process. The active matrix panel with a built-in drive circuit thus obtained is expected to be applied to an ultra-small panel unit that can display any image by simply applying a video signal and a synchronization signal.
第1図(α)l Cb)は従来のアクティブマトリクス
パネルを説明するための図。
好2図(a)、(A)は、本発明の概略構成を説明する
ための図。
第3図(α) # (’) 、第4図(α)I Cb)
、第5図、第6図は、本発明の具体的な実施例を説明す
るための図。
以上
出願人 株式会社諏訪精工舎
代理人 弁理士 最上 務
(Aノ
(b)
G1 G2 G!5
(σ、)
(トノ
第3図FIG. 1(α)lCb) is a diagram for explaining a conventional active matrix panel. Figures 2 (a) and (A) are diagrams for explaining the schematic configuration of the present invention. Figure 3 (α) # ('), Figure 4 (α) I Cb)
, FIG. 5, and FIG. 6 are diagrams for explaining specific embodiments of the present invention. Applicant Suwa Seikosha Co., Ltd. Agent Patent Attorney Tsutomu Mogami (A no (b) G1 G2 G!5 (σ,) (Tono Figure 3)
Claims (1)
データ線との交点に形成された薄膜トランジスタアレイ
及び薄膜トランジスタにより構成された駆動回路を具備
して成ることを特徴とする駆動回路内蔵アクティブマト
リクスパネル。 2 前記薄膜トランジスタのソース・ドレインがシリコ
ン薄膜で形成されるとともに、前記ゲート線、データ線
及び駆動回路内のすべての配線はシリコン薄膜及び透明
導電膜により形成されて成ることを特徴とする特許請求
の範囲第1項記載の駆動回路内蔵アクティブマトリクス
パネル。[Claims] 1. A drive circuit comprising a plurality of gate lines, a plurality of data lines, a thin film transistor array formed at the intersection of the gate lines and the data lines, and a drive circuit composed of the thin film transistors. Active matrix panel with built-in drive circuit. 2. The source and drain of the thin film transistor are formed of a silicon thin film, and the gate line, data line, and all wiring in the drive circuit are formed of a silicon thin film and a transparent conductive film. An active matrix panel with a built-in drive circuit as described in Scope 1.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP15545783A JPS6046525A (en) | 1983-08-25 | 1983-08-25 | Active matrix panel with built-in drive circuit |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP15545783A JPS6046525A (en) | 1983-08-25 | 1983-08-25 | Active matrix panel with built-in drive circuit |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS6046525A true JPS6046525A (en) | 1985-03-13 |
Family
ID=15606460
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP15545783A Pending JPS6046525A (en) | 1983-08-25 | 1983-08-25 | Active matrix panel with built-in drive circuit |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS6046525A (en) |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5885740A (en) * | 1996-09-27 | 1999-03-23 | Titan Kogyo Kabushiki Kaisha | Magnetite particles, a process for producing them and applications thereof |
KR100285303B1 (en) * | 1991-09-05 | 2001-04-02 | 이데이 노부유끼 | LCD Display |
-
1983
- 1983-08-25 JP JP15545783A patent/JPS6046525A/en active Pending
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR100285303B1 (en) * | 1991-09-05 | 2001-04-02 | 이데이 노부유끼 | LCD Display |
US5885740A (en) * | 1996-09-27 | 1999-03-23 | Titan Kogyo Kabushiki Kaisha | Magnetite particles, a process for producing them and applications thereof |
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