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JPS6041244A - Enclosure for semiconductor device - Google Patents

Enclosure for semiconductor device

Info

Publication number
JPS6041244A
JPS6041244A JP58149886A JP14988683A JPS6041244A JP S6041244 A JPS6041244 A JP S6041244A JP 58149886 A JP58149886 A JP 58149886A JP 14988683 A JP14988683 A JP 14988683A JP S6041244 A JPS6041244 A JP S6041244A
Authority
JP
Japan
Prior art keywords
enclosure
ceramic
envelope
semiconductor device
conductive pattern
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP58149886A
Other languages
Japanese (ja)
Inventor
Takemi Sato
佐藤　竹美
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP58149886A priority Critical patent/JPS6041244A/en
Publication of JPS6041244A publication Critical patent/JPS6041244A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/492—Bases or plates or solder therefor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/02—Containers; Seals
    • H01L23/04—Containers; Seals characterised by the shape of the container or parts, e.g. caps, walls
    • H01L23/053—Containers; Seals characterised by the shape of the container or parts, e.g. caps, walls the container being a hollow construction and having an insulating or insulated base as a mounting for the semiconductor body
    • H01L23/055—Containers; Seals characterised by the shape of the container or parts, e.g. caps, walls the container being a hollow construction and having an insulating or insulated base as a mounting for the semiconductor body the leads having a passage through the base
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32153—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being arranged next to each other, e.g. on a common substrate
    • H01L2224/32175—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being arranged next to each other, e.g. on a common substrate the item being metallic
    • H01L2224/32188—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being arranged next to each other, e.g. on a common substrate the item being metallic the layer connector connecting to a bonding area protruding from the surface of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48135—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/48137—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being arranged next to each other, e.g. on a common substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/4823—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a pin of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484—Connecting portions
    • H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
    • H01L2224/48464—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond the other connecting portion not on the bonding area also being a ball bond, i.e. ball-to-ball
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01082—Lead [Pb]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/12—Passive devices, e.g. 2 terminal devices
    • H01L2924/1204—Optical Diode
    • H01L2924/12041—LED
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/156—Material
    • H01L2924/15786—Material with a principal constituent of the material being a non metallic, non metalloid inorganic material
    • H01L2924/15787—Ceramics, e.g. crystalline carbides, nitrides or oxides
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/161—Cap
    • H01L2924/1615—Shape
    • H01L2924/16195—Flat cap [not enclosing an internal cavity]

Landscapes

  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Die Bonding (AREA)
  • Lead Frames For Integrated Circuits (AREA)

Abstract

PURPOSE:To obtain an enclosure of a semiconductor device having simple manufacturing steps and structure by forming to fix a metal portion integral with external leads to protrude from the outside to the inside of the member into a plurality of holes passing through a ceramic material. CONSTITUTION:A ceramic member 11 is shaped so that the bottom of the enclosure is integral with the side, and holes 18 passing through the both surfaces are formed at the bottom. A metal portion 19 formed to match to the hole 18 is formed integral with external lead 16. A conductive pattern 15 is formed on the bottom of the member 11, i.e., the surface to become the outside of the enclosurer. The lead 16 is connected by a brazing material 17 to the pattern 15. Fine metal wirings 22 for the wirings led from the electrode on a semiconductor element 21 are connected to the surface 20 exposed in the enclosure of the portion 19. The pattern 15 may be formed only one surface of the member 11, the manufacturing steps of the enclosure are simplified, and the electric circuit is simplified.

Description

【発明の詳細な説明】 本発明は高周波で使用される半導体装置の外囲器の構造
に関するものである。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to the structure of an envelope of a semiconductor device used at high frequencies.

高周波で使用される半導体装置の外囲器に高周波電力の
損失を小さくするために一般にセラミックを主体として
構成されているが外囲器そのものが高周波回路の一部を
形成している場合があり、高周波的に構造を考慮する必
要がある・第１図は従来１更用されている高周波用半導
体装置の外囲器の構造を示す断面図である。半導体素子
】０と外囲器の外部リード６との接続をするために外囲
器を構成するセラミック基板１の外囲器内面に半導体素
子ｌＯおよび電極配線９を接続するための４電性パター
ン３をその反対の面に外部リード６との接続のための導
電性パターン５とを形成し、両面のパターン３および５
を接続するためにセラミック基板ｌの′１１１１Ｊ面に
さらｒＣ導電性パターン４を形成している。導電性パタ
ーン５と外部リード６とはロー材７でロー付けされてい
る。セラミック基板１の周辺上部にはやはりセラミック
の壁部材２を有し、セラミック又は金属の蓋部材８で内
部が封止されている。このような外囲器においては、セ
ラミック基板ｌの両面と側面の３箇所に導電性パターン
３．　４．　５を形成しているため、外囲器の製造工程
が複雑になる。又高周波回路としても半導体素子１０を
接続する導電性パターン３から外部リード６までの回路
が複雑となってしまう。Envelopes of semiconductor devices used at high frequencies are generally mainly made of ceramic to reduce loss of high-frequency power, but the envelope itself may form part of the high-frequency circuit. It is necessary to consider the structure from a high-frequency perspective. FIG. 1 is a sectional view showing the structure of an envelope of a high-frequency semiconductor device that has been used in the past. Semiconductor element 10 and the outer lead 6 of the envelope are connected to each other on the inner surface of the envelope of the ceramic substrate 1 constituting the envelope. A conductive pattern 5 for connection with an external lead 6 is formed on the opposite side of the conductive pattern 3, and patterns 3 and 5 on both sides are formed.
Further, an rC conductive pattern 4 is formed on the '1111J surface of the ceramic substrate 1 for connection. The conductive pattern 5 and the external lead 6 are brazed with a brazing material 7. A ceramic wall member 2 is also provided on the upper periphery of the ceramic substrate 1, and the inside thereof is sealed with a ceramic or metal lid member 8. In such an envelope, conductive patterns 3. 4. 5, the manufacturing process for the envelope becomes complicated. Further, as a high frequency circuit, the circuit from the conductive pattern 3 connecting the semiconductor element 10 to the external lead 6 becomes complicated.

本発明はこの様な欠点をなく１〜、製造工程と構造が単
純な半導体装置の外囲器を提供するものである。本発明
によれば、半導体装置の外囲器において、セラミック基
板の同一面内に貢通ずる複数個の穴を設け、外囲器の外
側になるセラミック基板の面＜４を性パターンｆ形成し
、外部リード一体となった金属がその穴の内部にセラミ
ックの外１１１１の面から突き出るようにセラミック基
板に接着固定されている構造の外囲器を得る。The present invention eliminates these drawbacks and provides an envelope for a semiconductor device which has a simple manufacturing process and simple structure. According to the present invention, in an envelope of a semiconductor device, a plurality of holes communicating with each other are provided in the same surface of a ceramic substrate, and a surface <4 of the ceramic substrate that is outside the envelope is formed with a pattern f, To obtain an envelope having a structure in which the metal integrated with the external lead is adhesively fixed to the ceramic substrate so as to protrude from the surface of the ceramic exterior 1111 inside the hole.

次に、図面を参照１５．て本発明をより詳細に説明する
。第２図ａ本発明による実施例を示す断面図である。セ
ラミック部材１１け外囲器の底面と側面が一体となるよ
うに整形されており、この底面に両表面にＷ通する穴１
８ｆｔ設けである。外部リード１６にはに通人１８に合
わせてつくられた金属部分１９が一体となるように形成
されている。Next, refer to the drawings15. The present invention will now be described in more detail. FIG. 2a is a sectional view showing an embodiment according to the present invention. The bottom and side surfaces of the 11-piece ceramic envelope are shaped so that they are integrated, and a hole 1 is formed in the bottom to allow W to pass through both surfaces.
It is set at 8ft. A metal portion 19 made to fit the passer 18 is integrally formed with the external lead 16.

セラミック部材１１の底面、すなわち、外囲器の外側に
なる面ＶＣ＃−ｊ４電性パターン１５が形成されており
、この導電性パターン１５にロー材１７ＶＣよって外部
リード１６が接続されている。半導体素子２１および半
導体素子２１上の電極から導出される耐融用金属細線２
２は外部リード１６に一体となった金属部分】９の外囲
器の内部１Ｃ露出した面２０に接続される◎上２４フ２
部材１１上面には金属又はセラミックの蓋部材２３が接
着されて半導体素子２１を封止している。A VC#-j4 conductive pattern 15 is formed on the bottom surface of the ceramic member 11, that is, the surface facing outside the envelope, and an external lead 16 is connected to this conductive pattern 15 by a brazing material 17VC. Semiconductor element 21 and melt-resistant thin metal wire 2 derived from the electrode on semiconductor element 21
2 is a metal part integrated with the external lead 16] Connected to the exposed surface 20 of the inside 1C of the envelope of 9 ◎ Upper 24 F2
A metal or ceramic lid member 23 is adhered to the upper surface of the member 11 to seal the semiconductor element 21.

本発明の構造によれば、セラミック部材１１に設ける導
電性パターン１５はセラミック部材】１の一面のみに形
成すればよく外囲器の製造工程は簡略化され、電気的な
回路も単純化される効果を得ることができる。According to the structure of the present invention, the conductive pattern 15 provided on the ceramic member 11 only needs to be formed on one side of the ceramic member 1, and the manufacturing process of the envelope is simplified, and the electrical circuit is also simplified. effect can be obtained.

以上述べた実施例では、セラミック部材１１に導電性パ
ターン１５を形成する構造であるが、不発明の構造にお
いては外部リード１６と半導体素子２１との接続部であ
る金属部分１９とを含む金属がセラミック部材１１に接
続されていればよいのであって、導電性パターン１５は
必ず１−も必要ではない。また、外部リード１６と半導
体素子２１との接続部である金属部分１９とを含む金属
とセラミック部材１１０貫通穴との対は３箇以上あって
もよいことはいう゛までもない。In the embodiment described above, the conductive pattern 15 is formed on the ceramic member 11, but in the uninvented structure, the metal including the metal portion 19 which is the connection portion between the external lead 16 and the semiconductor element 21 is formed. It is sufficient that the conductive pattern 15 is connected to the ceramic member 11, and the conductive pattern 15 does not necessarily need to be 1-. Furthermore, it goes without saying that there may be three or more pairs of through-holes in the ceramic member 110 and metal including the metal portion 19 that is the connecting portion between the external lead 16 and the semiconductor element 21.

【図面の簡単な説明】[Brief explanation of the drawing]

第１図は従来の半導体装１ｄの外囲器の構造を示す断面
図であり、第２図は不発明の一実施例による半導体装置
の外囲６（の構造を示す断面図である。 １・・・・・・セラミック基板、２・・・・・・壁部材
、３．４゜５．１５・・・・・・導電性パターン、６．
１６・・・・・・外部リード、７１１７・・・・・・ロ
ー材、８．２３・・・・・・蓋部材、９・・・・・・金
属細線、１０．２１・・・・・・半導体素子、１１・・
・・・・セラミック部材、１８・・・・・・貫通穴、１
９・・・・・・金属部分、２０・・・・・・半導体素子
との接続面。 代理人　升理士　内　原　晋 　５− 気！閃FIG. 1 is a sectional view showing the structure of an envelope of a conventional semiconductor device 1d, and FIG. 2 is a sectional view showing the structure of an envelope 6 of a semiconductor device according to an embodiment of the invention. ... Ceramic substrate, 2 ... Wall member, 3.4°5.15 ... Conductive pattern, 6.
16... External lead, 7117... Brazing material, 8.23... Lid member, 9... Thin metal wire, 10.21...・Semiconductor element, 11...
...Ceramic member, 18...Through hole, 1
9...Metal part, 20... Connection surface with semiconductor element. Agent Susumu Uchihara 5- Ki! flash

Claims (1)

【特許請求の範囲】[Claims] セラミック部材に貫通する複数個の穴をもち、外部リー
ドと一体となった金属部分がその穴の内部にセラミック
部材の外側から内部に突き出るように前記セラミック部
材に固定されている構造を有することを特徴とする半導
体装置用外囲器。The ceramic member has a structure having a plurality of holes penetrating through the ceramic member, and a metal part integrated with an external lead is fixed to the ceramic member so as to protrude from the outside to the inside of the ceramic member. Features: Envelopes for semiconductor devices.
JP58149886A 1983-08-17 1983-08-17 Enclosure for semiconductor device Pending JPS6041244A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP58149886A JPS6041244A (en) 1983-08-17 1983-08-17 Enclosure for semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP58149886A JPS6041244A (en) 1983-08-17 1983-08-17 Enclosure for semiconductor device

Publications (1)

Publication Number Publication Date
JPS6041244A true JPS6041244A (en) 1985-03-04

Family

ID=15484783

Family Applications (1)

Application Number Title Priority Date Filing Date
JP58149886A Pending JPS6041244A (en) 1983-08-17 1983-08-17 Enclosure for semiconductor device

Country Status (1)

Country Link
JP (1) JPS6041244A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0577731A1 (en) * 1991-03-29 1994-01-12 Olin Corporation Surface mount device with high thermal conductivity
JPH062036U (en) * 1991-02-08 1994-01-14 正 星野 Fire conditioner
US8450842B2 (en) 2007-03-20 2013-05-28 Kyocera Corporation Structure and electronics device using the structure

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH062036U (en) * 1991-02-08 1994-01-14 正 星野 Fire conditioner
EP0577731A1 (en) * 1991-03-29 1994-01-12 Olin Corporation Surface mount device with high thermal conductivity
EP0577731A4 (en) * 1991-03-29 1994-01-19 Olin Corporation
US8450842B2 (en) 2007-03-20 2013-05-28 Kyocera Corporation Structure and electronics device using the structure

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