JPS6040717B2 - semiconductor equipment - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a semiconductor device, and particularly to a vertical double-diffused insulated gate field effect transistor having a gate portion formed within a structure provided on the surface of a semiconductor substrate.

FIG. 1 shows a cross section of a main part of a conventional V-groove vertical double-diffused insulated gate field effect transistor, and shows an N-channel type transistor.

Usually, in this case, N
A P-type impurity is diffused to a required depth over the entire surface of one main surface la of a semiconductor substrate 1 of the type to form a base region 3, and an N-type impurity is selectively diffused into this region 3. Second
A source region 4 is formed as shown in the figure. Then, a groove 5 having a V-shaped cross section is formed by cutting across the source region 4 from the side of the main surface la of the substrate 1 and cutting through the base region 3 below it to reach the drain region 1 below it. This groove 5
Inside, a gate insulating layer 6 is deposited at least on the base region 3 facing into the trench 5, and a gate electrode 7 is deposited on this. A source electrode 8 is ohmicly deposited on the source region 4, and this source electrode 8 is normally deposited over the base region 3.

Although the drain electrode is not shown, the other main surface lb of the base 1
installed on the side. Note that an N-type low resistivity region 2' is formed on the surface 1b side of the base 1 by, for example, full-surface diffusion.
In the field effect transistor having such a configuration, the effective length ff of the channel formed on the surface of the base region 3 facing into the groove 5 between the source region 4 and the drain region 2 under the gate insulating layer 5 is equal to that of the base region. Corresponding to the difference L between the diffusion depths of regions 3 and 4, it can be defined by defining the diffusion depths of these regions 3 and 4, and this can be defined by selecting a small value. 4. can be selected and the high frequency characteristics can be improved.

However, even in a field effect transistor with such a configuration, the channel length ff is
and 4 is large compared to the difference L in the diffusion depth,
This channel length LeH cannot be selected to be sufficiently small. This is based on the fact that the side surfaces of the V-shaped groove 5 do not follow the thickness direction of the base body 1 but have a required width, that is, they do not cross the base region 3 at the shortest distance but diagonally.
In other words, P between the source region 4 and the base region 3
This is based on the fact that the side surfaces of the groove 5 are not perpendicular to the N junction plane J, and the PN junction plane (J) between the base region 3 and the drain region 2. Incidentally, this groove 5 is usually formed by crystal orientation etching in order to have a uniform shape. That is, a silicon slice with, for example, a 10-groove crystal plane is used as the substrate 1, and this is subjected to crystal orientation etching to form a V with the 111 crystal plane as the side surface where the etching mainly proceeds.
A groove is formed, and since the angle at the bottom of this V-shaped groove is the angle 700 formed by the two 111 crystal planes, ff/L' is about 1.25. Therefore, in this structure, if a sufficiently small channel length ff is to be obtained, the difference L between the diffusion depths of both regions 3 and 4 must be further reduced.
This results in a decrease in breakdown voltage between the source and drain. In contrast, as shown in FIG. 3, the base region 3 and the source region 4 form at least the gate portion from the main surface la side of the base 1 without forming a groove in the base 1. diffused through the diffusion window of the diffusion mask that has a common edge on the side that
A part of the drain region 2 faces the plane la, and a gate insulating layer 6 is deposited on the base region 3 interposed between this part and the source region 4, and a gate electrode 7 is deposited on this. For those with a double diffusion type planar configuration, each region 4
, 3, and 2 extend almost orthogonally to the plane la of the substrate 1 where the channel is formed, the channel length ff and the diffusion of both regions 3 and 4 are Keff/L with a groove L having a depth of is almost "1".

However, in the case of this configuration, the pattern is designed so that the verification per unit area, that is, the sum of the opposing lengths of the drain region 2 and the source region 4 facing the plane la and facing each other with the base region 3 in between, is made as long as possible. If the distance between the opposing base regions 3 is narrowed in order to increase the density of Drain resistance R due to resistance.

becomes large. The present invention aims to provide a semiconductor device, particularly an insulated gate field effect transistor, completely eliminating the above-mentioned drawbacks.

The present invention will be described with reference to FIG. 4, in which 10 generally indicates an insulated gate field effect transistor according to the present invention.

The illustrated example shows the case of an N-channel type, and in this case, an N-type semiconductor substrate 1 1, e.g.
A Si substrate with a 0 Masuyoshi crystal plane is provided. A second semiconductor region of the second conductivity type, that is, a P-type base region 13 is selectively formed on one main surface 11a, and a third semiconductor region of the first turtle type is formed on a portion above this. A double diffusion region with the semiconductor region 14 is provided. Further, the main surface 11a of the base body 11 has grooves 15,
For example, a V-shaped groove is formed by crystal orientation etching, but in this case, the groove 15 connects to the bonding surface L formed between the source region 14 and the base region 13, as shown by the chain line b in FIG. , the side surface of the groove 15 is formed so as to cross the source region 14 and the base region 13 at the curved portion of the junction surface i2 formed between the base region 13 and the drain region 12. The joint surface i and the original are made to be substantially perpendicular to each other. Then, a gate insulating layer 16 having a required thickness, such as Si02, is deposited on the surface of the base region 13 in the trench 15, and especially on the surface of the base region 13 interposed between the drain region 12 and the source region 14 facing the trench 15. , on which a gate electrode 17 is deposited.

Reference numeral 18 denotes a source magnetic pole ohmically deposited on the source region 14, and a part of the source magnetic pole 18 is deposited astride the base region 13 facing the surface la of the substrate 1.

Also in the present invention, an N-type high impurity concentration, ie, low resistivity, region 12' is formed on the other main surface 11b of the substrate 11, and a drain electrode (not shown) is provided in this region.
30' is an insulating layer for surface passivation such as Si02 formed on the surface of the substrate.

According to the present invention described above, both the base region 13 and the source region 14 are made into selective double diffusion regions, and curved portions are formed on both the junction surfaces i and i2, and this Since the groove 15 is made to be substantially orthogonal to each joint surface i and i2 at the curved portion, the width of the base region 13 facing into the groove 15, that is, the effective channel length ff', is almost perpendicular to both regions 13 and i2. Since the channel length ff can be made equal to the diffusion depth L of 14, the channel length ff can be made sufficiently small.

In addition, by setting ff≠L in this way, the difference L between the diffusion depths of both regions 13 and 14 avoids the need to make it 4 times smaller than the desired channel length ff. A field effect transistor for high frequency and high voltage use can be obtained in which the drop in breakdown voltage as described in 1. can be avoided. Further, according to the configuration of the present invention, since the groove 15 is provided and the gate portion is provided on the inner surface of the groove 15, the adjacent base regions 13 can be brought close enough to each other or in contact with each other, as shown in FIG. 4, for example. By forming the groove 15 as indicated by the horizontal line b in FIG. 5, joint surfaces i and i2 are formed on both opposing sides of the groove 15, respectively, as shown in FIG. It is possible to configure a gate portion that can extend along orthogonal directions and has a sufficiently large sum of verifiability.

Incidentally, as shown in FIG. 6, if we assume that each area has the same arrangement pattern as in FIG. 4 but has a planar structure as shown in FIG. 3 without providing the groove 15, this In this case, the resistance Ro between the source and drain becomes large, but according to the present invention, this increase in resistance Ro can be avoided. Next, with reference to FIG. 7, an example of a manufacturing method for obtaining the device 10 of the present invention illustrated in FIG. 4 will be described.

In this case, as described above, as shown in FIG. 7A,
10 An N-type Si substrate 11 cut out to have a positive crystal plane is provided,
An N-type low resistivity region 12' is formed on the main surface 1b on the back side by, for example, full-surface diffusion.

On the other hand, an impurity diffusion mask 21 is formed on the front surface 11a of the base 11. This mask 21 can also be used as an oxidation mask, for example, it can be composed of a Si3N4 layer. In this case, a thin Si02 layer 22 for preventing distortion is formed entirely on the surface 11a of the base 11, and on this Similarly, a Si3N4 layer 23 is formed on the entire surface, and a Si02 layer 23 with a thickness sufficiently larger than that of the layer 22 is formed on the Si3N4 layer 23 to serve as an etching mask for selectively etching away the Sj3N4 layer 23 on the entire surface. Layers 24 are each applied by well-known techniques. Then, Si0
Unnecessary portions of the second layer 24 are removed, and then, using this Si02 layer 24 as an etching mask, the portions of the Si3N4 layer 23 that are not covered by the Si02 layer 24 are etched away, and the remaining thick Si02 layer 24 and Si3N4 layer 23 are removed. Using these as an etching mask, the portions of the thin Si02 layer 22 not covered by these are etched away. The pattern of this mask 21 is, for example, in the form of a band extending in a direction perpendicular to the plane of the paper in FIG. Next, as shown in FIG. 7B, P-type impurities are selectively diffused to a required depth through the portions not covered by the mask 21, that is, the windows 21a and 21b on both sides.
form 3.

In this case, the base region 13 diffuses not only under the windows 21a and 21b but also from the edges of these windows 21a and 21b so as to enter under the mask layer 21, and has a PN arc-shaped cross section approximately centered on this twilling portion. Joint surfaces are formed. Next, as shown in FIG. 7C, a diffusion window, for example, region 1, is formed so that at least the edge on the side where the gate portion will ultimately be formed coincides with the twill of the window in which the previously formed region 13 is diffused.
N-type impurities are diffused through the windows 21a and 21b, which are the same as the diffusion windows No. 3, to selectively diffuse the source region 14.

In this case as well, the region 14 has windows 21a and 21b.
It is formed by penetrating under the mask layer 21 with a cross-sectional arc centered on the edge of the region 13, and a curved portion is formed on the PN junction surface between it and the region 13, but the depth of diffusion in this case is , is chosen to be smaller than the diffusion depth of the base region 13. Further, for example, this diffusion is performed in an atmosphere containing oxygen, and the windows 21a and 21
An Si02 layer, that is, an insulating layer 30 for surface inactivation, is formed on the surface of the base 11 so as to close the area b. Thereafter, as shown in FIG. 7D, the mask layer 21 is removed, and using the insulating layer 30 as an etching mask, the exposed portions of the mask layer 21 are etched by crystal orientation etching to form the grooves 15. .

The etching groove 15 formed in this way has an inner surface formed by the crystal plane of the seam 111 as etching progresses, so the size and shape of the etching groove 15 are determined by the width of the entrance of the groove 15, that is, the mask layer. By defining the width of 21, it is formed into a certain size and shape. Therefore, by selecting the entrance width of this groove 15, the side surfaces of this groove 15 cross both joint surfaces i and i2 at their curved portions, and these side surfaces are approximately orthogonal to the joint surfaces i and j2. Eggplant. Then, as shown in Figure 7E,
In this groove 15, the base region 1 faces at least the side surface thereof.
A gate insulating layer 16 is formed by, for example, surface thermal oxidation to produce a Si02 layer.

Then, although not shown in the drawings, an electrode window is formed on the source region 14 and the insulating layer 30 on the surface of the base region, the source electrode 18 is ohmically attached, and the gate electrode 17 is coated on the gate insulating layer 16. wear it. In this way, the device of the present invention, ie, the field effect transistor 10, illustrated in FIG. 4 is obtained. The illustrated example is an N-channel field effect transistor, but when applied to a P-channel type, the conductivity types of each part shown in the figure may be set to opposite conductivity types.

[Brief explanation of the drawing]

FIG. 1 is an enlarged cross-sectional view of a conventional V-groove field effect transistor, FIG. 2 is an explanatory diagram, FIG. 3 is an enlarged cross-sectional view of a conventional planar field effect transistor, and FIG.
The figure is an enlarged cross-sectional view of an example of the device of the present invention, FIG. 5 is a diagram for explaining the same, FIG. 6 is an enlarged cross-sectional view of a comparative example for the device of the present invention, and FIGS. 7 A to E are examples of the device of the present invention. It is an enlarged cross-sectional view in each step of one manufacturing method. 10 is a semiconductor device according to the present invention, 11 is a semiconductor rhombus, 1
2, 13 and 14 are first, second and third semiconductor regions;
i and i2 are PN junction surfaces, 15 is a trench, 16 is a gate insulating layer, and 17 is a gate electrode. Figure 1 Figure 2 Figure 5 Figure 3 Figure 4 Figure 6 Figure 7 Figure 7

Claims (1)

[Claims] 1 A selective double diffusion region of a second semiconductor region of the second conductivity type and a third semiconductor region of the first conductivity type is formed in the first semiconductor region of the first conductivity type, and a groove is formed. formed,
The side surfaces of the groove are formed in the second and third semiconductor regions.
PN formed between the first and second semiconductor regions
A gate electrode is formed at a curved portion of the bonding surface so as to intersect the bonding surface at a substantially right angle, and a gate electrode is provided between the first and third regions facing into the groove with a gate insulating layer interposed therebetween. semiconductor device.