JPS6035829B2 - memory device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a memory device that includes a source region, a drain region, and a memory section, and is capable of retaining charges in the memory section.

Conventionally, this type of memory has been integrated into an IC as a non-volatile memory.

For example, according to the MNOS type memory shown in FIGS. 1 to 3, an N-type semiconductor substrate 1 is provided with a long P-type source region 2 and a drain region 3 facing each other, and between these regions, Si02 layer 4 on semiconductor substrate 1 (
The thin Si02 layer 5 (thickness 25
Grade A). Moreover, S on the Si02 layers 4 and 5
The i3N4 layer 6 (about 600A thick) is uniformly formed,
Furthermore, on this Si3N4 layer, a longitudinal gate electrode 7 is deposited parallel to each other and intersects the source region 2 and drain region 3 at approximately right angles. Therefore, thin Si02
The layer 5 and the portion of the Si3N4 layer 6 on it are gate oxide films and form a memory section, and by applying a voltage to the gate electrode 7 overlapping the layer 5, the Si02 layer 5 and the Si3N4 layer 6 are separated.
Minority carriers in the semiconductor substrate 1 are held at the interface with the 3N4 layer 6. In other words, in this memory,
The memory portions are arranged between the source region 2 and the drain region 3 so as to be spaced from each other along a second direction perpendicular to the first direction connecting the source region 2 and the drain region 3. In such a memory, a thick Si02 layer 4 exists between each gate electrode 7, but as shown in FIG. 3, the boundary between this thick Si02 layer 4 and the thin Si02 layer 5 in the memory section There is no vertical step, but a sloped portion 8 that gradually becomes thicker from the Si02 layer 5 to the Si02 layer 4.

Then, the gate electrode 7 is formed from the thick Si02 layer 4 from this inclined part.
Both sides of it extend across. Now, by applying a negative voltage to the gate electrode 7, holes, which are minority carriers, are removed from the Si0
When storing memory by trapping at the interface between the second layer 5 and the Si3N4 layer 6, a thick S layer is formed under the gate electrode 7.
In the i02 layer 4, the amount of trapped carriers is smaller than in the thin Si02 layer 5, and as a result, the shift amount of VTH in the above-mentioned slope part 8 is equal to the VT of the memory part.
It is smaller than the shift amount of H.

To explain this using the equivalent circuit in Figure 4, for example -10V
and MNOS type memory 9 in the memory section with high VrH,
For example, an MNOS type memory 10 with a low slope 8 of -3V and VrH exists in parallel in the memory state of "1",
The amount of shift in the low current region from the non-memory "0" state to the "1" state becomes small as shown in FIG. Therefore, in the memorized state, it is 1 in the low current region. s gradually increases, but this is due to the leakage current flowing through the slope portion 8. In this way, leakage current increases, power loss increases, and the design of the memory logical output circuit becomes more difficult. In order to prevent this drawback, as shown in FIGS. 1 and 3, a highly doped N+ type semiconductor region 11 is formed between each gate electrode 7 over the width W of the memory section. It is known to be used as a channel stopper. However, channel stopper 1 1
spans the width W of the memory section, so the source area 2
Since the gap between the drain area 3 and the drain area 3 cannot be sufficiently removed, the withstand pressure will not be sufficient. However, since both ends of the channel stopper 11 are located on both sides of the gate electrode 7, leakage current due to the slope portion 8 cannot be sufficiently prevented. Another type of memory is shown in FIG. 6, in which P+
Si0 of the cross section forming the channel stopper 11 of the mold
The second layer 5 and the Si3N4 layer 6 have the same thickness as the insulating layer of the memory section.

In order to form the channel stopper 11, since the B+ ion beam 12 is implanted using the gate electrode 7 as a mask, the channel stopper 11 corresponding to the width of the memory section is formed, and the same process as described above is performed. Pressure resistance decreases. In addition, when activating by annealing after ion implantation, the gate electrode 7 is usually made of AI and the melting point of this AI is as low as 530 to 540 degrees, so the annealing temperature should not be higher than this. However, it is about 500qC at most. Therefore, the amount of ion beam implanted must be as large as 3×1 and 5 ions/field, which requires a large implantation device and increases the implantation time. The present invention was invented to correct the above-mentioned defects, and includes a first conductivity type source region provided on the surface of a semiconductor substrate, and a first conductivity type source region provided on the surface of the semiconductor substrate. A conductive type drain region is arranged between the source region and the drain region so as to be spaced from each other along a second direction perpendicular to a first direction connecting the source region and the drain region. and a channel stopper region of a second conductivity type provided on the surface of the semiconductor substrate between these memory parts, and the memory parts are sequentially stacked on the semiconductor substrate. The channel stopper region includes a thin insulating layer, an insulating layer capable of retaining charge, and a gate electrode, and the channel stopper region is formed from the source region and the drain region so that the channel stopper region is located approximately in the center between the source region and the drain region. The channel stopper regions are spaced apart from each other by approximately the same distance, and both ends of the channel stopper regions overlap opposing sides of the memory portions that are adjacent to each other in a direction perpendicular to the surface. It is something.

By configuring this way, leakage current can be sufficiently reduced. This is advantageous in terms of space and circuit design, provides sufficient withstand voltage, and simplifies the manufacturing process. Next, an embodiment in which the present invention is applied to an MNOS type memory integrated into an IC will be described with reference to FIGS. 7 to 11.

7 to 9 show a first embodiment of the present invention.

Since the memory according to this embodiment has parts in common with the one shown in FIG. 1, the common parts will be designated by common reference numerals and a description thereof will be omitted.

In this memory, a channel stopper 21 made of a high concentration N0 type semiconductor region provided on a semiconductor substrate 1 is formed in a memory portion adjacent to each other or a thin Si02 layer 5.
It is formed so as to straddle the gap.

That is, the channel stopper 21 extends from the thick Si02 layer 4 to the inclined portion 8, and further extends to the thin Si02 layer 5 at both ends thereof, and overlaps the memory portion.
Also, the width W2 of the channel stopper 21 (i.e., the width of the source
The length (length in the channel direction between the drains) is shorter than the width W of the Si02 layer 5 in the memory section, and these channel stoppers 21 are spaced from the source region 2 and the drain region 3 by approximately equal distances. If the channel stopper 21 is formed in this way, since the end thereof extends from below the above-mentioned inclined part 8 to the memo IJ- part, the channel stopper 21 can pass through the inclined part 8 in the memory state (i.e., "1" state). It is possible to significantly reduce the load current, reduce power loss, and simplify the memory read circuit.
Further, since the channel stopper 21 is located approximately in the center between the source region 2 and the drain region 3, the channel stopper 21 and the source region 2 and the drain region 3
It is possible to maintain sufficient distance between the Therefore, the withstand voltage can be increased without increasing the size of the device, and the tolerance range for misalignment of the channel stopper 21 can be increased, thereby simplifying the manufacturing process. Furthermore, when forming the channel stopper 21 according to this embodiment, it is not necessary to use the ion implantation method as shown in FIG. The concentration is diffused and then activated.

Thereafter, AI is deposited on the above-mentioned Sj3N4 layer 6 and a predetermined portion is removed by etching to form a gate electrode 7. Therefore, since the gate electrode 7 is not present at the time of activation of the channel stopper 21, the processing temperature can be raised sufficiently, and the process requires less equipment and time than the method shown in FIG. It can be simplified to Onaka. Next, a second embodiment of the present invention will be described with reference to FIG. According to this example, the channel stopper 31 has a shape similar to that of the channel stopper 21 shown in FIG. 9 with the middle portion removed.

That is, one channel stopper 31 overlaps the Si02 layer 5 of the memory section and extends rightward to the thick Si02 layer 4, fully including the slope part 8, and the other channel stopper 31 also overlaps the Sj02 layer 5. In an overlapping state, they fully include the sloped portion 8 and extend to the left up to the thick Si02 layer 4. Therefore, also in this embodiment, since the channel stopper 31 is located below the inclined portion 8 and is located approximately in the center of the source region 2 and drain region 3, the same effect as in the first embodiment can be obtained. You can get it. Next, a third embodiment of the present invention will be described with reference to FIG.

According to this embodiment, unlike the first and second embodiments, the Si02 layer 45 has the same thickness as the Si02 layer in the memory section in the cross section where the channel stopper 41 is formed, and The Si3N4 layer 46 on this is 600
It is uniformly formed with a thickness of about A.

In this case, the insulating layer under the gate electrode 7 acts as a memory section, but the channel stopper 41 is present between adjacent memory sections, as shown in FIG.
And both ends thereof overlap with the memory section.

Therefore, although it is different from the case with the sloped portion 8 described above, leakage current can still be reduced through the periphery of the memory section, and the width of the channel stopper 41 is also selected so as to be sufficiently far away from the source and drain. Because of this, it can withstand a large amount of pressure.

Furthermore, since the channel stopper 41 is formed without using ion implantation, the process can be simplified. Note that the channel stopper according to this embodiment can also be divided into two parts as in the second embodiment.

Although the present invention has been described above based on examples, it will be understood that the present invention is not limited to these examples and can be further modified based on the technical idea thereof.

For example, the size of the channel stopper may be varied in order to reduce leakage current and improve breakdown voltage. Also,
As the insulating layer on the Si02 layer, in addition to Sj3N4, a layer made of Si state y0z, mountain 203, etc. may be used. Furthermore, it is of course possible to convert the conductivity type. As mentioned above, the present invention
Since the opposing side portions of adjacent memory portions and both ends of the channel stopper region overlap each other in the direction perpendicular to the surface of the semiconductor substrate, leakage current is prevented from flowing through the periphery of the memory portion. Reducing it is advantageous in terms of output, power loss, and circuit design.

In addition, since the channel stopper region is configured to be located approximately in the center between the source and drain regions, a sufficient distance can be maintained between the channel stopper region and the source and drain regions, and the device The withstand voltage can be greatly improved without increasing the voltage, and the manufacturing process can be simplified because the tolerance range for misalignment of the channel stopper region can be increased.

Moreover, since the channel stopper region does not have to be formed by ion implantation as in the conventional method, the process can be simplified in terms of annealing and the like.

[Brief explanation of drawings]

Figures 1 to 5 show examples of follow-up functions, in which Figure 1 is a plan view of a portion of an MNOS type memory, Figure 2 is a sectional view taken along the 0-Ro line in Figure 1, and Figure 3 is a sectional view of a portion of the MNOS type memory. m- in Figure 1
Fig. 4 is an equivalent circuit diagram of the memory section and its surroundings, and Fig. 5 is a partial enlarged cross-sectional view of the m-line.
It is a curve diagram showing the shift of TH. FIG. 6 shows another conventional example, and is a sectional view of a portion of an MNOS type memory. 7 to 11 show an embodiment in which the present invention is applied to an IC-based M-disk OS type memory, in which FIG. 7 is a plan view of a portion of the memory according to the first embodiment, and FIG. 8 is a wind line sectional view in FIG. 7, FIG. 9 is a partially enlarged sectional view taken along the line K-X in FIG. 7, and FIG. 10 is an enlarged sectional view of a portion of the memory according to the second embodiment. FIG. 11 is a cross-sectional view of a portion of the memory according to the third embodiment. In addition, in the symbols used in the drawings, 2 is the source region, 3 is the drain region, and 7 is the source region.
8 is a gate electrode, 8 is an inclined portion, and 21, 31, and 41 are channel stoppers. Figure 1 Figure 2 Figure 3 Figure 4 Figure 5 Figure 6 Figure 7 Figure 8 Figure 9 Figure 10 Figure 11

Claims (1)

[Claims] 1 A source region of a first conductivity type provided on the surface of a semiconductor substrate, a drain region of a first conductivity type provided on the surface of the semiconductor substrate, and a first conductivity type drain region connecting these source regions and drain regions. a memory portion disposed between the source region and the drain region so as to be spaced apart from each other along a second direction perpendicular to the first direction; and a surface of the semiconductor substrate between the memory portions. channel stopper regions of a second conductivity type provided in the semiconductor substrate, and the memory portion includes a thin insulating layer, an insulating layer capable of retaining charge, and a gate electrode, which are sequentially laminated on the semiconductor substrate. the channel stopper region is spaced approximately equidistant from the source region and the drain region so as to be located approximately centrally between the source region and the drain region; A memory device characterized in that both end portions overlap mutually opposing side portions of the memory portions that are adjacent to each other in a direction perpendicular to the surface.