JPS60254912A - Josephson latch circuit - Google Patents

Abstract

PURPOSE:To hold data in a superconduction loop securely by lowering an enable signal for a latch first and then lowering a bias current when data is latched by an interference element. CONSTITUTION:Current delay operation is utilized for the bias current and enable signal inputted to the interference signal 6 to set the value of a resistance 12 where the bias current flows to a value large enough to have a load line shown by (a) and the value of a resistance 16 where the enable current flows to a value small enough to have a load line shown by (b), delaying the falling of the bias current behind the falling of the enable signal. Therefore, the enable signal falls first and then the bias current falls, so that a circulating current is held in the superconduction closed loop 7 securely without malfunction. Thus, the resistances 12 and 16 are set to the high and low resistance values respectively to vary the timing of the bias current and enable signal, thereby preventing malfunction which occurs when the bias current and enable signal fall at the same time.

Description

DETAILED DESCRIPTION OF THE INVENTION (1) Technical Field of the Invention The present invention relates to a Josephson logic circuit, and particularly to a Josephson launch circuit that reliably retains data in a flip-flop logic circuit.

(2) Background of the invention Superconducting quantum interference devices (hereinafter referred to as interference devices) using Josephson junctions are currently used in switch circuits.

It is used in logic circuits such as memory circuits and latch circuits, and in magnetic measurement. Especially in order to use this interference element as a latch circuit for data retention.

An alternating current is applied as a bias current to the junction of the interference element, and before the bias current falls, the enable signal that has been magnetically input to the junction of the interference element falls, and the superconducting loop connected to the interference element is turned off. It is necessary to maintain the loop current.

(3) Prior Art and Problems Figure 1 is an equivalent circuit diagram of a Josephson launch circuit in which data is held in a superconducting loop coupled to a conventional interference element, and is part of the master flip-flop of the launch circuit.

A bias current, which is an AC pulse signal, is input to the interference element 2 from the terminal 1, and the data previously held in the interference element 2 is cleared at the rise of the bias current. After that, when the same bias current (same pulse) is flowing through the interference element 2, when the latch enable signal is magnetically input to the interference element 2 from the terminal 3, the interference element 2 and the inductance 4 shown by the dotted line in the figure form the latching enable signal. A current is transferred to the superconducting closed loop 5. This circulating current remains and flows in the superconducting loop 5 even after the bias current and enable signal are removed.
Operates as a launch circuit that holds data.

- However, in order to ensure that the superconducting closed loop 5 is retained after the enable signal falls.

Although it is necessary for the bias current to fall, in conventional circuits, the bias current and the enable signal may fall at the same time. Therefore, the operation of maintaining the circulating current in the superconducting closed loop 5 becomes unstable, causing malfunction of the launch circuit.

(4) Purpose of the Invention In view of the above-mentioned conventional drawbacks, the present invention provides a method for launching data into a superconducting loop by first lowering the launch enable signal and then lowering the bias current. An object of the present invention is to provide a Josephson launch circuit that can reliably hold data.

(5) Structure of the Invention According to the present invention, the above object includes a first resistor whose one end is connected in parallel to a first Josephson element, and a second resistor whose one end is connected in parallel to a second Josephson element. a resistance, and the first
a superconducting quantum interference device to which a bias current is supplied through the resistor and controlled by the current flowing through the second resistor; and a superconducting loop coupled to the superconducting quantum interference device, A resistive load line crosses the characteristic gap voltage of the first Josephson element.

Achieved by providing a Josephson latch circuit characterized in that the operating point is set such that the load line by the second resistor intersects at a voltage lower than the characteristic gap voltage of the second Josephson element. be done.

(6) Embodiments of the Invention Below, one embodiment of the present invention will be described in detail with reference to the accompanying drawings.

FIG. 2 is an equivalent circuit diagram of the Josephson latch circuit of the present invention.

In the figure, an inductance 8 for forming a superconducting closed loop 7 is connected to the interference element 6.

One end of the interference element 6 and the inductance 8 are grounded. A Josephson AND circuit (hereinafter referred to as an AND circuit) 9 is a Josephson element for delaying a bias current input from a terminal 10 with respect to an enable signal input from a terminal 11, and one end of the AND circuit 9 is connected to the terminal 10 and a resistor. 12
One end is connected to the connection point between the interference element 13 and the resistor 14 . The resistor 12 is a first resistor for delaying the bias current with respect to the enable signal together with the AND circuit 9, and the other end of the resistor 12 is connected to the interference element 6.
connected to the bias current input of the

The interference elements 6 and 13 are provided with a control line 15 for passing a launch enable signal from the terminal 11.

Control line 15 is connected to ground via a second resistor 16 for delaying the bias current with respect to the enable signal. Further, a bias current for driving the interference element 13 is inputted to the interference element 13 from a terminal 17 via a resistor 14 .

FIG. 3 is a principle circuit diagram for explaining the bias current delay operation of the equivalent circuit of FIG. 2, and the Josephson junction 18 corresponds to the AND circuit 9 of FIG.

Resistor 19 corresponds to resistor 12 or resistor 16 in FIG.

First, the principle of operation of the present invention will be explained using FIG. The voltage-current characteristics of the Josephson junction element 18 are as shown in curve A in Figure 4+al or curve B in Figure 4 (bl). When the gap voltage V6 is reached, the current rapidly increases, resulting in a nonlinear characteristic I=f(V).

When a load resistor 19 of a resistor RL is connected in parallel to a Josephson junction element 18 exhibiting such a nonlinear characteristic 1=f(V) as shown in FIG. If the voltage across 18 is ■.

■Go --(1/R-v+I e ・ ・ ・ ・(
1). This equation (1) is called the so-called load line,
In Figure 4(a) and fbl, the straight line C or D, respectively.
becomes.

The voltage of the Josephson junction element 18 has a nonlinear characteristic 1 = f
This is because it must satisfy (V) and satisfy the linear characteristics of 1 and +11 formula.

r(v)=-(1/RL)v+Ie...This is the solution to the equation (2). This solution, that is, the operating point is shown in Figure 4 ia)
, (b) becomes point X.

Figure 4 (al is the case where the load resistance RL is a large resistance RL, and therefore the slope (1/RL l ) is small, and Figure 4 (bl is the case where the load resistance RL is a small resistance RL2, and therefore the slope (1/RL l ) is small. /RL 2 ) is large.The Y-intercept P of the load line is the same in both Figure 4(a) and (bl), which is 18.The height to the operating point X is a Josephson junction. Current flowing through element 18 Current I flowing through load resistor RL at height H between PX (PX) in one device
It's Q. Figure 4 (In case of al, the load resistance RL is large and the slope of the load line C is small, so the operating point
It is on the characteristic curve of the Josephson junction element 18 where the slope at r is almost infinite, and in FIG. Sub gear smaller than 7
voltage is coming. As the bias current (1)8 is made smaller, the load resistance RL of the load line remains constant.

Move in parallel. In Figure 4 (al), the load line C with Y-intercept P moves in parallel and becomes the load line E with Y-intercept Q. At this time, the operating point X moves on the characteristic at the gap voltage Vq and becomes X'
However, during that time period T, H(PX)=H(Q
X'), the load current IRL+ hardly changes and remains constant.

On the other hand, in FIG. 4), the load line of Y-intercept P is translated in parallel to become load line F of Y-intercept Q. At this time, the operating point X moves on the characteristic corresponding to the sub-gap voltage smaller than the gap voltage VB and reaches point current I
RL 2 will be monotonically decreasing. Therefore, a circuit like the one shown in FIG. 3 whose load resistance has a large value RL1 and a small value RL2 can be independently and simultaneously connected to the same bias current I.
.

When operated using , as shown in Fig. 5.

When the bias current ■8 is lowered at time to, the current IR flowing through the large load resistance RL and 1 during the 9-hour period T
L% is constant, and the current flowing through the small load resistance R12 is 1. Lλ will fall with the fall of ■ゎ.

This means that the current 1i> of the large load resistor RL7 is delayed.

Here, by utilizing this current delay effect on the bias current input to the interference element 6 in FIG. Set to

By setting the value of the resistor 16 through which the enable current flows to a small value so as to have the load line shown in FIG. 2(b), the fall of the bias current can be delayed from the fall of the enable signal.

That is, if a bias current is applied to the interference element 13 from the terminal 17 to make the interference element 13 active, and an enable signal is input from the terminal 11 at the same time as the bias current is input from the terminal 10, the interference element 13 performs an AND operation due to the input of the enable signal. A current is applied to the circuit 9. The AND circuit 9 uses this current and the bias current input from the terminal 10 to connect the resistor 1.
A bias current is supplied to the interference element 6 via 2. Further, an enable signal is also magnetically coupled and inputted to the interference element 6, causing current to flow through the superconducting closed loop 7. Next, terminal 10.1
When the bias current and enable signal input from 1 decrease, the bias current decreases with a delay with respect to the enable signal due to the characteristics created by the AND circuit 9 and the resistors 12 and 16, as described above. Therefore, the enable signal falls first, and the bias current falls later.

Circulating current can be reliably maintained in the superconducting closed loop 7 without malfunction.

In this way, the present invention uses resistors 12 and 16 as high resistance and high resistance, respectively.
Vary the bias current and enable signal timing by selecting a low resistance.

At the same time, it is possible to prevent malfunctions that occur when the bias current and enable signal fall.

The present invention is not limited to the above-described embodiments, and the AND circuit 9 may be configured with one or more Josephson junctions, or may be implemented with interference elements.

(7) Effects of the Invention As described in detail above, according to the present invention, the fall of the bias current can be delayed with respect to the fall of the launch enable signal.

Malfunction of the Josephson latch circuit can be prevented and the operating margin of the launch circuit can be improved.

Furthermore, the bias current and enable signal input to the interference element can be set only by setting the resistance values of the resistors 12 and 16 to high resistance and low resistance, respectively, and the circuit configuration becomes very simple.

[Brief Description of the Drawings] Fig. 1 is a conventional Josephson latch circuit diagram, Fig. 2 is a Josephson latch circuit diagram of the present invention, and Fig. 3 is a configuration diagram illustrating the operation of the Josephson latch circuit of the present invention. Figure 4 (a
l, (bl is a characteristic curve diagram, and Figure 5 is a current characteristic curve diagram. 6.13... Josephson quantum interference device. 7... Superconducting closed loop, 8... Inductance,
9...Logic product circuit. 12.16.19...Resistance, 1B...Josephson junction. Figure 1 Figure 2 Figure 3 Figure 4 (a) (b) Figure 5

Claims (1)

[Claims] A bias current is supplied through a first resistor whose one end is connected in parallel to the first Josephson element, a second resistor whose one end is connected in parallel to the second Josephson element, and the first resistor. and a superconducting quantum interference device controlled by a current flowing through the second resistor, and a superconducting loop coupled to the superconducting quantum interference device, and the load line by the first resistor is connected to the first resistor. The operating point is set so that the load line of the second resistor intersects at a voltage lower than the characteristic gap voltage of the Josephson element. Characteristic Josephson launch circuit.