JPS60182169A - Amorphous silicon inverter - Google Patents

Abstract

PURPOSE:To increase the density of integration while miniaturizing the titled inverter by a method wherein a driving amorphous thin film transistor and a load resistor are formed into a double structure through the intermediatry of insulating films. CONSTITUTION:A gate insulating film 12, an alpha-Si:H film 13 as an active layer and another insulating film for protecting channel part are successively formed on a gate electrode 11 formed on a substrate 10. Later after etching the protective insulating film for the part other than channel part, an n<+> alpha-Si film 14 is succesively formed to improve ohmic contact and after evaporating a metal for source.drain on overall surface, source.drain electrodes 15, 16 are formed to produce a driving amorphous silicon thin film transistor. After forming an interlayer insulating film 17, a contact hole is formed therein. An n<+> alpha-Si film for load resistor is formed on the electrode 16 side utilizing mixed gas as reacting gas and after patterning process, a load resistor 18 may be formed by etching process.

Description

TECHNICAL FIELD OF THE INVENTION The present invention relates to improvements in amorphous silicon inverters.

Prior Art and Problems FIG. 1 is a diagram for explaining a conventional inverter using an amorphous silicon thin film, where α is a cross-sectional view and b is an equivalent circuit diagram. In the figure, 1 is a glass or quartz substrate, 2 is a gate electrode G, 6 is a gate insulating film, 4 is a hydrogenated amorphous silicon (a-si:a) film, and 5 is an n''
a-81 film, 6 is the source electrode s, 7 is the drain electrode,
Reference numeral 8 indicates a load resistance electrode. As shown in Figure 0, this inverter has a gate electrode 2 and an α-8 on a substrate 1.
A driver thin film transistor (TI
A load resistor RL consisting of an n+α-81 film 5 and an electrode 8 is formed, and is constructed like the circuit shown in Figure b. When no signal is applied to the gate G of the TPT, Tout is 1H'', and when a signal is applied to the gate G, the TPT is turned on, setting Vout @L'' and functioning as an inverter.

In such a conventional amorphous silicon inverter, the driver thin film transistor TPT and the load resistor RL are arranged two-dimensionally on the substrate, so the element area becomes large, and when applied to peripheral circuits such as a shift register, it becomes expensive. There was a drawback that it was difficult to increase the density.

OBJECTS OF THE INVENTION In view of the above-mentioned conventional drawbacks, the present invention has two objects: to provide a miniaturized amorphous silicon inverter.

According to the present invention, this object is achieved by providing an amorphous silicon inverter characterized in that driver amorphous silicon thin film transistors and load resistors are constructed in multiple layers.

Examples of the invention Embodiments of the present invention will be described in detail below with reference to the drawings.

FIG. 2 is a diagram for explaining an amorphous silicon inverter according to the present invention. In the figure, 10 is a substrate, 11 is a gate electrode, 12 is an insulating film, 13 is a hydrogenated amorphous silicon (a-8i:H) film, and 14 is an n
15 is a source electrode, 16 is a drain electrode, 17 is an interlayer insulating film, 18 is a load resistor, 19 is a power supply electrode, 20 is an output terminal electrode, and 21 is a ground terminal electrode.

In this embodiment, a gate electrode 11, a gate insulating film 12, an α-8i:H film 13 serving as an active layer, the α-3i:H film and a source are used. -♂α-81 for improving ohmic contact with the drain electrode
A load resistor 18 of an ♂α-81 film is connected to an amorphous silicon thin film transistor consisting of a film 14, a source electrode 15, and a drain electrode 16 via an interlayer insulating film 17 formed at a temperature that does not cause deterioration of the characteristics of the thin film transistor. Further, an output terminal electrode 20 connecting the load resistor 18 and the drain electrode 16, a power supply electrode 19 at the other end of the load resistor 18, and a ground terminal electrode 21 connected to the source electrode 15 are provided. It is something that

This embodiment has a two-layer structure in which a load resistor is formed on an amorphous silicon thin film transistor for a driver via an insulating film, so the substrate area is smaller than that of a conventional single-layer structure. Miniaturization is achieved.

Next, the manufacturing process of this embodiment will be explained. First, the gate electrode fi! is formed on the substrate 10. 5102 or S on 11
Gate insulating film 12 using iN, active layer α-8i:H
Membrane 13, 8102 or S for channel protection
An iN insulating film is continuously formed by a glow discharge decomposition method. After that, a protective insulating film is applied to the area other than the channel area, and after
Next, an nα-81 film 14 is formed for ohmic improvement, and a source/train metal is deposited on the entire surface, and then a source/drain electrode 15 is formed by photolithography.
16 to produce an amorphous silicon thin film transistor for a driver.

Thereafter, a 5in2. A contact hole is formed by etching in the hindlimb film on which an interlayer insulating film 17 made of an inorganic material such as SiN or an organic material such as polyimide is formed.

Next, a mixed gas containing phosphine and monosilane is used as a reaction gas on the drain electrode side, and the glow discharge decomposition method is used at the above temperature to create a load resistor. An α-81 film is formed, and after patterning, a load resistor 18 is formed by etching.

Thereafter, wiring electrode metal is deposited and patterned using conventional photoetching techniques to form a t-source electrode 19, an output terminal electrode 20, and a ground terminal electrode 21, thereby completing the process.

FIG. 6 is a diagram for explaining another embodiment of the present invention. In this figure, the same parts as those of the previous embodiment shown in FIG. 2 are denoted by the same reference numerals. This embodiment differs from the previous embodiment in that a load resistor 18 is formed on the output terminal electrode 20, and a power supply electrode 19 is formed on it to form a site-to-side structure. Note that the effects of this embodiment are exactly the same as those of the previous embodiment.

Effects of the Invention As explained in detail above, the amorphous silicon inverter of the present invention has a 2N structure between the amorphous silicon thin film transistor for the driver and the load resistor via an insulating film, making it possible to increase the density and reduce the size of the liquid crystal display. It has great effects in that it can be applied to display drive circuits, image sensor switching element shift registers, etc., and contributes to their miniaturization.

[Brief explanation of the drawing]

FIG. 1 is a diagram for explaining a conventional amorphous silicon inverter, FIG. 2 is a diagram for explaining an amorphous silicon inverter according to the present invention, and FIG. 3 is a diagram for explaining another embodiment of the present invention. It is. In the drawing, 10 is a substrate, 11 is a gate electrode, 12 is a gate insulating film, and 16 is hydrogenated amorphous silicon (α
-8i+H) membrane, 14? 15 is a source electrode, 16 is a drain electrode, 17 is an interlayer insulating film, and 18 is a load resistance. Patent applicant Fujitsu Co., Ltd. Patent application agent Akira Aoki Patent attorney Kazuyuki Nishidate Patent attorney Yukio Uchida Patent attorney Akiyuki Yamaguchi Figure 1 (a) (b)

Claims (1)

[Claims] 1. An amorphous silicon inverter characterized by a multi-layered structure of driver amorphous silicon thin film transistors and load resistors.