JPS60178751A - Detection circuit for signal deterioration - Google Patents

Abstract

PURPOSE:To detect a signal deteriorating state including the detections of an error factor, the S/N deterioration, the break of an input signal, etc., by providing a window type indentifier in parallel to a data identifier to attain the control of the identification level and at the same time connecting a counter to the window type identifier to count the number of data which are put within a identifying range of the window type identifier within a prescribed period of time. CONSTITUTION:An input data signal is applied to a terminal 21, and a timing clock is applied to a terminal 22 respectively. A comparator 11 outputs ''1'' and ''0'' with signals higher than or lower than Vth. A circuit R consisting of the comparator 11 and a flip-flop 14 constitutes of a data identifier, and the outputs of flip-flops 15 and 16 are applied to an AND circuit 17. The flip-flop 15 outputs ''1'' when an input signal is lower than Vth+DELTA; while the flip-flop 16 outputs ''1'' when the input signal is higher than Vth-DELTA. Thus an output of ''1'' is obtained from the circuit 17 when the input signal is set at Vth+ or -DELTA. A counter 19 counts the outputs fed from the circuit 17 to count the signals entering an area of oblique lines shown in a figure.

Description

Detailed Description of the Invention [Technical Field of the Invention] The present invention relates to a device for monitoring signal deterioration due to transmission paths and repeaters in PCM communication, and particularly to a device for monitoring signal degradation due to transmission paths including repeaters, receivers, etc. The present invention relates to a detection circuit that detects a signal deterioration state, such as detection, S-deterioration detection, and input signal disconnection detection.

[Technology background]

PCM communication is currently widely used as a technology for transmitting large amounts of information, and has recently become increasingly important as optical PCM communication. One of the most important roles of communication is to transmit information accurately, and for this purpose, it is important to manage the operating status of transmission paths including repeaters, receivers, etc.

In order to ensure accurate information transmission at all times, we must constantly monitor the transmission path, including repeaters, etc., and prevent problems such as increases in signal error rates, increases in S/N deterioration, and interruptions in input signals. When it occurs, it is necessary to detect it immediately.

[Conventional technology and problems]

To this end, various proposals have been made for monitoring transmission paths including repeaters and receivers.

For example, in order to detect the error rate of a transmitted signal online, there is a method known as a bipolar checker, CRV detection, RDS detection, etc., which provides redundancy to the transmitted signal and uses that characteristic to digitally process it. However, this method has drawbacks such as the need to provide redundancy to the signal as information and the need for a large circuit scale for digital processing.

Further, it has been proposed to detect a timing component of an input signal and detect the presence or absence of the timing component to detect an input signal disconnection.

This will be explained using an example in which this is applied to an optical PCM receiver.

FIG. 1 is a diagram schematically showing a conventional optical PCM receiver that detects disconnection of an input signal based on the presence or absence of a timing signal.

An avalanche photodiode (hereinafter referred to as A/PD) 1 converts an input optical signal into an electrical signal, and outputs data to a terminal 6 via an amplifier 2 and an identification circuit 4 to be described later. The APD has an automatic gain control circuit (hereinafter referred to as A).
(referred to as GC) 3 is connected. The output of the amplifier 2 is also connected to a well-known timing circuit 5 consisting of a bandpass filter.
is connected to extract the timing component. This timing component is applied to an identification circuit 4, where the presence or absence of this timing component is monitored.

When the signal input is no longer present, the timing signal is no longer present, so by detecting the presence or absence of this, it is possible to detect the disconnection of the input signal.

However, in this case, since the timing components vary greatly depending on the pattern of the input signal, it is difficult to predict the state of the point at which the input signal is disconnected, and it is difficult to determine whether the input signal is disconnected.

Furthermore, in most cases, AGC is applied in the receiving section as illustrated in FIG. This also has the disadvantage that a timing component corresponding to this noise is generated, causing the identification circuit 4 to malfunction.

[Purpose of the invention]

This invention was made in order to improve the above-mentioned drawbacks, and it is possible to reliably detect the error rate of a signal through a transmission path including repeaters, receivers, etc., and to prevent S deterioration with a relatively simple configuration. It is an object of the present invention to provide a detection circuit capable of detecting a signal deterioration state such as detection of input signal failure and detection of input signal disconnection.

[Structure of the invention]

In order to achieve this object, the present invention provides a window type discriminator whose discrimination level can be adjusted in parallel with the data discriminator, and connects a counter to the window type discriminator to identify the window type within a predetermined time. The method is characterized in that it counts the number of data that has fallen within the identification range of the device and detects signal deterioration states such as error rate detection, S/N deterioration detection, and input signal disconnection detection.

[Embodiments of the invention]

Before giving a detailed explanation of the present invention, a detailed explanation of the present invention will be given.

As is well known, PCM communication is performed using a combination t of digital and digital codes of "0" and "1". This digital code is sent out as a rectangular wave pulse as shown in FIG. The result is a distorted shape as shown in h>.

FIG. 3 is a diagram showing an example of an eye waveform in the receiving section in the case of such a binary signal. In FIG. 31, the horizontal axis is time and the vertical axis is voltage.

Further, Vth represents an identification voltage, and t represents an identification time.

The received signal is at the identification voltage Vt at the identification time t.
If it is higher than h, it is determined to be "1", and if it is lower than Vth, it is determined to be "0".

If this is shown in terms of the probability distribution of the signal based on the identification time, the fourth
It will look like curves A and B in the figure. In FIG. 4, the horizontal axis is voltage and the vertical axis is probability.

Further, Vth is an identification voltage, and "S" is a pulse voltage representing "1". Curves A and B each have a voltage of 0.0 when the mark rate of the signal is m. The maximum probability is at the point S, and the variance σ1. σ3. is a Gaussian distribution curve. That is, the diagonally shaded part (α) of curve A that exceeds vi is
This is the part that should be recognized as "0" but is recognized as "1", and the shaded part (1) of curve B that exceeds Vth downward is recognized as "1". This is the part that is recognized as "0" even though it should be. Therefore, this part (α> + <b> becomes the error rate in this case.

When the signal deterioration due to transmission is small, the distribution becomes as shown by the broken line in FIG. 4, and it can be seen that in this case, the error rate for the identification voltage Vth is approximately zero.

Now, if we count the signals that fall within the range of ±4 around Vth, which is shown as the shaded area in Figure 5, this value has a correlation with the error rate (α) + (h> shown in Figure 4). expected to have.

The relationship between the detection rate pi and the error rate pi of signals falling within the range of vth±Δ is expressed as Δ=0.2. Δ=0.1. △=0.0
5 is plotted. In the figure, the horizontal axis is the error rate Pi, and the vertical axis is the detection rate Fi.

According to the figure, there is a one-to-one correspondence between the detection rate Fi and the error rate Pi, and it can be seen that the error rate PL can be estimated by measuring the detection rate Fi.

For example, when Δ=0.1, detection rate Fi = IX
10'''J, it can be estimated that the error rate circle is about I x 10-'.

As the signal clarity decreases, the curves A, B become more dispersed and therefore the detection rate F/ falling in Vth±Δ becomes higher. In this respect, it can be said that this detection rate Fi represents the degree of deterioration of S.

Also, when the input signal is cut off, the signal component becomes zero and only the noise component is input, but this noise component is
Since the voltage does not have a peak at two specific voltages and is distributed with an even characteristic, in this case, the detection rate pi naturally becomes high, and the signal error rate pi also becomes high. Therefore, it is expected that input signal interruption can be estimated when a specific error rate is reached.

FIG. 7 shows the relationship between the calculated error rate Pi and input signal disconnection. In the figure, the horizontal axis is the error rate P1, and the vertical axis is the probability of input signal disconnection. As can be seen from the figure, when the error rate is about I x 10'', it is predicted that the input signal will be disconnected with a probability of about 50.

As described above, by examining the number or probability of signals falling within the range of the discrimination voltage Δ, it is possible to detect the signal error rate, S/N deterioration, and input signal disconnection. .

This invention applies the above principle.

FIG. 8 shows an embodiment of the present invention to which this principle is applied. In the figure, 11, 12, and 13 are con/z6 rake, one input side of which is connected to the terminal 21, and Vth and Vl connected to the other terminals 23, 24, and 25, respectively.
! A+Δ and ■th−Δ are connected.

14, 15, and 16 are DC flip-flops whose C terminals are connected to the clock input terminal 22. 17 is an AND circuit, 18 is a timer, 19 is a counter, 20
is a DC flip-flop.

In this circuit, an input data signal is applied to terminal 21,
A timing clock is applied to terminal 22.

Comparator 11 indicates when the signal is higher than Vth.
1", and when it is low, "0" is output. This output is added to the next stage flip-flop 14#. Since a clock is applied to the C terminal of the flip-flop 14, a data output is obtained from the terminal 26, which is the Q output of the flip-flop 14. Therefore, the circuit consisting of the comparator 11 and the flip-flop 14 constitutes a discriminator for data discrimination. The comparator 12 outputs "1" when the input signal is higher than vth+Δ, and "0" when the input signal is lower than vth+Δ, but this is added to the next stage flip-flop 15 as before, and this time the C of the flip-flop 15 is output. Get the output from the terminal. Therefore, the output of the flip-flop 15 becomes "1" when the input signal to the comparator 12 is lower than vtA+Δ. Comparator 1
3 outputs "1" when the input voltage is higher than ■t-Δ, and outputs "0" when the input voltage is lower, and is applied to the flip-flop 16 at the next stage. Since the output is obtained from the terminal Q of the flip-flop 16, "1" is output from the flip-flop 16 when the input signal is greater than Vt-Δ. The outputs of flip-flops 15 and 16 are AND
added to circuit 17. As mentioned above, when the input signal from the flip-flop 15 is lower than vth+Δ, "l" is output.
" is output, and the flip-flop 16 outputs "1" when the input signal is higher than vth-Δ, so the AND circuit 17 outputs "1" when the input signal falls within the range of Vth±Δ. 1" will be obtained. If the output from the AND circuit 17 is counted by the counter 19, this means that the signals entering the shaded area in FIG. 5 are counted. In addition, comparator 12゜13,
Since the circuit W composed of flip-flops 15 and 16 extracts signals falling within the range Vth±, that is, within the window of voltage Vth±Δ, this circuit is called a window type discriminator. Also,
It goes without saying that vth and Δ can be adjusted. By the way, if the counter 19 is operated for a predetermined time, the total amount of data input within that time can be calculated, and the detection rate Fi can be obtained from this total amount and the count number of the counter 19. The timer 18 is provided for this purpose and controls the operation of the counter 19. If the configuration is configured so that "1" is output when the ship's own counter 19 counts a predetermined number for a predetermined time set by the timer 18, the output terminal 24 will output
It can be configured to output "1" at any predetermined detection rate Fi, and any S/N deterioration can be detected.

In addition, there is a one-to-one correspondence between the detection rate Fi (!: error rate pi) and the error rate pi, as explained in Fig. 6.
It can be seen that any error rate can be detected.

Furthermore, it goes without saying that by detecting when the error rate reaches a certain high value, it is possible to detect a disconnection of the input signal.

In the embodiment shown in FIG. 8, the output may be obtained from the terminal 27 before a specific detection rate is reached, or the value of the detection rate may be displayed continuously.

It goes without saying that the portion indicated by the broken line 30 in FIG. 8 may be processed in an analog manner. FIG. 9 shows an example of this, in which the output of the AND 17 is outputted as an analog direct signal by a low-pass filter 41, and when the output exceeds a predetermined reference value is detected by a comparator 42 and outputted to a terminal 44.

〔Effect of the invention〕

As described above, according to the present invention, it is possible to reliably and accurately detect error rates, S-deterioration, input signal disconnection, etc., without adding redundancy to signals and with a relatively simple configuration. Signal degradation can be detected.

[Brief explanation of the drawing]

Fig. 1 is a diagram showing an outline of an optical PCM receiver using a conventional detection circuit, Fig. 2 is a diagram showing a pulse-like signal, and Fig. 3 is an example of an eye waveform in the case of a binary signal. Figure, Figure 4,
Figure 5 shows the probability distribution of binary signals, Figure 6 shows the relationship between detection rate and error rate, Figure 7 shows the relationship between error rate and probability of input signal disconnection, and Figure 8 9 is a diagram showing an example of a detection circuit according to the present invention, and FIG. 9 is a diagram showing another embodiment. DESCRIPTION OF SYMBOLS 1... Avalanche photodiode, 2... Amplifier 3... Automatic gain control circuit, 4... Identification circuit 5.
...Timing circuit, 11, 12.13... Comparator 14.15, 16, 20... DC flip-flop 17... AND circuit, 18... Timer 19.
··counter. Patent Applicant Fujitsu Limited Agent Patent Attorney Akira Yamatani Eidai 1. Business 2 Figure 3 Figure 4 Figure 5I2I 7J Gyotamasu (5.

Claims (1)

[Claims] A window type discriminator whose discrimination level can be adjusted is provided in parallel with the data discriminator, and a counter is connected to the window type discriminator to count the number of data that falls within the discrimination range of the window type discriminator within a predetermined time. A signal deterioration detection circuit characterized in that a signal deterioration state is detected by detecting a signal deterioration state.