JPS60162373A - Reading system - Google Patents

Abstract

PURPOSE:To attain a high-speed and accurate reading system with use of plural photodetecting elements by dividing plural photodetecting elements arrayed in a straight line into groups and then scanning and reading those photodetecting elements every group. CONSTITUTION:The 2n units of photodetecting elements D1-D2n are divided into two groups every (n) units. An output terminal Q of flip-flop FF1 and FFn+1 of the first stage of each group is set at a high level respectively. While the terminal Q of each of FF2-FFn and FFn+2-FF2n is set at a low level. Then a line 32 is set at a low level, and a clock signal is extracted from a line 33. Then the terminal Q of the FF1 is set at a high level, and the line 32 is set at a low level again. Thus a logical state is attained as shown in a table. Then the line 36 is set at a high level, and the clock signal is extracted from the line 33. Thus the logical states of FF1-FF2n are shifted by a stage for each group. This attains the simultaneous scan/read is possible for each group.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a system for optically reading a document or the like using a plurality of light receiving elements.

In a typical conventional facsimile transmitter, a plurality of light-receiving elements are arranged in the width direction perpendicular to the direction of document travel, and as the document is traveling, the light-receiving elements are sequentially scanned. is configured to be read. In such prior art, in order to increase the reading speed, it is necessary to shorten the time required to perform a signal calling operation for each light receiving element, which reduces the delay in the operation of circuit elements related to the light receiving element. As a result, false detection may occur.

SUMMARY OF THE INVENTION An object of the present invention is to provide a reading method that can read manuscripts and the like at high speed and accurately.

FIG. 1 is an electrical circuit diagram of one embodiment of the present invention.

In order to optically read a document or the like in a facsimile transmitter or the like, light-receiving sweets D1 to D2n are arranged adjacent to each other in a straight line in the reading direction of the document in the width direction perpendicular to the traveling direction of the shoulder of the document. Ru. In this embodiment, the light receiving element DI
~D2n is divided into two groups of n pieces each, and each group has a light receiving element D I ~Dn, Dn+1.
-D2n tri, signal extraction line 11.1
2 are commonly connected to each other. Light receiving element DI-D2n
K is individually connected in series with analog switches SXI-5X2n, and these analog switches are commonly connected to line 13. analog switch SXI
When a high level signal is applied to .about.5X2n from AND gates 01.about.G2n, four passes are made only during the period in which the high level signal is applied.

One input of the AND gate Gl=(y!n is the output terminal Q of the so-called D-shaped lip 70-tube FFI to FF2n.
The output from is given. The other input terminal of the AND gates Gl-G2n is supplied with a signal from line 36 that is at a high level during the dismounting operation. D type flip 7
Tarock terminal CKKVi of 0 knobs FFI to FF2n,
A clock signal is applied from line 33, and a clear signal is applied from clear input terminal CRKi-1, line 34.

In the 7-lip 70-tube FFM, when a clock signal is applied to the tarlock input terminal CK while a high-level signal is applied to the input terminal, the high-level signal from the data input terminal is derived from the output terminal QK. do. When a high level signal is applied to the clear input terminal CR, the output terminal Q becomes low level. Like this lip 70 tube F
The operation of FI is the remaining 7 lip 70 lip FF2~FF2
The same applies to n. Line 13, 32, 33゜3
At 4.36, a signal is derived from the control circuit 14.

FIG. 2 is a diagram for explaining the operation of analog switch SXI. As shown in FIG. 2(1) from the AND gate G1, when a high level signal is applied for a period TW, the analog switch SXI becomes conductive with a delay of a time T1. When the signal from the AND gate G1 is switched to low level, the analog switch SKI is turned off after time T2 has elapsed. The times TI and T2 are, for example, 0.3 μs. AN'D game) Duration of high level of output from Gl TW, time TI + T2
, which ensures that the calyx window of the analog switch SXI is achieved. The same applies to the remaining analog switches SX2 to 5X2n.

Table 1 7 lips and 70 tubes FFI to FFn for each group.

FFn+1-FF2n first stage 7-lip 70-tube FFI
.

The output terminal Q of FF n + 1 is set to high level as shown in Table 1, and the remaining flip 70 terminals FF2~
The output terminals Q of FFn, FFn+2 to FF2n are set to low level. Such a setting operation first derives a high-level signal from the line 34, sets the output terminal Q of the clip 70 tube FFI-FF2n to a low level, and then outputs a low-level signal to the line 32. By deriving the tarok signal from the line 33 in this state, the output terminal Q of the flip 70-tube FFI can be brought to the noise level. Therefore, by setting the line 32 to low level and deriving n tarok signals from the line 33, the clip 70 tube F F n +1
The output terminal Q of can be set to high level.

Next, set line 32 to the noi level and line 33
The output terminal Q of the 7-lip, 70-tube FFI is set to /% low level, and the line 32 is set to low level again. In this way, the logic states shown in Table 1 can be obtained. At this time, line 36 remains at low level. The control circuit 14 outputs a high level signal to the line 32 every time n tarok signals are derived. As another example, the final stage flip 70 tube F
The output of the output terminal Q of F2n and the signal output from the control port I@14 on the line 321C# may be input to the data input terminal of the first stage 7-lip 70-tub FFI through an OR gate. Once the logical state of table 1 has been cleared, line 32 may remain at a low level.

After the logic states shown in Table 1 are achieved, the logic states of the flip-flops FF1 to FF2n are shifted by one step to each group @ by setting the line 36 to a high level and deriving the tarlock signal from the line 33. Thus the third
As shown in Figure (1), the analog switch SXI~
SXn is sequentially connected to the analog switch SXn + I ~ 5X2 as shown in Figure 3 (2).
n becomes conductive in sequence.

Analog switch SXI for pair δ for each group.

SXn+I; SX2, SXn+2; -; S
Xn and 5XLn are simultaneously conductive. Therefore, from line l1.12, Fig. 3(3) and Fig. 3(4)
) are respectively derived. In this way, the 2n light receiving elements D1 to D2n are divided into two groups of n light receiving elements, and each group has a light receiving element DI to Dn.
; Since Dn+1 to D2n are simultaneously scanned and read, all of these light receiving elements 1)I to D2n
The time required to read the light receiving elements D1 to D1 of each group is
It is equal to the time required to read Dn and Dn+I - D2n. In this way, the scanning time required for reading can be shortened, and reading errors caused by delays in the operation of analog switches SXI to 5X2n can be prevented.

FIG. 4 is a diagram of another embodiment of the present invention. This example is similar to the previous example, but it should be noted that the 7-lip 70-tube FFI for each group,
The Fn+l K lines 32, 32a are configured to individually apply high level signals to achieve the logical window shown in Table 1.

According to such a configuration, the flip-flops FFI to F
It is easy to make the logical window of F2n look like a %1 table.

FIG. 5 is an electrical circuit diagram of another embodiment of the present invention. Although this embodiment is similar to the embodiment shown in FIG. 4, it should be noted that the AND gate Gl-G2n
is omitted, simplifying the configuration.

FIG. 6 is an electrical circuit diagram of another embodiment of the present invention. In this embodiment, the light receiving elements D1 to D4p
is divided into four groups of p pieces each, two of which are analog switches SXa and S.
Scanned with Xb. Starvation signals for each valley group are derived on lines 41 to 44, respectively. - It is also possible to quickly read the signals of the light receiving elements D1 to D4p of the matrix 4HW.

As described above, according to the present invention, a plurality of linearly arranged light receiving elements are grouped and the light receiving elements included in each group are scanned and read for each group, so that originals etc. can be detected quickly and accurately.

[Brief explanation of the drawing]

Figure 1 is an electrical circuit diagram of one embodiment of the present invention, and Figure 2 is the electrical circuit diagram of one embodiment of the present invention.
A waveform diagram explaining the operation of the illustrated analog switches SXI to 5X2n, a waveform diagram explaining the operation of the embodiment shown in FIG. 81, and a waveform diagram explaining the operation of the embodiment shown in FIG. 5 is an electric circuit diagram of still another embodiment of the present invention, and FIG. 6 is a simplified electric circuit diagram of another embodiment of the present invention. 11~13,32,32a,33,34,36゜41~
44... Line, 14... Control times M, DI ~ D2
n, DI-D4p-5e Mitsuko, 5XI-5X2n
. SXa, 5Xb-analog switch, 01~G2n=
-A N D gate, F F I ~ F F 2 n
-D 717 Lip Flop Agent Patent Attorney Kei Nishi, Part 6 Figure 6 Relationship with the case of the Commissioner of the Patent Office Applicant name: Kyocera Corporation 4, agent address: Shinkobushi Building Showa, 1-13-38 Nishihonmachi, Nishi-ku, Osaka April 24, 1959 (shipment date)

Claims (1)

[Claims] Group multiple light-receiving sweets arranged in a straight line,
A bladder removal method characterized by scanning and reading the light-receiving elements included in each group.