JPS6016668B2 - Processor selection method in multiprocessor systems - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a processor selection method in a multiprocessor system.

In an online system, if multiple processors can operate simultaneously and perform equal processing, the expandability of the system (or the ability to add more processors to make up the system) and reliability will improve.

In particular, if the control method could be the same regardless of the number of processors, it would be possible to control Even if the number of processors decreases, it can be ensured that other processors are hardly affected. Note that in order to have multiple equal processors perform work for a single purpose, it is generally necessary to provide a common memory that can be accessed equally by each processor, and this memory A group of tasks to be performed is memorized. Then, each processor takes out this data and processes it. In this case, how to allocate work to each processor, ie, its scheduling, becomes important. For example, electronic exchange f Oku Masaru,
For systems that require real-time processing to perform a large number of processes in parallel, or for online systems that require highly time-accurate processing, a scheduling method that uses interrupts at fixed time intervals is recommended. A priority processing method is used.

This method uses, for example, clock interrupts for each ahs, and when an interrupt occurs, the process currently being executed is interrupted, a process that requires higher priority, that is, time accuracy, is performed, and after this process is completed, This method restarts the execution of interrupted processing. In such a case, there are a plurality of processes with high priority, and the execution time interval has a property that the execution time varies depending on the content of the process. For example, some processes are executed every time, i.e. every
Executed every s. Conventionally, such scheduling has been performed by a single, fixed master processor, which has assigned tasks to be executed by other processors, including itself.

However, since the master processor must always recognize and manage how many processors are present in the entire system, the above method does not allow the master processor to notify that a new processor has been added. I needed to let Setsa know. If a failure occurs in one of the processors, that processor will be disconnected, but since it is necessary to avoid assigning work to that processor, it is also necessary to recognize this fact. If a failure occurs in the master processor, the entire system will stop unless one of the other processors takes over as the master processor. Therefore, complicated processing is required to change the master processor. An object of the present invention is to provide a processor selection method that enables the above-described scheduling independently of the number of processors in a multiprocessor system.

A feature of the present invention is that in a multiprocessor system in which a plurality of processors are connected to at least one memory card common to all processors, and each processor generates interrupts at regular intervals, the number of interrupts at regular intervals is counted. In addition, there is a system time counter that is common within the system to control the execution interval of processing, a processor counter that is provided for each processor and counts interrupts that occur there, and when interrupt requests are generated from multiple processors, The selected processor compares the contents of the system time counter and its own processor time counter, and if they match, the contents of both counters are If the processor executes a predetermined process as the master processor of the system, and the contents of the two counters do not match, the processor time counter of the processor is incremented by the contents of the system time counter. The purpose is to rewrite the contents of. In general, a multiprocessor system has exclusive control means on a program, ie, a function that allows only one processor to obtain rights, using a rest & set command or the like.

By using this function, for example, an &hs clock interrupt is issued to each processor at the same time, causing each processor to execute an instruction at the same location, and using the exclusive control means described above, only the processor that executes the instruction earliest gains the right. If this processor is used for scheduling, it becomes possible to schedule the entire system without determining an individual master processor. In addition, like this 1
The mechanism by which only one processor can obtain rights in advance also involves the system's common memory access mechanism. Since a memory can only accept access from one processor at a time, the access mechanism generally includes a selection circuit. For this reason, even if each processor simultaneously generates an interrupt and executes the same instruction sequence from the same address, the time at which the exclusive control means is used is different for each processor, and the selection order of the selection circuit is different. Since it is random, any processor can have scheduling rights. A processor that has acquired scheduling rights determines the process to be executed in that period, stores it in the common memory, and notifies other processors that the process to be executed has been determined by ignoring the flag in the common memory. .

As a result, each processor uses the exclusive control means again, so that one processor simultaneously picks up only one of the sequentially determined processes and executes that process. When the execution of that process is completed, one of the remaining processes is extracted and executed again using the same method. When there are no more processes to execute, the process returns to the process that was interrupted by the interrupt. However, when such a scheduling method is adopted, some processes currently being executed by the processor may not be interrupted by clock interrupts, and some processors set an interrupt mask that prohibits clock interrupts during that time. You need to consider what you might do.

The timing at which the clock interrupt mask is removed has nothing to do with the clock interrupt, and if there is already a clock interrupt when the mask is removed, interrupt operation must be started immediately. However, at that time, it is not known whether the processor that can obtain the scheduling right is the one that uses the exclusive control means first, or whether the other processor has already performed the same, so the scheduling method described above is used. I won't be able to do that. Therefore, in the present invention, the above-mentioned problems are also solved by the following configuration.

FIG. 1 shows an embodiment of the present invention. In the figure, 1 is a processor constituting a multiprocessor system, 2 is a comparison means, 3 is a processor time counter, and 4 is an increment means. It is something. A multiprocessor system to which the present invention is applied has a plurality of such configurations (configurations surrounded by dashed-dotted lines), but in the figure, only one () is representatively shown in detail,
Others are omitted. Reference numeral 5 indicates exclusive control means, and reference numeral 6 indicates a system time counter.

A system time counter 6 counts the number of interrupts that have occurred in the entire system, and controls the processing execution interval.

This is, for example, a counter modulo 11, and the value of the counter becomes zero at the 12th interrupt. This allows ahs
The execution time is recognized at a cycle of ×12=98hs, and each process can be executed at a maximum of 96hs, generally an integer fraction of 98hs, and at a minimum of 8hs. Each processor copies the contents of the system time counter 6 to its own processor time counter 3 each time an interrupt occurs. FIG. 2 is a flow diagram showing an outline of the operation of the embodiment shown in FIG.
The operation of the above embodiment will be explained.

For example, if all processors constituting a multiprocessor system generate clock interrupts at the same time, the exclusive control means 5 selects the only processor 1.

Note that, as already stated, this exclusive control function may be, for example, a Test&Set command. When only one processor is selected, the contents of the time counter 3 of that processor and the contents of the system time counter 6 are compared in the comparison means 2. Both counters 3 and 6
If the contents of
and 6 are equally advanced.

Alternatively, only the counter 6 may be incremented and its contents may be transferred to the counter 3. Further, if the contents of both the counters 3 and 6 match, it means that the processor selected by the exclusive control means 5 is the leading processor, so the processor 1 receives the coincidence signal. When the master processor receives the command, it releases exclusive control, allows selection of another processor, and thereafter, as the master processor, performs scheduling of the entire system in this cycle. Even if another processor 1 is subsequently selected in this cycle, the system time counter 6 has already been incremented, so the contents of the time counter 3 of that processor 1 and that of the system time counter 6 must match. Therefore, in that cycle, the other processor 1 will not be mistaken as the master processor. Both counters 3 and 6
If the contents do not match, the time counter 3 of that processor is replaced with the contents of the system time counter 6 at that time by the non-coincidence signal from the comparison means 2.

In other words, it is transferred. After that, exclusive control is released. As explained above, according to this method, the control method for each processor is unified, so system expandability is improved, and since the master processor is not fixed, even if a failure occurs in the master processor, No complicated processing is required.

Furthermore, according to this method, even if a processor that has been masking clock interrupts releases the mask late and generates an interrupt, the contents of its own time counter will have already been updated outside of the system time counter. Since there is a discrepancy between the two, there is no way to mistakenly consider yourself to be the master processor.

[Brief explanation of the drawing]

FIG. 1 is a diagram showing an embodiment of the present invention, and FIG. 2 is a diagram showing its operation flow. In the figure, 1 is a processor, 2 is a comparison means, 3 is a processor time counter, 4 is an increment means, 5 is an exclusive control means, and 6 is a system time counter. Multi-r drawing boat Z drawing

Claims (1)

[Claims] 1. In a multiprocessor system in which multiple processors are all connected to at least one common memory and each processor generates interrupts at predetermined intervals, the number of interrupts at each predetermined cycle is counted and the processing execution interval is calculated. A system time counter that is common within the system that controls the system, a processor time counter that is provided in each processor and counts interrupts that occur there, and the contents of both the system time counter and the processor time counter. It has means for comparing, means for incrementing the contents of both counters, and a mechanism for selecting only one processor from among them when an interrupt request is generated from a plurality of processors. The contents of the system time counter and its own processor time counter are compared by the above-mentioned comparing means, and if they match, the contents of both counters are incremented equally by the above-mentioned incrementing means. executes a predetermined process as a master processor of the system, and when the contents of the two counters do not match, the contents of the processor time counter of the processor are rewritten by the contents of the system time counter. A processor selection method in a multiprocessor system.