JPS60154781A - Image pickup device - Google Patents

Abstract

PURPOSE:To enhance not only horizontal-direction resolution but also vertical- direction resolution by dividing a light image obtained through an image pickup lens into four and shifting a prescribed pitch portion for image pick up. CONSTITUTION:A color filter is provided so that G (green) information enters A plate 11, R (red) enters B plate 12, B (blue) enters C plate 13, and G (green) enters D plate 14. A synchronizing signal generation circuit 51 outputs a basic clock signal, horizontal and vertical synchronizing signals. An image pickup element driving circuit 52 generates a drive pulse and provides the drive pulses simultaneously to the A plate 11 - D plate 14 in parallel. Output signals from the A plate 11 - D plate 14 are supplied to a signal processing circuit 53. Horizontal output signals from the A and B plates are sampled alternately by the basic clock, horizontal output signals from the C and D plates are processed while delaying by 30mus, and obtain a high fine image in the horizontal and vertical directions.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field] The present invention relates to an imaging device used, for example, in an electronic camera or a TV camera, and particularly relates to an improvement in means for improving resolution.

[Prior art]

Conventionally used NTSC and PAL systems.

Imaging methods such as the SECAM method have already reached their limits in terms of improving image quality, particularly resolution. Therefore, new imaging methods with a larger number of scanning lines and higher horizontal resolution have been devised and some have been put into practical use for broadcasting or business use.

An example of this is an imaging system based on the high-definition TV standard, which is being researched and developed mainly by the Japan Broadcasting Corporation. The above standards assume the following specifications:

"Number of horizontal scanning lines"...1125 "Number of images per second"...30 frames (60 fields)2
:1 interlace "horizontal scanning frequency"...33.75 days 2 "color subcarrier frequency"...24.3MHz "luminance signal band tf<
(Y)J ・20MHz "Color difference signal/wideband color signal (
CW) J...7H2 "Color difference signal/narrowband color signal (CN) J...5.5H2 The characteristic point of the imaging method that obtains such high-definition video signals is that the frequency band used is extremely high. In the above example the 20-30 MHz band is used.

In some recent trends, there has been a strong push toward solid-state imaging devices in addition to higher definition imaging methods. However, when considering a solid-state image element that can support the high-definition imaging method described above, it requires a pixel count of 1 million or more and a tarok frequency of 30 MH2 or more. Such a solid-state image sensor is currently difficult to realize and requires long-term efforts.

By the way, as shown in Japanese Patent Publication No. 38-23724, there is already known a means for improving the image quality by improving the optical system in an image capturing system using the NTSC system. This uses a three-color separation prism system as an optical system,
This is a three-panel solid-state TV camera in which pixels are shifted laterally. This three-panel solid-state TV camera improves horizontal resolution. However, it is not suitable for improving vertical resolution.

Note that Y and R have been conventionally used as a means of improving image quality.

A four-position imaging system using four image pickup tubes corresponding to each of G and B signals is known. This method is described, for example, in "Kotabe Wakui [ITV Camera] (published by Japan Broadcasting Corporation) P2O-P66J.

The above-mentioned 4-position imaging system is also called the 1i1f imaging system, and has three imaging tubes for R, G, and B, and one additional imaging tube for Y, that is, for brightness. . The optical system used in this 911111 degree imaging system is usually constructed of a so-called half mirror, and is quite large.

〔the purpose〕

The present invention has been made based on the above circumstances, and its purpose is to provide a compact and easily configured optical system and imaging system that can improve resolution not only in the horizontal direction but also in the vertical direction, and that can significantly improve the resolution. The purpose of the present invention is to provide an image capturing device that can be used in a variety of ways.

〔overview〕

In order to achieve the above object, the present invention is characterized by the following configuration. That is, the optical image obtained through the imaging lens is divided into four by an optical system consisting of, for example, four prisms, and the first and second optical images are formed at positions optically shifted by a predetermined pitch on each light-receiving surface. A feature is that a fourth solid-state image sensor is arranged.

In addition, by simultaneously driving the first to fourth solid-state image sensors in parallel in parallel and having N horizontal pixels and M vertical pixels, and processing signals taken out from each solid-state image sensor, the number of horizontal pixels is 2N and the number of vertical pixels is 2N. It is characterized by obtaining a high-definition video signal equivalent to the signal obtained from a 2M solid-state image sensor.

〔Example〕

FIG. 1 to FIG. 7 are diagrams showing one embodiment of the present invention, and FIG. 1 shows first to fourth solid-state image sensors 11 to 1.
4 (hereinafter abbreviated as A plates 11 to D plates 14). FIG.

As shown in FIG. 1, considering the A plate 11 as a reference, the B plate 1
Plate 2 is shifted by a predetermined pitch in the horizontal scanning direction, Plate C 13 is shifted by a predetermined pitch in the vertical scanning direction with respect to Plate A 11, and Plate D 14 is shifted by a predetermined pitch in both horizontal and vertical directions with respect to Plate A 11. ing. The above-mentioned pitch deviation amounts PN and PM are an integer of each horizontal and vertical pixel arrangement pitch of the A plate 11 to D plate 14, similar to the pixel shifting method shown in Japanese Patent Publication No. 56-40546. 1 and eggplant.

It is clear from prior applications that by adopting such an optical arrangement, the resolution in the horizontal and vertical directions is improved.

FIG. 2 is a diagram showing the configuration of an optical system for obtaining the optical arrangement shown in FIG. 1 above. 21 to 24 are first to fourth prisms, and there is a slight air gap between the first prism 21 and the second prism 22 and between the second prism 22 and the third prism 23. is formed. When light enters the first prism 21 through an imaging lens (not shown) disposed on the optical axis 30, when looking at the center light 31, first, the light enters the boundary between the first prism 21 and the second prism 22. Reflecting only 1/4 on the surface, 32
Then, it is totally reflected on the incident surface of the first prism 21 and becomes 33
and enters the C plate 13.

3/4 of the light 34 transmitted through the interface between the first prism 21 and the second prism 22 is transmitted to 1/3 (1/3 of the total) at the interface between the second prism 22 and third prism 23. 4)
The beam is reflected by the beam 35, and is totally reflected at the incident surface of the second prism 22 to beam 36, which then enters the B plate 12. 2/3 (2/4 of the total) of the light 37 that has passed through the interface between the second prism 22 and the third prism 23 is 1 at the interface between the third prism 23 and the fourth prism 24. /2 (1/4 of the total) is reflected and becomes 38, and the third prism 2
It is totally reflected at the incident surface of 3, becomes 39, and enters the D plate 14. 1/2 (1/4 of the total) of the light 40 transmitted through the interface between the third prism 23 and the fourth prism 24 is A.
The light is incident on the plate 11.

Note that the broken lines in the figure indicate the paths of light on both sides of the central light.

By adjusting the positions of the A plates 11 to D plates 14 in the arrangement shown in the second figure, the relative positional relationship shown in FIG. 1 can be achieved. In this case, the number of reflections of the light incident on the A plate 11 to the D plate 14 is as follows:
is 0 times, and the incident light 36. of the B plate 12 is 0 times. Incident light 3 on C plate 13
3. Since the incident light 39 on the D plate 14 is twice each,
No mirror image occurs in the light image incident on each plate. Therefore, the same type of 1151 elements can be used for the A plates 11 to D plates 14, and the scanning directions can also be the same.

Furthermore, since this optical system is a prism system and there is no intermediate relay lens system, registration adjustment, that is, image distortion adjustment, is easy. Regarding color separation, the color information incident on each board is R and G in parentheses in Figure 2.
, a dichroic filter may be configured on the reflective surface of the prism so as to be as shown in B, or the spectral characteristics of the reflective/transmissive surface of the prism may be made flat (N-D) and the A plate 11 to D plate A uniform color filter may be provided on each front surface of 14. Furthermore, color stripe filters or color mosaic filters having the size of the pixel order of each element may be provided on the surfaces of the A plates 11 to D plates 14.

In addition, as the A plate 11 to the D plate 14, for example, an NTSC image sensor may be used. Assuming that the number of effective pixels in the vertical direction in an NTSC image sensor is 490,
In this device, the number of pixels in the vertical direction is 490X2=98
It becomes 0. Therefore, a high-definition image with 980 effective scanning lines can be obtained. Note that when using the above-mentioned NTSC image sensor, the frequency of each pixel driving clock is equal to the original N
It is not limited to the driving clock of the TSC image sensor, and may be arbitrarily selected within the lock frequency range as long as it is operable. For example, when using a standard similar to the Japan Broadcasting Corporation's high-definition TV camera standard mentioned above, the number of scanning lines can be increased by adding 145 vertical blanking times to the effective number of 980 scanning lines. It may be made to have 1125 pieces. In other words, it is possible to select the optimum clock frequency that complies with the above standards.

Note that the size of the A plate 11 to D plate 14 shown in FIG. 2 is reduced to 2/3.
When using an inch lens, the F number of the imaging lens is F.
1 and 4, the entire volume of the first to fourth Bridims 21 to 24 is large enough to fit into a cube with one side of 50 mm. Therefore, it can be easily incorporated into a portable type device.

FIG. 3 is an enlarged view showing the arrangement relationship of each pixel of the A plate 11 to D plate 14 whose relative positional relationship is determined as shown in FIG. 1 in pixel order. However, this FIG. 3 is an example in which the pixels are shifted by 1/2 pixel pitch in both the horizontal and vertical directions.

Figure 4 shows the arrangement of each pixel in Figure 3, with G (green) on the A plate 11 and R (red) on the B plate 12 as shown in Figure 2.
, is a diagram showing a color pixel arrangement state when a color filter or a dichroic filter is provided so that color information of B (blue) is incident on the C plate 13 and G (green) is incident on the D plate 14.

If the number of pixels in the horizontal direction of the four image sensors is H2O2 and the number of pixels in the vertical direction is V490, then in the case of the model shown in Figure 4, the total number of pixels is 1.5 million color pixels, and the horizontal resolution is can exhibit performance equivalent to that of an image sensor with on the order of 1000 lines. Various conventional reading methods can be applied as the signal reading method for the A board 11 to the D board 14.
In this embodiment, a four-board simultaneous parallel reading method is adopted.

FIG. 5 is a block diagram showing signal processing means of the simultaneous parallel readout method. A board 11. B plate 12° C plate 13. As the D plate 14, an NTSC image sensor or one having a pixel configuration on the same level as this and having a color pixel arrangement as shown in FIG. 4 is used. Each of these A plates 11 to D plates 14 is G.

R, B, and G color images are projected.

A basic clock signal is output from the simultaneous signal generation circuit 51.

Horizontal and vertical synchronization signals, etc. are output. The image pickup device drive circuit 52 receives the signal from the synchronization signal generation circuit 51, generates a drive pulse, and supplies this to the A plates 11 to D plates 14 simultaneously and in parallel.

Therefore, each plate is driven in parallel. Here, as shown in FIG. 4, the first horizontal scanning line of the A plate 11 is A1, and the B plate 1 is
Assuming that the first horizontal scanning line of 2 is 81, the first horizontal scanning line of C plate 13 is 01, and the first horizontal scanning line of D plate 14 is Dl, AI.

B1. Each signal is read out from C1 and DI simultaneously. A
1. B1. After reading C1 and DI, next
2. B2. They are also read out from C2 and D2 at the same time.

Below A490,8490. Reading is performed sequentially up to C490 and C490.

The output signals from the A-plates 11 to D-plates 14 are amplified by a preamplifier (not shown), and then supplied to a sampling/holding circuit (not shown), where they are held in sipling at a timing synchronized with the basic zero signal. The signals are then supplied to the signal processing circuit 53 as original signals SG, SR, SS, and SG of each color.

According to the above-mentioned four-board simultaneous parallel readout method, the readout clock frequency of each board can be reduced, which has the advantage of facilitating circuit design and reducing power consumption.

FIG. 6 is a block diagram showing a more specific circuit configuration of the above-mentioned simultaneous parallel reading system. This circuit reads out A board 11 to D board 1 simultaneously at a slow clock frequency.
4 video signals are converted into horizontal progression for high-speed, high-definition images. For simplicity, A
The horizontal reading time of plates 11 to D plates 14 is 60 μs,
The readout time of the horizontal signal for high-definition images obtained is 30 μs, which is 172 seconds.

The reference clock sent out from the reference clock generation circuit 61 has a frequency twice that of the clock used in the NTSC image sensor, and this reference clock has a frequency of 1/2.
2 frequency divider 62. Readout control circuit 63.2 multiplier circuit 64
supplied to The divided output of the 1/2 frequency divider 62 is the A plate 11
~Clock frequency for operating the D board 14, for example, 7MH
It has two or more frequencies, the first. Second drive circuit 6
Supplied at 5.66. 1st. Second drive circuit 65.6
6 responds to a control signal from a readout control circuit 63.

The drive pulse sent out from the first drive circuit 65 is
1. It is applied to the B plate 12.

Signals are read from the A plate 11 and the B plate 12 in a form in which the pixels are shifted by a time of 60 μS72 N, where N is the number of horizontal pixels. On the other hand, drive pulses sent out from the second drive circuit 66 are applied to the C plate 13 and the D plate 14. The frequency of the drive pulse output from the second drive circuit 66 is the same as the drive frequency output from the first drive circuit 65, but the frequency of the drive pulse output from the C plate 13. The horizontal reading time from the D plate 14 is the A plate 11. The timing is such that it is delayed by 60/2 μs with respect to the B plate 12.

A board 11. The horizontal output signal from the B board 12 is supplied to the first switching circuit 67. The first switching circuit 67 is responsive to a reference clock as a control signal from the readout control circuit 63. Thus, by this switching circuit 67, the horizontal output signals from the A plate 11 and the B plate 12 are alternately sampled at the reference clock frequency. This sampled signal is 6 as a total horizontal scanning signal.
Although the time is 0 μs, the horizontal pixel information has a number of pixels 2N, which is twice the number of pixels of each of the A plate 11 and the B plate 12. The A1.81 outputted from the first switching circuit 67 at the timing shown in T1 in FIG.
The signal from C0D7 is an analog shift register.
1, it is immediately written at the timing shown at T2 in FIG. The above C0D71 is the readout control circuit 63
It operates with a reference clock from

On the other hand, C plate 13. The horizontal output signal of the D plate 14 is output from the A plate 11.
The signal is outputted with a delay of 30 μS from the horizontal output signal of the B board 12, and is supplied to the second switching circuit 68. Then, it is processed in the same manner as in the previous case, and becomes a signal with the timing shown at T4 in FIG. 7, which is immediately written to the CCD 72, which is an analog shift register, at the timing shown at T5 in FIG. .

CCD71. The horizontal output signal written to the CCD 72 is shown at 73. in FIG. The high-definition horizontal signal HDIH, which is read out with a clock having twice the frequency of the reference clock at the timing shown in T6, is output from terminal 75.76 for 30 μs.
Sent as HD2H.

In this way, two high-definition horizontal output signals are obtained from the four horizontal output signals of the A-board 11 to the D-board 14. in this case,
A1. B1. Since C1 and Dl are read out to the four main building rows in approximately 60 μs, and this becomes two 1-ID signals of 30 μs, time alignment is achieved by itself. In addition, CC
D73 and CCD 74 perform the writing and reading operations even when reading from the second horizontal scanning line of A plate 11 to D plate 14 continues as shown in 77 and TIO in FIG. This is a shift register provided so that processing can be performed without any trouble, and specifically, it is used to process even-numbered horizontal signals. Since its operation is similar to that described above, the explanation will be omitted. In this way, it is possible to read out 30 images per second.

In the embodiment shown in FIG. 6, existing NTSC image pickup elements, PAL elements, and SECAM elements can be used as they are, and the circuit configuration can be extremely simplified, which has the advantage of reducing costs. However, A plate 11 to D plate 14
The problem is that the circuit system for obtaining high-definition output is specified depending on the basic operating system. For example, as an image sensor, there are the following variations even within the NTSC system, and a high-definition circuit system suitable for each is required.

(1) Half-bit element (number of vertical scanning lines: approx. 240) (2) Full-bit element (number of vertical scanning lines: approx. 480 to 49)
0) (3) Interlace readout element (4) Non-interlaced readout element (5) Horizontal 2-line simultaneous readout element (6) TV mode element (video mode) (7) Still image mode exclusive element (8) Frame readout Readout element (9) Field readout element (10) Variable storage time element There are also many variations in high-definition image applications, as described below.

(11) High-definition TV camera (video) (12) High-definition electronic camera (still image) (13) Printing plate-making camera (14) Image processing camera Therefore, depending on the application, a method that is not subject to the above-mentioned restrictions is desired. .

Figure 8 shows the patent application Nos. 57-144-559 to 1 filed by the present applicant.
44561 is a block diagram showing a signal processing means using a pixel memory for an image sensor; FIG. The method shown in this figure is effective as a method for converting signals from four image sensors into high-definition signals using small-capacity memory, and has the characteristic that it is not restricted by the readout method specific to the image sensor. .

In particular, this method is suitable for the above-mentioned (12), (13), and <14) still image recording applications.

In FIG. 8, the reference clock generation circuit 81 has a 14MH clock.
2 clock is generated. The frequency of the above clock is divided by 1/2 by a 1/2 frequency divider 82 to become a 7MH2 clock.

This 7MH2 clock is supplied to the drive circuit 83.

The drive circuit 83 generates an H clock, a (2) clock, etc., and supplies these to the A boards 11 to D boards 14 in parallel.

Since the A plates 11 to D plates 14 can be driven at exactly the same timing, a single drive circuit 83 may be used.

From the image sensor to the pixel memory, the A to D series perform the same operation, so the A series will be explained. Analog signals, which are the photoelectric conversion outputs of each pixel, are read out in time series from the A-board 11 which is in readout mode in response to drive pulses from the drive circuit 83. This read output includes not only analog charge information of each pixel but also position information of each pixel. That is, in the solid-state R element, the positional relationship of each pixel is fixed with high precision, so the clock count value during clock operation becomes positional information. Therefore, in the circuit of FIG. 8, the clock of 7MH2 is set to 11.
A preamplifier 91. A sampling hold (S/H)
Circuit 101. A analog-to-digital (A/D) converter 111. This is to ensure that the pixel position information is not lost by supplying it to all of the A pixel memory 121. However, a clock is applied to the pixel memories 121 to 124 through a pixel memory write control circuit 84.

The output of the A plate 11 is amplified by the preamplifier 91 and
The /H circuit 101 samples and holds the signal in synchronization with the 7 MHz tarlock. The sampled and held analog voltage is A/D converted into a digital signal with a digitization bit count of 5 bits to 10 bits by an A/D converter 111 that also operates in synchronization with a 7 MHz clock.
converted and written into pixel memory 121. In this case, the image information written in the pixel memory 121 is
The data is written to corresponding addresses in the memory 121 that correspond one-to-one to all pixels of 1. For this reason, the pixel memory 1
The positional information of each pixel of the A plate 11 is also held in 21 at the same time.

That is, in the system shown in FIG. 8, all photoelectric conversion information of the A plate 11 including position information is stored in the pixel memory 121. B plate 12° C plate 13. Similarly, the contents of D board 14 are changed to B at the same timing as the contents of A board 11.
, C, and D are stored in each pixel memory 122, 123, and 124. Therefore, the reading method for each board is A, B, C, and D.

Regardless of the element structure described in (1) to (10) above, the original image information is stored as a digital signal in the pixel memories 121 to 124. As a result, the problem of matching the readout method of the image sensor and the required high Mtia signal method with the system shown in FIG. It will be solved by how you do it.

Reading from the pixel memories 121 to 124 of AD is performed as follows. 14M)-12 reference clock is passed through the doubling circuit 85 to become a 28MHz reference clock,
This is supplied to the pixel memory readout control circuit 86. In addition, as a clock equivalent to the above 28MH2, 7
The four-phase clock of MH2 may be directly supplied to the control circuit 86.

The methods of the readout control circuit 86 are A and B.

It may be determined by taking into consideration the pixel shift patterns of each of the C and D plates 11 to 14, the readout system two-color filter arrangement, etc., and also taking into account compatibility with the format of the high-definition signal.

The control signal from the readout control circuit 86 is supplied to the pixel memories 121 to 124 and the D/A converter 87.

Thus, writing to each of the pixel memories 121 to 124 is performed at 7 MHz, and reading is performed using a 28 MHz or 7 MHz four-phase clock from the readout control circuit 86. Therefore, 4 pixel memories 1
The outputs from 21 to 124 are time series signals corresponding to 28 MHz. This signal is transferred to a D/A converter 87 operating at 28MHz.
The signal is converted back to an analog signal at the terminal 88, and output as a high-frequency, high-definition signal from the terminal 88. Note that the high-definition signal becomes an image signal that can be displayed via a process circuit, a matrix circuit, and an encoder (not shown).

Note that the number of times the pixel memories 121 to 124 are read out per second is 3.
By setting the number of times to 0 or 60 times, a still image can be displayed on a monitor operating in TV mode.

In this way, according to this method, the pixel memories 121 to 124
The reading mode can be electrically set freely. Therefore, it is possible to realize a high-definition signal conversion method that is not restricted by the readout method of boards A to D.

Further, according to this method, a plurality of image sensor drive circuits 65, 66 and switching circuits 67, 68 as shown in FIG.
．． Not only can the analog shift registers 71 to 74 be omitted, but also various types of image pickup devices can be used simply by changing the readout mode of the pixel memory readout control circuit 86. Furthermore, high-definition signals in various formats can be obtained by changing the readout mode.

Furthermore, the circuits before the pixel memories 121 to 124 can basically operate with a low-speed clock (7 MHz), which is advantageous in terms of power consumption, element cost, etc.

FIG. 9 is a block diagram showing signal processing means that can be used in a video mode such as a VTR. Pixel memory 121
The structure from 124 to 124 is the same as that in FIG. The output of pixel memories 121 to 124 is pixel memory readout/D/A
D/A converters 131 to 4 that perform low-speed clock operations (7 MHz) according to control signals from the control circuit 89;
The signals are converted into analog signals at 134 and supplied to FM modulation/recording amplifiers 151 to 154 via LPFs 141 to 144.

Then, after being FM modulated and current amplified here,
The signal is supplied to four magnetic heads 161 to 164 and recorded in four channels on the magnetic disk 170. the result,
The G, R, B, and G color signals output from the A plates 11 to D plates 14 are recorded on independent magnetic tracks. Therefore, color mixing is less likely to occur. However, with this method, phase shifts tend to occur in each of the G, R, B, and G channels during reproduction. Therefore, it is desirable to record the phase reference signal multiplexed on the color signal.

In another embodiment shown in FIG. 9, digital recording is performed by directly connecting the digital outputs from the pixel memories 121 to 124 to a recording amplifier, taking advantage of the low readout speed of the pixel memories 121 to 124. You can also do that.

As described above, the present device has the following effects.

High-definition image sensors, which have too many pixels to be made as a single-chip device, are difficult to manufacture, and have problems in terms of yield and cost. realizable.

With a single-chip element, the readout speed of the image sensor is faster (~30
MH2), making it difficult to manufacture and increasing power consumption, but with this device, the speed can be significantly reduced and power consumption can be reduced.

Single-chip elements require microfabrication such as stripe filters or mosaic filters, and these filters also need to be installed in alignment with each pixel.
Although the work process becomes extremely complicated, according to this method, it is only necessary to attach a full-surface filter to each image pickup plate or to attach a dichroic surface to the optical system, so the filter configuration is greatly simplified.

For a 2/3-inch class single-plate element, the manufacturing rule must be about 1 μm, but the device used in this device can be manufactured satisfactorily with a 2 μm rule.

The four image sensors are NTSC, PAL, and SE.
Conventional elements such as CAM or elements with higher resolution can be used.

By adopting a new four-plate optical system, the optical system can be significantly downsized.

By adopting a new four-board signal output parallel processing method, the circuit is significantly simplified. Additionally, it can support various high-definition formats.

〔Effect of the invention〕

According to the present invention, an optical image obtained through an imaging lens is divided into four parts by an optical system including, for example, four prisms,
The first to fourth solid-state imaging devices are arranged so that the above-mentioned light images are formed at positions optically shifted by a predetermined pitch from each other on each light-receiving surface.

In addition, by simultaneously driving the first to fourth solid-state image sensors in parallel in parallel and having N horizontal pixels and M vertical pixels, and processing signals taken out from each solid-state image sensor, the number of horizontal pixels is 2N and the number of vertical pixels is 2N. It is designed to obtain a high-definition video signal equivalent to the signal obtained from a 2M solid-state image sensor.

Therefore, according to the present invention, it is possible to provide a compact and simple-configured imaging device that is capable of increasing resolution not only in the horizontal direction but also in the vertical direction, and is equipped with an optical system and an imaging system that can significantly improve the resolution.

[Brief explanation of drawings]

1 to 7 are diagrams showing one embodiment of the present invention, and FIG. 1 is a diagram showing the relative optical arrangement of four solid-state image sensors;
Figure 2 is a side view showing the 4-split optical system, Figure 3 is an enlarged view of the pixel order showing the pixel configuration of four image sensors, and Figure 4 is an enlarged view of the pixel order.
The figure is also an enlarged view of the pixel order showing the color pixel arrangement state,
FIG. 5 is a block diagram showing the signal processing means of the simultaneous parallel readout method of the image sensor, FIG. 6 is a block diagram showing the configuration of FIG. 5 in more detail, and FIG. 8 and 9 are diagrams showing other embodiments of the present invention, respectively, and FIG. 8 is a block diagram showing a signal processing means using a pixel memory for an image sensor, and FIG. FIG. 2 is a block diagram showing a signal processing means that can be used in a moving image mode. 11...A plate (first solid-state image sensor), 12...h
plate (second solid-state image sensor), 13...C plate (third solid-state image sensor), 14...D plate (fourth solid-state image sensor)
, 21-24...first to fourth prisms. Applicant's representative Patent attorney Atsushi Tsuboi Figure 1 Figure 2 Figure 3 Rotation 0 Round 0 Roro Recapitalization Diagram Prisoner I Prisoner Diagram 4 Rorororo Roro--AI, B1 0 Rororo Roro-CI, 01 Mouth Mouth Roro--A2.82 Japan-Russia-Japan Roro-Japan-C2, D2 0 mouth turn mouth mouth low" A3. 田ロロロロ round round low--C3, D3 0 mouth turn round [ii] low A4. B4

Claims (4)

[Claims] (1) An imaging lens, an optical system that divides the optical image obtained through the imaging lens into four optical images, and each optical image divided into four by this optical system are optically connected to each other on each light receiving surface. The first one is arranged so that the image is formed at a position shifted by a predetermined pitch.
- A fourth solid-state image sensor. (2) In the first to fourth solid-state image sensors, the position of the light image formed on the second solid-state image sensor is horizontal with respect to the position of the light image formed on the first solid-state image sensor. The position of the light image formed on the third solid-state image sensor is shifted by a predetermined pitch in the vertical direction, and the position of the light image formed on the fourth solid-state image sensor is shifted both horizontally and vertically. The fjIIi device according to claim 1, wherein the fjIIi device is positioned so as to be shifted by a predetermined pitch. (3) The predetermined pitch is selected to be an integer fraction of the pixel arrangement pitch of the first to fourth solid-state image sensors. 2
). (4) An imaging lens, an optical system that divides the optical image obtained through the imaging lens into four optical images, and each optical image divided into four by this optical system is optically positioned in a predetermined manner with respect to each other on each light-receiving surface. first to fourth solid-state image sensors each having a horizontal pixel number N and a vertical pixel number M arranged so as to form images at positions shifted by a pitch;
By simultaneously driving these first to fourth solid-state image sensors in parallel and processing the signals taken out from each solid-state image sensor, a high-speed signal equivalent to that obtained from a solid-state image sensor with 2N horizontal pixels and 2M vertical pixels can be obtained. 1. An imaging device comprising means for obtaining a fine video signal.