JPS60142625A - Digital to analog converter - Google Patents

Abstract

PURPOSE:To obtain a wide dynamic range, simplify constitution, and facilitate the formation of a complementary MOS integrated circuit by raising input digital data which is raised to the (1/n)th power to the (n)th power through a digital/ analog converter. CONSTITUTION:A 16-bit digital audio signal is processed by a digital signal processor DSP11 for extraction of square root to obtain an 8-bit compressed signal. This is loaded in a counter 53 through a shift resistor SR51 and clock pulses begin to be counted; and an integrator 7 integrates the output current I of a constant current 55 and the output 1/2I.TF<2> of the integrator 7 is obtained at the point TF of point when the contents of the counter 53 attain to 0. The square- law D/A conversion is carried out, so the wide dynamic range is obtained. Further, complementary MOS IC implementation is facilitated because a single constant current power source is used.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of Industrial Application The present invention is a digital/
Regarding analog converters.

Background art and its problems Discs on which digitally converted acoustic signals (hereinafter referred to as digital audio signals) are optically recorded and their playback devices, as well as digital audio recording and playback devices using magnetic tape as recording media, are already commercially available for consumer use. has been done.

By the way, in digital audio signal processing equipment, non-linearity and monotonically increasing characteristics are emphasized, quantization noise has a negative effect on the playback quality at low levels, and the dynamic range of human hearing is as wide as about 120 dB. The larger the number of bits of the digital signal, the better; generally, the number of bits is 14 to 16 and the processing speed is 20 μs or more.

However, for example, digital/analog converters (
In order to simply convert the digital audio signals mentioned above in a D/A converter (hereinafter referred to as a D/A converter), an ultra-high-speed clock signal such as 2" + 20 μs #3.3 GHz is required, and this cannot be realized. Therefore, in an actual D/A converter, for example, 2" ÷ 20 μS # 13 MHz
A clock signal of about 100 MHz is now sufficient. Counter-type D/A converters that provide high accuracy with a simple configuration have been highly praised.

First, an example of a conventional D/A converter for digital audio signals will be described with reference to FIGS. 1 to 3.

In Figure 1, (1■) and (IL) are each 16
This is a shift register corresponding to the upper 8 bits and lower 8 bits of bit input data, and LSB first (first) serial type 16-bit digital audio data is supplied from the input terminal (2a). A shift clock is supplied from 2b). The digital audio data converted into parallel data in both shift registers (Iff) and (IL) is divided into upper 8 bits and lower 8 bits and supplied to an upper counter (3H) and a lower counter (3L), respectively.

(5H) and (5L) are constant current sources corresponding to the upper 8 bits and lower 8 bits of the human data, respectively, and the output current I) of the upper current source (511) and the lower current source (5L
) and the output current It is set to IH/IL=28. These IH and I are supplied to an integrator (7) via electronic switches (6H) and (8L) controlled by upper and lower counters (3H) and (3L), respectively, and a resistor network RN.

The integrator (7) consists of an operational amplifier (7A) and an integrating capacitor (
7C), and a reset electronic switch (7C) such as an FET in parallel with the integrating capacitor (7C).
S) is connected. The output voltage of the integral m (71) is led out to the output terminal 0ω via an electronic switch (8) and a low-pass filter (9).

Now, when the load pulse is supplied from the LOADM input terminal (4a) as shown in FIG. 2A to the upper and lower counters (3H) and (3L) and the integrator (7), both counters (3H) and ( The upper 8 bits and lower 8 bits of the human-powered digital audio data are loaded into the shift registers <1)I) and (IL), respectively, from the shift registers <1)I) and (IL). At the same time, the load pulse closes the switch (7S) of the integrator (7th line), the charge of the integrating capacitor (7C) is discharged, and the output voltage of the integrator ear becomes OV. Time T when the load pulse disappears.

, the upper counter (3N) and the lower counter (3N)
L) simultaneously starts counting the clocks supplied from the input terminal (4h). Then, both counters (311)
Borrow signals BRW (H) and BRW (L) as shown in FIG. 2B and (C) are respectively supplied from switches (6H) and (6L) from
6■) and (6L) are closed.

By closing both switches (6H) and (6L), the constant currents IN and IL from the upper and lower current sources (5H) and (5L) are passed through the resistor network RN to the integrator (7).
supplied to On the other hand, the switch (7S) of the integrator (7)
The force (off) causes the integrator (7) to start integrating.

Both the upper and lower counters (311) and (31,) are down counters, and are loaded with the upper and lower bits of the digital audio signal, respectively, and run the clock until the count reaches zero. In this way, the time corresponding to the input digital data is set.

For example, suppose that the lower counter (3L) becomes 0 at time TL, and the upper counter (3) becomes 0 at time T)I. The integrator (7) is connected to the upper current source (5) from the time To.
Current IH of H) and current IL of lower current source (5L) are supplied, and the output voltage of the integrator (7) is equal to the current (IH+
IL).

At time TL, the lower counter (3L) °BRW(
L) signal disappears and the switch (6L) is opened, so the supply of the current It of the lower current source (5L) is cut off, and from time TL onwards, the output voltage of the integrator (7) is the same as that of the upper current source (5L).
H) rises at a slope corresponding to the current IN. Similarly, at time TH, the upper counter (3H) is connected to the upper current source (5H).
After the time TH, the output voltage of the integrator (7) corresponds to the input digital audio data, i.e., until the integrating capacitor (7C) is discharged by the next load pulse. A constant value proportional to the instantaneous level of the original sound signal (I L ・(TL TO) +I
Maintain H.(TH-To)). This pattern is shown in the second diagram.

A sampling pulse of a certain width as shown in Fig. 2 is applied to the switch (
8), and the constant value output voltage of the integrator (7) is extracted by the analog switch (8) with a constant pulse width, as shown in FIG. 2F.

Generally, each sample value of the original audio signal is different from each other, and each data of the corresponding digital audio signal is also different, so the integration period of each time is T, as shown in FIG. 3A.
'+T2+T3, and accordingly, the output of the integrator (7) also changes as Vl, V2°■3. The analog switch (8) operates during the high level period shown in Figure 3B, and the output of the extracted integrator (7) is shown in Figure 3C.
The result is a PAM signal as shown in . This PAM signal is restored to an audio signal through a low-pass filter (9) and is applied to the output terminal Oω.

In the conventional counter type D/A converter as described above, two bits corresponding to the upper eight bits and the first eight bits are
It was difficult to set the current ratio (2":1) of two constant current sources with high precision. Also, since a 2111i1 constant current source was required, power consumption was reduced by complementary MO3 integrated circuits. It was also difficult to

This problem arises because the number of bits of the digital audio signal is large. Looking back,
For audio signals, the most important point is a small distortion rate, which is a factor relative to the signal level, so if the number of bits can be compressed using techniques such as nonlinear quantization, the above problems can be solved by itself. It will be possible.

In view of the above, an object of the present invention is to provide a counter type suitable for digital audio signals, which can obtain a wide dynamic range even with a small number of bits, has a simple configuration, and is easy to integrate into a complementary MO3 integrated circuit. There are several types of D/A converters available.

Summary of the Invention The present invention provides a digital signal processing device that performs an l/n power operation on input digital data, and a digital/analog conversion means that converts the output digital data of this digital signal processing device into an analog signal corresponding to the nth power of the digital signal processing device. A digital/analog converter consisting of

According to the present invention, a wide dynamic range can be obtained, the configuration is simple, and complementary MO'S integrated circuits can be easily implemented.

EXAMPLE Hereinafter, an example of the present invention will be described with reference to FIGS. 4 to 12.

In this embodiment, when a human-powered digital audio signal is represented by (x) )2 . . . The square calculation process expressed by (2) is performed. In this equation (2), (1
Substituting Equation 1 gives g (x) = x (3), and the signal subjected to the square calculation process becomes equal to the ring digital audio signal. These square root and square calculations are performed by a digital signal processing device (Digital), which will be described later.
1 Signal Processor (hereinafter referred to as DSP) and a modified counter type D/A converter.

DSP processes digital signals in the time axis and frequency domain.
It processes numerical calculations for operations in real time, and its feature is that it uses an ALU (it) with a relatively long word length.
! It has hardware such as a scientific arithmetic unit and multiplier,
It is microprogram controlled. The configuration is such that digital signal processing operations can be managed by a host computer system using a microprocessor or the like. Furthermore, by using RAM as the microprogram memory and coefficient memory, data in these memories can be transferred from the host computer system, and data in the coefficient memory and microprogram memory can be transferred from the host computer side while the microprogram is being executed in the DSP. Can be changed.

411th! FIG. 1 is a block diagram showing an example of the configuration of a basic system of a digital signal processing device using a DSP, which has already been proposed by the applicant of the present invention, to which the present invention is applied. In this FIG. 4, for example, a DSP (11) and a memory control unit (12) (Memory Control
IJnit, hereinafter referred to as MCU. ) are each LSI
It is used as a standardized electronic component.

The digital signal memory (13) stores, for example, a digital signal of 24 bits per word into 64 words (65°5
36 words), and a D-RAM (dynamic random access memory) or the like is used. The host computer system (14) is configured using, for example, a so-called microprocessor, and manages digital signal processing operations by the DSP (11) and MCU (12).

In addition, in this configuration example, the host computer system (14) is connected to the microprogram memory (1
6) and coefficient memory (17).

An address control section (18) for accessing each word of the digital signal memory (13) is provided inside the MC1J (12). This address control section (
18) includes incrementers, comparators, etc., and D
The operation is controlled according to various control signals from the sequence control section (19) of the SP (11,). In addition, MCU (1
2) includes an interface circuit (20) for transmitting and receiving signals with the host computer system (14).
), a scratch pad memory (21), etc. are provided.

In a system using such a DSP (11) as shown in FIG. 4, the digital audio signal to be subjected to signal processing is divided into, for example, 16 Quantized in bits. By the way, in consideration of the fact that the number of bits increases when a coefficient is multiplied with this digital signal of 16 bits per word, in a system using a DSP (11), for example, a digital signal of 24 bits per word is It is configured so that it can be handled easily.

Next, a more specific example of the circuit configuration inside the DSP (11) will be described with reference to FIG. In these figures 4 and 5, there is a 24-bit data bus DB inside the DSP (11), and this data bus DB is connected to an arithmetic processing unit (30), an input register (22), and an output register. -C is connected to a register (23) and a digital signal input/output port (24). The input register (22) converts the serial data from the data input terminal (26) into 24-bit parallel data and puts it on the data bus DB, and the output register (23) converts the 24-bit parallel data from the data bus DB into serial data. Convert it to the data output terminal (
27). The arithmetic processing unit (30) is provided with at least an ALU (logic unit) (31) and a multiplier (32).
1) In conjunction with the multiplier (32), the multiplexer (
33) is provided. In addition, a data memory (a so-called scratch pad memory) that temporarily stores intermediate data etc. during processing operations in the arithmetic processing unit (30) is also provided.
40) and a temporary register (42). The data memory (40) has a storage capacity of, for example, 256 words (24 bits per word). next,
The coefficient data that becomes the multiplier in the multiplier (32) is, for example, 1
Although each word is 12 bits, the coefficient memory (17) that stores this coefficient data is made up of, for example, 1 word (16 bits), and stores 2 pages (16 bits x 1024 words) with 512 words as one page. It is possible. Each word of this coefficient memory (17) is accessible by address information from a coefficient pointer (17a). The output terminal of this coefficient memory (17) is connected to a terminal for inputting coefficient data X of each of the multiplier (32) and multiplexer (33), and this connection point is connected to a 24-bit data bus DB. ing. Further, the data bus DB is connected to a terminal for inputting the multiplicand data Y of the multiplier (32), an output terminal of the data memory (40), and an input terminal of the temporary register (42).

The multiplexer (33) has, in addition to the input terminal for the coefficient data 12-bit logical shift (11-bit arithmetic shift) to the right (lower direction)
An input terminal for input data PP is provided, and the output of this multiplexer (33) is sent to an ALU (logical operation unit) (31). In the ALU (31),
A shift logic circuit (35) for focus shift processing is provided. The contents of the flags that change according to the arithmetic processing in this ALU (31) are stored in the status register (36).
), and the 24-bit digital data as the calculation result is stored in the data bus DB and also in the multiplexer (4
3) to a data memory (4o), respectively. The other input terminal of this multiplexer (43) receives output data T from the temporary register (42).
P is being sent.

Next, the microprogram memory (16)
A so-called microprogram is stored that instructs the processing procedure for each part of the sequencer (11).
The microinstructions of the microprogram are sequentially read out by the address signal from 9a). This microinstruction has a word length of, for example, 32 bits and is sent to the instruction data bus IDB via the pipeline register (16a). Here, one 32-bit microinstruction word is divided into several fields, such as a field to which immediate data is delivered,
Field that controls data memory (40), ALU
(31) Field that controls sequencer (19a)
Fields etc. are provided to control the. The immediate data in the microinstruction is transferred to the data bus DB.
The control data of the data memory (40) is sent to the data memory (40) via the multiplexer (44).
low address input port. Sequencer (
19a), the address to be read next in the microprogram memory (16) is determined by the sequencer control data in the My20 instruction and status data (state of flags, etc.) from the status register (36). The output control logic circuit (19b)
This is a circuit unit for controlling U(12), and its operation is controlled by microinstructions. This output control logic (1
9b) and the sequencer (19a) constitute a sequence control section (19) in FIG.

In addition to this, the above data memory (40
) and the bit that increments the data pointer (45) that indicates the upper address of the coefficient pointer (1
7a), etc. are included.

Next, data from the host computer system (14) consists of 1 word of 8 bits, and these 8-bit data Bo=Bv are sent to the interface circuit (15).
It can be written to the microprogram memory (16) and the coefficient memory (17) via the microprogram memory (16).

Here, the microprogram memory (16) and coefficient memory (17) are connected to the host computer system (1).
4) The memory map when viewed from the side is shown in FIG. As is clear from FIG. 6, from the host computer side, one word is 8 bits (1 byte), which can be seen as the previous 4096 words (212 bytes) of memory MR, and the 12-bit address A.

~A1'1 allows access in byte units. Divide this memory MR into two equal parts, and divide one half into 2048 bytes, that is, the address value is $000 in hexadecimal notation.
~$7FF is defined as an area MPM corresponding to the program memory 6, and the other 2048 bytes (the address value is $800~$FPF) is defined as an area CFM corresponding to the coefficient memory 7. Also, coefficient memory area CF
The 2048 bytes of M are further divided into two equal parts, one of which is $8.
00~$ BFF is base O, the other $000~8
PFF is set to bege 1. In this way, when accessing from the host computer side, the 12-bit address A o = A l'l allows $000 to $FF
The 4096 bytes of F can be accessed in byte units, but inside the DSP (11), the program memory area MPM is accessed by the sequencer (19a) and stores 32-bit microinstruction data Io to I3.
1 are read out at the same time, and the coefficient memory area CFM is accessed by the coefficient pointer (17a) to read out 16-bit coefficient data K o '' K 15 at the same time.

In this case, 9 bits corresponding to A2 to Aso are used as the address from the sequencer (19a),
512 words (32 bits per word) are accessed, and 9 bits corresponding to A1 to A9 are used as addresses from the coefficient pointer (17a) for accessing 512 words per page. The page to be accessed in this case is determined by the contents of the bits of the page switching control signal PAGE in the control data from the host computer side.

Next, the 8-bit signal from the host computer system (14) is converted into 2-bit mode switching signals R5O, R3.
According to I, DS is generated as four types of signals with mutually different contents.
It is sent to P(11,). That is, FIG. 7 is a diagram showing the contents of the 8-bit signal corresponding to this mode switching, and the mode switching signals R3O and R3I correspond to four switching states from I'OOJ to "11". Four modes are shown: data mode MO1, upper address mode Ms, lower address mode M2, and control mode M3. As is clear from FIG. 7, in the data mode Mo, each bit of 8-bit data from the host computer system (14) Bo=Bt
are the data DO to D7 actually written in the areas MPM, CFM, etc., and in the upper address mode M1, bits BO to B3 are the upper 4 bits of the address A8 of the 12 bit address for accessing the memory MR. ~A I+, and ■(In the rising address mode M2, bit Bo=Bv becomes the lower 12 bits of the address AO to A7. Also, in the control mode M3, each bit BO to B? of the above 8-bit data is , are used as control signals, for example, beep)B
v is the page switching control signal PAG[! of the 1st coefficient memory area CFM. It is used as a seal.

To obtain 8-bit data by performing the square root calculation using SP as described above, a sequential comparison method as shown in the following equation (4) is used.

y=2-1-87 +2-2, a6→-・----
-1-'1-B-a.

A flowchart of this square root calculation is shown in FIG.

That is, first, it is determined whether input data is positive or negative, and 0 or 1 is set as a polarity flag. Next, to calculate the first term of equation (4), 2-(n+11 with n=0)'1'=
(Comparing the magnitude of +A and X, the coefficient a7 of the first term is 1
or 0. Furthermore, let n = 1′(,
The magnitude of y2'=(+)' and X is compared to determine the coefficient a6 of the second term. Hereinafter, by performing similar calculations up to n-2°3...7 to determine a5 to aQ, this 8-bit data of F can be obtained.

Note that the final determination of the polarity flag is performed in the D/A converter.

As can be seen from this flowchart, in the square root calculation using equation (4), the coefficients are changed during the execution of the calculation, so the above-mentioned D
SP is extremely useful.

The 16-bit digital audio signal supplied to the DSP is expressed in two's complement form, and for simplicity, if we use 3 bits as an example, the values from the maximum positive value to the maximum negative value are sequentially 011.010.001. .000.111°110,
It looks like 101.100. That is, the most significant digit (M
0.1 of SB) is the sign bit that represents the positive or negative polarity of the audio signal, and the number from the next digit (23B) to the least significant digit (
LSB) represents the absolute value of the audio signal. Therefore, in a DSP, a digital audio signal is first separated into a sign bit and an absolute value bit, and a square root operation is performed on the signal. At this stage, the bit length of the absolute value of the digital audio signal is rounded up by 15/2 and compressed to 8 bits.

FIG. 9 shows the configuration of an embodiment of a D/A converter according to the present invention. In FIG. 9, parts corresponding to those in FIGS. 1 and 4 are given the same reference numerals, and redundant explanation will be omitted.

In FIG. 9, (51) and (53) are a shift register and a counter, respectively, and as described above, 5P
8-bit serial digital audio data compressed by (11) is supplied to a shift register (51), converted into a parallel format, and supplied to a counter (53). (54) is a drive circuit, in which the sign bit from the DSP (11) is supplied to one NAND circuit (54P) via a NOT circuit (54A), and is also directly supplied to the other NAND circuit (54N). Supplied. Furthermore, a pollo signal BRW is supplied from the counter (53) to both NAND circuits (54P) and (54N). (55) is a constant current source similar to the aforementioned constant current source (5H), and its output current I is supplied to the integrator (7). The output of the integrator (7) is divided into two parts, one of which is fed directly to one switch (58P) and the other to the other switch (58N) via an inverting amplifier (56). Ru. The output sides of both switches (58P) and (58N) are both connected to a low pass filter (9).

The operation of this embodiment is as follows. When the load pulse n shown in FIG. 10A is supplied to the counter (53) and the integrator (7), the counter (53)
) is loaded with compressed 8-bit data from the shift register (51), and at the same time the charge of the integrating capacitor of the integrator (7) is discharged.

From the time To when the load pulse disappears, the counter (53
) starts counting clock pulses, the discharging switch of the integrating capacitor is opened, and the integrator (7) starts integrating the output current ■ of the constant current source (55). During the counting operation, the counter (53) outputs a borrow signal BRW, which is shown in FIG. Depending on whether the polarity of the signal is positive or negative, either one NAND circuit (54P) or the other NAND circuit (54N>) of the drive circuit (54) switches one switch (58P) or the other corresponding switch. switch (58
Apply a negative drive signal to N > to turn it on.

Therefore, the output of the integrator (7) rises at a slope corresponding to the constant current I at 9'9 as shown in FIG. , or an inverted amplification device (
56).

At the time TF when the counter (53) reaches 0, the switch (58P) or (58N) turns off,
As is clear from FIG. 10C, the output (voltage/time product) of the integrator (7) taken out during the operation of the counter (53) becomes +■·TF2. As mentioned above, the counter (
The time TF set by the count in 53) corresponds to the input digital data to which this counter is preset.
There is. Therefore, it is clear that the output (voltage/time product) taken out from the integrator (7) mentioned above corresponds to the square of the human input digital data.

Similarly to the above, when the time set by the counter (53) changes as T a, T b, T c as shown in FIG. 11A in response to the instantaneous level of the original audio signal. , switch (58P) or (58N) is turned on for only that time, as shown in FIG. and,
The voltage/time product taken out from the integrator (7) changes as shown in FIG. At the output of the low-pass filter (9), an analog voltage having the square value of the instantaneous level of the original audio signal is returned.

The input/output characteristics and resolution of the square D/A converter of this embodiment are plotted in FIG. 12 (both the vertical and horizontal axes are in og2 scale). In Fig. 12, the straight line σ■ connecting point A, which corresponds to 8 bits of input and 16 bits of output, and the origin O is squared D/
This shows the input/output characteristics of the A converter, and a dynamic range of 16 bits is obtained for an 8-bit input.

Further, the resolution in this case can be determined from the following equation (5).

(28-1)"(2'-1-1)' = 509#2
(5) Therefore, the operating range of the square D/A converter of this embodiment is point B where the input is 1 bit and the output is 2 bits, and point B where the input is 8 bits and the output is 9 bits. It is represented by a triangle defined by point C and point A mentioned above.

According to this embodiment, since square/A conversion is performed, a wide dynamic range can be obtained. Furthermore, since a single constant current source is used, it is easy to implement a complementary MO3 integrated circuit. Furthermore, since the voltage/time product is used as the output of the integrator, it is resistant to noise and has stable operation.

In the embodiment 111, although a wide dynamic range can be obtained, the resolution is not necessarily sufficient.

When performing square root calculation in DSP, this is the above-mentioned (
As is clear from the formula 4) or the flowchart of FIG. 8, this is because the absolute value data is limited to the upper 8 bits and the lower bits are discarded.

The 16-bit absolute value data of human power is A, and this person is D.
In SP, n in equation (4) is up to 15, or the 8th
In the figure, let the loop counter be n-16, and the square root-processed 16-bit data be B(=/'rt, and the value obtained by adding 1 to the upper 8 LSBs of this B is BH1. If the error due to truncation is d, then The following equation (6) holds true.

d=BH2-A (6) On the other hand, if the truncated lower 8-bit data is BL, then the following equation (7) holds true.

B L = u...(7) f61. +71 By rearranging both equations, the following equation (8) is obtained.

A=BH2-BL2 (8) From this equation (8), it can be seen that a more preferable result can be obtained by negative feedback of the square operation data of the lower pitch (BL).

Next, other embodiments of the D/A converter according to the present invention will be described with reference to FIGS. 12 to 15.

FIG. 13 shows the configuration of another embodiment of the present invention. This first
In FIG. 3, parts corresponding to FIGS. 1, 4, and 9 are designated by the same reference numerals, and redundant explanation will be omitted.

In FIG. 13, (51H) and (51L) are shift registers supplied with the above-mentioned serial upper bit (BH) and serial lower bit (BL), respectively;
501) and (51L), the parallel upper bits BH and parallel lower bits BL are supplied to the corresponding upper counters (53H) and lower counters (531,), respectively. These shift registers (51H
) , (51L) and counter (5311).

(53L) operates in exactly the same way as the shift register and counter shown in FIG.

The borrow signal BRW (H) of the upper counter (53H) is directly supplied to the AND circuit (59),
The borrow signal BRW (L) of the 2-T circuit (3L) is
60) to the AND circuit (59).

If the borrow signals BRW (H) and BRW (L) from both counters (53■) and (53L) are as shown in FIG. 14B and C, respectively, then the AND circuit (59)
From time TL to time T)I, as shown in the same figure,
Output can be obtained only during the period up to This AND circuit (59
) and the sign bit from the DSP (11) are supplied to the drive circuit (54).
The upper counter (53
11) until count end point r, H switch/chi (
58P) EL (58N) is turned on, and the output of the integrator (7) is taken out as shown in FIG. 14E. This extracted output of the integrator (voltage/time product) is nothing but the squared difference calculation result of the above-mentioned equation (8).

The operating range of the D/A converter of this embodiment can be determined as follows.

In FIG. 12, let D be the intersection of a straight line passing through point C and parallel to the horizontal axis and straight line AO. Let E be the intersection of the straight line passing through the dot and parallel to the vertical axis and the straight line BC.

Let F be the intersection of a straight line passing through point E and parallel to the horizontal axis and an extension of straight line AC. The triangle defined by this point F and points B and C is the operating region expanded by the square difference calculation (or integral leading edge control) of this embodiment, and the resolution at the maximum amplitude is up to 10.5 bits. improves.

Furthermore, as shown in FIG. 15, if the difference between the output voltage of the integrator (7) and the offset level is extracted, the inverting amplifier (56) and the switch (
D/A conversion 9 of negative numbers can be performed without using 58N), and the circuit can be simplified.

Note that both of the two embodiments use square root and square calculations, but if the playback quality is compromised, the dynamic range may be further expanded by using square root and cube calculations. It is possible.

Effects of the Invention As described in detail above, according to the present invention, a wide dynamic range can be obtained by n-th power calculation, and since a single constant current source can be used, the configuration can be simplified, and complementary type M
It is easy to implement O3 integrated circuit. Furthermore, by controlling the leading edge of the integration period, resolution can be increased.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing an example of a conventional D/A converter,
2 and 3 are waveform diagrams for explaining the D/A converter in FIG. 1, FIGS. 4 and 5 are block diagrams for explaining the present invention, and FIGS. 6 and 7 are the same. The route map, Figure 8 is the same flow chart, and Figure 9 is the D/A according to the present invention.
Block diagrams illustrating embodiments of the converter, Figures 10 and 1
1 is a waveform diagram for explaining the embodiment of FIG. 9, FIG. 12 is a diagram for explaining the present invention in detail, FIG. 13 is a block diagram showing another embodiment of the present invention, and FIG. 14 is a diagram for explaining the embodiment of the present invention. and FIG. 15 is a waveform diagram for explaining the embodiment of FIG. 13. (3H) and (5311) are upper counters, (3L) and (53L) are lower counters, (5■), (5L)
and (55) is a constant current source, (7) is an integrator, (11) is a DSP, (14) is a host computer, (17) is a coefficient memory, (31) is a multiplier, and (32) is a logic operation unit. , (53) is a counter, and (54) is a drive circuit. JP-A Sho GO-142625 (10) <= B JP-A Sho GO-142G25 (13) Procedural amendment 1. Display of the case 1963 Patent Application No. 247807 2, Title of the invention Digital/analog converter 3, Person making the amendment Relationship to the case Patent applicant address Tokyo Parts 6-7-35 Name (21
8) Norio Ohga, representative director of Sony Corporation 5, date of amendment order 6, Showa month/day 6, number of inventions increased by amendment 7, subject of amendment Detailed explanation of the invention in the specification column 8
, Contents of the amendment (1) In the specification, on page 2, lines 6-16, ``However,
...is being done. ” will be deleted. (2) On the 17th line of the same page, after "...while", "It is composed of a double slope counter type D/A converter,
Add "Lowered processing speed". (3) Same, page 7, lines 10-12: [It was difficult. ...It was difficult. " was corrected to "It was necessary. And it was difficult to achieve such high precision with complementary MO8 integrated circuits." (4) In the same page, page 19, line 18, the statement "1 lower 12 bits" has been corrected to "lower 8 bits." (5) Similarly, in the second line from the bottom of page 20, the text "8-bit data" is corrected to "data up to the upper 8 bits."that's all

Claims (1)

[Claims] A digital/analog converter comprising a digital signal processing device that performs calculations on 1/n of input digital data, and digital/analog conversion means that converts the output digital data of the digital signal processing device into an analog signal corresponding to the nth power of the digital signal processing device. .