JPS60133592A - Composite memory refresh system - Google Patents

Abstract

PURPOSE:To simplify the refreshing of a memory to be accessed in common from plural processors by using respective outputs from a refresh requesting circuit and a refresh address circuit in each processor. CONSTITUTION:If a refresh request to a memory circuit 8 is generated in a processor 1a, the refresh request is transmitted from a refresh request circuit 3a to an OR circuit 10 and OR between the outputs from the circuit 3a and a refresh request circuit 3b is inputted to a memory access competition circuit 5. A refresh address to the circuit 8 is inputted from a refresh address circuit 4a to a register circuit 11 and an update address is applied from the circuit 11 to the circuit 8. If a memory refresh request is generated in a processor 1b, refresh is attained similarly.

Description

[Detailed description of the invention] r Chung・ (JHθ) at IE Act 4 ff1F'
1. The present invention relates to a complex memory refresh method in a switching system, and more specifically, to a seven-refresh method for selecting a plurality of processors each having memory refresh means to perform memory access.

[Background of the invention]

A switching system such as a Panat switching system has a plurality of processors. The present invention provides a memory circuit that is to be accessed in common from a plurality of processors having memory refresh means capable of sending a memory refresh address in accordance with a memory refresh island request and a refresh request. The present invention relates to a common memory refresh island system in an exchange system in which a processor selected from the processors accesses the memory circuit.

A conventional method when a plurality of processors access a common memory circuit is shown in FIG. 1 and will be described. In FIG. 1, 1a and jb are processors, 2a and 2b are provided in the processors 1a and 1b, and have memories provided corresponding to the number of processors, as well as access request circuits 5a and 6b for access to the main circuit. Similarly, processor 1
4a and 4b are refresh address circuits that are used to refresh the memory that corresponds to the processor; 5 is a refresh address circuit that is used for refreshing the memory that corresponds to the processor;
a memory access competition circuit that selects one access request from the access request circuits 2a, 2b and the refresh request generation circuit 6 provided in the above according to the priority order;
Reference numeral 6 denotes a refresh request generation circuit that is a trigger for performing refreshment to the memory circuit 8, and 7 a refresh address that indicates the address on the memory circuit 8 to be refreshed by counting based on the refresh request signal from the refresh request generation circuit 6. A counting circuit 8 is a memory circuit that is commonly accessed by the plurality of processors 1a and 1b, and 9 is a counting clock generation circuit for generating refresh requests at regular intervals.

In the above circuit configuration, a method for refreshing the memory circuit 8 will be described.

First, when a request to access the memory circuit 8 is generated within the processor 1a, a request signal is input from the access request circuit 2a to the memory access competition circuit 5. In the memory access contention circuit 5, the access request circuit 2 in the processor 1a
a, selects inputs from access request circuit 2b and refresh request generation circuit 6 in processor 1b according to priority order.

Here, when the access request from the access request circuit 2a is accepted, the access request is input to the memory circuit 8, which means that the memory access from the processor 1a is possible.

On the other hand, a memory refresh request to the memory circuit 8 is generated at regular intervals by counting a fixed number of clocks from the clock generating circuit 9 in the refresh request generating circuit 6. The refresh request generated in this manner is input to the memory circuit 8 via the memory access contention circuit 5 described above.

The refresh address counting circuit 7 is composed of counters that count the number of IT for each refresh request, and is input to the memory circuit 8 along with the refresh request input to the memory circuit 8 via the memory access contention circuit 5 described above.

In this way, the refresh request to the memory circuit 8 is executed as described above, but for this purpose, the refresh request generation circuit 6, the refresh address counting circuit 7, and the clock generation circuit 9 are required, and the hardware The amount of wear will also increase.

Furthermore, although the processors 1a and 1b have refresh request circuits 5a and 3b and refresh gourd address circuits 4a and 4b, respectively, they are not used effectively and are wasted.

[Purpose of the invention]

SUMMARY OF THE INVENTION An object of the present invention is to provide a composite memory refresh method that solves the problems in the prior art mentioned above and can easily refresh a memory circuit when a plurality of processors access a common memory circuit. It is in.

[Summary of the invention]

A feature of the present invention is that a refresh request circuit and a refresh circuit within the processor are used to simplify the refresh method. That is, a memory refresh address from a specific processor is used as a refresh address to the common memory, and continuous address refresh is possible even when other processors are accessing the common memory.

[Embodiment of the Invention] An embodiment of the present invention will be described below with reference to FIG. Second
In the figure, the same reference numerals as in FIG. 1 indicate the same things, but in FIG.
11 is a processor 1;
This is a register circuit that stores the refresh address output from the refresh address circuit 4a in the refresh address circuit 4a.

In FIG. 2, the following operation will be explained on the assumption that the processor 1a is selected as the sender of the refresh address.

That is, when a memory refresh request to the memory circuit 8 is generated within the processor 1a, the refresh request circuit 3a also inputs the input to the OR circuit 10. The OR circuit 10 performs a logical OR with the input signal from the refresh request circuit 3b, and inputs the logical sum result to the memory access contention circuit 5.

The refresh address to the memory circuit 8 is first inputted to the register circuit 11 from the refresh address circuit 4a in the selected processor 1a, using the generated refresh address.

In the register circuit 11, the refresher address circuit 4a
Stored every time the Karanori Flexi address is updated,
Input to memory circuit 8. When the output from the OR circuit 10 is input to the memory circuit 8 via the memory access contention circuit 5, the flexible device address becomes valid.

On the other hand, when a memory refresh request is issued to the memory circuit 8 within the processor 16, refreshing becomes possible as in the case described above.

Here, a request signal from the flexible device requesting circuit 3a in the processor 1a and a request signal from the flexible device requesting circuit 5b in the processor 1b are inputted to the OR circuit 10,
The logical sum result of these is stored in the memory access contention circuit 5 and 7.
The refresh request signal is input to the memory circuit 8 regardless of whether the refresh address generation circuit 3a in the processor 1a or the refresh share address generation circuit 5b in the processor 2a is selected as the refresh address sending source. This is to ensure continuity of Lexie addresses.

As described above, a simple refresher circuit can be realized by using the refresh request circuits 5a, 3b and the refresher address circuits 4a, 4b of the processors 1a, 1b.

Note that in order to maintain the effectiveness of the system, it is necessary to suppress the increase in the number of refresher executions due to an increase in the number of processors to within a certain number.

〔Effect of the invention〕

As is clear from the embodiments described above, according to the present invention, when a plurality of processors access a common memory circuit, it is possible to easily refresh the memory circuit with a simple hardware configuration. This has the advantage that the circuit and refresh address circuit can be used effectively.

[Brief explanation of the drawing]

FIG. 1 is a circuit block diagram for explaining a conventional composite memory refresher method, and FIG. 2 is a diagram showing an embodiment of the present invention, and is a circuit block diagram for explaining the composite memory refresher method. DESCRIPTION OF SYMBOLS 1... Processor, 2... Access request circuit, 3
. . . refresh request circuit, 4 . . . refresh limit 11th circuit, 5 . Memory circuit, 9... Clock generation circuit, 10... OR circuit, 11... Register circuit. Continued from page 1 [Inc.]・Inventor Book 1) Takashi @ Inventor Hiroyuki Ichikawa 3-9-11 Midoricho, Musashino-shi Nippon Telegraph and Telephone Corporation Musashino Telecommunications Research Institute 3-9-11 Midoricho, Musashino-shi Nippon Telegraph and Telephone Musashino Telecommunications Research Institute

Claims (1)

[Claims] Select from a plurality of processors that are to access a memory circuit that is a common access target from among a plurality of processors that have memory refresher means capable of sending a memory refresher address in accordance with a memory refresher request and a memory refresher request. In a composite memory refresh method in which a processor accesses the memory circuit, an arbitrary processor is selected from among the plurality of processors, and a refresh address sent from the processor is stored in a register circuit as needed;
7 retrieval from the processor that performs memory access &
A composite memory refresher method characterized in that a request is refreshed by a request and an address stored in the register circuit and a refresh address.