JPS60134320U - Amplifier circuit coupled to differential amplifier circuit - Google Patents
Amplifier circuit coupled to differential amplifier circuitInfo
- Publication number
- JPS60134320U JPS60134320U JP2086684U JP2086684U JPS60134320U JP S60134320 U JPS60134320 U JP S60134320U JP 2086684 U JP2086684 U JP 2086684U JP 2086684 U JP2086684 U JP 2086684U JP S60134320 U JPS60134320 U JP S60134320U
- Authority
- JP
- Japan
- Prior art keywords
- transistor
- amplifier circuit
- diode
- npn transistor
- differential amplifier
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Landscapes
- Amplifiers (AREA)
Abstract
(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.
Description
、第１図は本考案に係る差動増幅回路に結合された増幅
回路の一実施例を示す回路図であり、第２図はその出力
波形を示す図であり、第３図は本考案に係る差動増幅回
路に結合された増幅回路の他 １の実施例を示す回路図
である。
１：入力端子、２：出力端子、３：電源端子、４：接地
端子、５．６，７：電流ミラー回路、Ａ：差動増幅回路
、Ｂ：増幅回路。
第１２ ｖ、。
」
Ｄ ””
第２図
３ クレ■ヨエ
−ｖ ｊｔ２ 。
４, FIG. 1 is a circuit diagram showing an embodiment of an amplifier circuit coupled to a differential amplifier circuit according to the present invention, FIG. 2 is a diagram showing its output waveform, and FIG. FIG. 7 is a circuit diagram showing another embodiment of an amplifier circuit coupled to such a differential amplifier circuit. 1: input terminal, 2: output terminal, 3: power supply terminal, 4: ground terminal, 5.6, 7: current mirror circuit, A: differential amplifier circuit, B: amplifier circuit. 12th v. "D""Figure 2 3. 4
Claims (2)
トランジスタが相補的に接続された出力段とそのバイア
ス回路からなり、該差動増幅回路に結合された第１の電
流ミラー回路と、該第１の電流ミラー回路のバイアス側
のダイオ−、ド接続したトランジスタのカソードを抵抗
を介し前記出力段のＮＰＮトランジスタとＰＮＰ トラ
ンジスタの接続点に接続し、該第１の電流ミラー回路の
出力側のトランジスタのコレクタに、該ＮＰＮトランジ
スタのベースとダイオード接続されたＮＰＮトランジス
タのアノードが接続され、該ＮＰＮ トランジスタと該
ダイオード接続されたＮＰＮトランジスタが第２の電流
ミラー回路を形成し、該ダイオード接続されたＮＰＮト
ランジスタのカッτドにダイオード接続されたＰＮＰト
ランジスタのアノードが接続され、該ダイオード接続さ
れたＰＮＰ トランジスタと前記出力段のＰＮＰトラン
ジスタが第３の電流ミラー回路を形成し、該ダイオード
接続されたＰＮＰトランジスタが第１の電流源用トラン
ジスタを介し接地され、前記出力段のＮＰＮトランジス
タとＰＮＰトランジスタの接続点が第２の電流源用トラ
ンジスタを介し接地してなり、前記出力段のＮＰＮ ト
ランジスタとＰＮＰ ）ランジスタの接続点から出力を
得ることを特徴とする差動増幅回路に結合された増幅回
路。(1) Differential amplifier circuit, NPN transistor, and PNP
It consists of an output stage in which transistors are connected in a complementary manner and a bias circuit thereof, a first current mirror circuit coupled to the differential amplifier circuit, and a diode and a diode connection on the bias side of the first current mirror circuit. The cathode of the transistor is connected to the connection point between the NPN transistor and the PNP transistor in the output stage through a resistor, and the base of the NPN transistor is diode-connected to the collector of the transistor on the output side of the first current mirror circuit. The anode of the NPN transistor is connected, the NPN transistor and the diode-connected NPN transistor forming a second current mirror circuit, and the anode of the PNP transistor diode-connected to the cathode of the diode-connected NPN transistor. are connected, the diode-connected PNP transistor and the PNP transistor of the output stage form a third current mirror circuit, the diode-connected PNP transistor is grounded via the first current source transistor, and the A differential device characterized in that a connection point between an NPN transistor and a PNP transistor in an output stage is grounded via a second current source transistor, and an output is obtained from a connection point between an NPN transistor and a PNP transistor in the output stage. An amplifier circuit coupled to an amplifier circuit.
た第１項記載の差動増幅回路に結合された増幅回路。(2) An amplifier circuit coupled to the differential amplifier circuit according to item 1, wherein the differential amplifier circuit is formed of a double-balanced differential amplifier.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2086684U JPS60134320U (en) | 1984-02-16 | 1984-02-16 | Amplifier circuit coupled to differential amplifier circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2086684U JPS60134320U (en) | 1984-02-16 | 1984-02-16 | Amplifier circuit coupled to differential amplifier circuit |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS60134320U true JPS60134320U (en) | 1985-09-06 |
| JPH0540577Y2 JPH0540577Y2 (en) | 1993-10-14 |
Family
ID=30511749
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2086684U Granted JPS60134320U (en) | 1984-02-16 | 1984-02-16 | Amplifier circuit coupled to differential amplifier circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS60134320U (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH01221905A (en) * | 1988-01-13 | 1989-09-05 | Tektronix Inc | Wide band differential amplifier |
-
1984
- 1984-02-16 JP JP2086684U patent/JPS60134320U/en active Granted
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH01221905A (en) * | 1988-01-13 | 1989-09-05 | Tektronix Inc | Wide band differential amplifier |
Also Published As
| Publication number | Publication date |
|---|---|
| JPH0540577Y2 (en) | 1993-10-14 |
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