JPS60128489A - data conversion circuit - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION (a) Technical Field of the Invention The present invention provides a method for outputting data arranged in a matrix for each ζ bit column by column, with the row direction being the bit arrangement direction of a word. The present invention relates to a data conversion circuit that converts data arrays.

(b) Background of the technology For example, image data handled in an image processing system using a computer, etc. is an original image in which each pixel is arranged in a matrix, with black pixels being 1'' and white pixels being 0.
It is often represented by value data.1 Normally, such image data is read in the order obtained by rask scanning with the main scanning direction in the 9-line direction, and is stored in an image memory, etc., in units of words, just like general data. .

For example, suppose the size of a pixel is 0.1 mm square.

One scan, or one line, of an original image with a width of 25.6 mm is represented by 256 bits (32 bytes) of binary data, and if one byte is one word, it is represented by 32 words.

By storing the information in this form, it is possible to easily display it on a CR7 display device or record it on a laser printer.

However, some types of printers require multiple lines of bone image data to be input in parallel, and in such cases, they are stored in an array such as 1[1J(a)]. It is necessary to convert the data into an array like the one shown in the same figure (bl).

(,c) Prior art and problems In order to convert data stored in an array like ta+ in Figure 1 to an array like bl in the same figure, conventionally a microcomputer or the like is used. The conversion is performed using 1M data, and therefore, in the above example, there was a problem in that the conversion required a long time of about 1ms.

(d) Object of the Invention The object of the present invention is to perform data conversion that enables high-speed conversion of a data array arranged in a matrix for each bit, with the row direction being the bit arrangement direction of a word, and outputting the data column by column. It is in providing the circuit.

(e) Structure of the Invention The data conversion circuit according to the present invention includes a memory that stores a plurality of words of data, and reads the stored contents of the memory one word at a time in order and converts data at a specified bit position for each word. The data selector includes a data selector that selects and outputs data, bit position specifying means that specifies a bit position to be selected by the data selector, and a shift register that sequentially stores the output of the data selector.

(f>Examples of the Invention The gist of the present invention will be specifically explained below using examples.

Figure 2 is a block diagram showing the configuration of an embodiment of the present invention.
Memory that stores data in an array like al.

2 is a data selector that sequentially reads the stored contents of memory l one word at a time and selects and outputs the data at the specified bit position for each word; 3 is a data selector that specifies the bit position to be selected by the data selector 2 and the memory address. A control circuit that controls writing and reading of the shift resistor 4 and the output sofa 5, which will be described later.

4 is a shift register that sequentially stores the output of the data selector 2, and 5 is an output sofa.

That is, the data selector 2 reads the stored contents of the memory 1 one word at a time from address 00 to address O7 under the control of the control circuit 3, and reads one word for each word.
outputs the data of the bit position of po, P8 . PI6. P24. P32. P2O, Pd2
．． P56 is set, and the shift register 4 assembles these and sends them to the output sofa 5.

In the next read cycle, data selector 2 is memory]
The storage contents of PI, P9 . PL? , P25. P33
．． Pd2. Pd2. P57 is set and sent to the output cover sofa 5.

Similarly, data stored in the array shown in FIG. 1(a) can be converted into an array shown in fbl in FIG.

According to the above embodiment, by using general-purpose elements for the data selector 2, shift register 4, and output buffer 5, such as configuring the memory 1 using four 4×4 bit storage elements, as shown in FIG. Data stored in the array shown in (a) could be converted into the array shown in (b) in 50 μS.

(g) Detailed Description of the Invention According to the present invention, for example, a data array arranged bit by bit in a matrix with the row direction as the word bit arrangement direction is converted at high speed and output column by column. can do.

[Brief explanation of the drawing]

FIG. 1 is an explanatory diagram of data conversion according to the present invention, and FIG. 2 is a block diagram illustrating the configuration of an embodiment of the present invention. In the figure, 1 is a memory, 2 is a data selector, 3 is a control circuit, and 4 is a shift register.

Claims (1)

[Claims] a memory that stores a plurality of words of data; a data selector that sequentially reads the stored contents of the memory one word at a time and selects and outputs data at a designated bit position for each word; A data conversion circuit comprising: bit position specifying means for specifying an exponent bit position; and a shift register for sequentially storing outputs of the data selector.