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JPS60117748A - Manufacture of semiconductor device - Google Patents

Manufacture of semiconductor device

Info

Publication number
JPS60117748A
JPS60117748A JP58225657A JP22565783A JPS60117748A JP S60117748 A JPS60117748 A JP S60117748A JP 58225657 A JP58225657 A JP 58225657A JP 22565783 A JP22565783 A JP 22565783A JP S60117748 A JPS60117748 A JP S60117748A
Authority
JP
Japan
Prior art keywords
layer
groove
region
etching
forming
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP58225657A
Other languages
Japanese (ja)
Inventor
Kazuhiro Kanbara
一博 神原
Osamu Hataishi
畑石　治
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP58225657A priority Critical patent/JPS60117748A/en
Priority to KR1019840006940A priority patent/KR900001267B1/en
Priority to US06/675,613 priority patent/US4575925A/en
Priority to EP84308280A priority patent/EP0143662B1/en
Priority to DE8484308280T priority patent/DE3477447D1/en
Publication of JPS60117748A publication Critical patent/JPS60117748A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02612—Formation types
    • H01L21/02617—Deposition types
    • H01L21/02634—Homoepitaxy
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02436—Intermediate layers between substrates and deposited layers
    • H01L21/02439—Materials
    • H01L21/02488—Insulating materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02367—Substrates
    • H01L21/0237—Materials
    • H01L21/02373—Group 14 semiconducting materials
    • H01L21/02381—Silicon, silicon germanium, germanium
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02436—Intermediate layers between substrates and deposited layers
    • H01L21/02439—Materials
    • H01L21/02441—Group 14 semiconducting materials
    • H01L21/0245—Silicon, silicon germanium, germanium
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02436—Intermediate layers between substrates and deposited layers
    • H01L21/02494—Structure
    • H01L21/02496—Layer structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02436—Intermediate layers between substrates and deposited layers
    • H01L21/02494—Structure
    • H01L21/02496—Layer structure
    • H01L21/02505—Layer structure consisting of more than two layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02518—Deposited layers
    • H01L21/02521—Materials
    • H01L21/02524—Group 14 semiconducting materials
    • H01L21/02532—Silicon, silicon germanium, germanium
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Power Engineering (AREA)
  • Chemical & Material Sciences (AREA)
  • Materials Engineering (AREA)
  • Bipolar Transistors (AREA)
  • Element Separation (AREA)
  • Recrystallisation Techniques (AREA)

Abstract

PURPOSE:To enable contact with a buried diffused layer to be taken on an element surface by a method wherein a groove is formed in the side surface of an epitaxial grown layer on a single crystal layer of one conductivity type, its surface being then exposed; and a contact region is formed by burying a layer of one conductivity type in the groove. CONSTITUTION:The double-layer structure of an N<+> Si single crystal layer 15 and an Si epitaxial layer 16 is formed by being surrounded with an SiO2 film 12b in the element-forming region. Next, in order to form the groove taking contact with the layer 15, first a resist film is formed by coating over the entire surface and then patterned, thus forming an etching mask 17. After a contact groove 18 is formed by Si etching, the etching mask is removed, and this groove is formed vertically to the bottom of the layer 15. After formation of the groove, a phosphorus-doped poly Si layer 19 is grown. Successively, the poly Si layer on the SiO2 film is removed by polish-etching, and the base diffused region 20 and an emitter diffused region 21 are formed, resulting in the formation of a bi-polar transistor.

Description

【発明の詳細な説明】 ＋１１発明の技術分野 本発明はエネルギービームを用いるアニールにより、絶
縁層で囲まれた島形成領域の多結晶シリコン（ポリシリ
コン）を単結晶化する５０１　（ｓｉｌｉ−ｃｏｎ　Ｏ
ｎ　Ｉｎ５ｕｌａｔｏｒ）技術を用いた半導体装置、特
にバイポーラトランジスタの製造において、高濃度埋没
層に達するコレクタコンタクトを素子の表面から形成す
る方法に関する。Detailed Description of the Invention +11 Technical Field of the Invention The present invention is directed to monocrystallizing polycrystalline silicon (polysilicon) in an island forming region surrounded by an insulating layer by annealing using an energy beam.
The present invention relates to a method for forming a collector contact reaching a highly doped buried layer from the surface of a device in the manufacture of semiconductor devices, particularly bipolar transistors, using the In5ulator technology.

（２）技術の背景 底とまわりが絶縁物（二酸化シリコン、５ｉＯｚ　）で
分離されたシリコンを単結晶化して作られた島にトラン
ジスタの如き素子を形成する技術が開発されている。そ
れを第１図の断面図を参照して説明すると、シリコン基
板１上に０．５μｍの厚さに５ｉ０２膜を形成し、それ
を選択的にエツチングしてＳＩＯ＋の絶縁層２を作る（
第１図（８））。(2) Background of the technology A technology has been developed to form elements such as transistors on an island made by single crystallizing silicon whose bottom and periphery are separated by an insulating material (silicon dioxide, 5 iOz). To explain this with reference to the cross-sectional view of FIG. 1, a 5i02 film is formed to a thickness of 0.5 μm on a silicon substrate 1, and it is selectively etched to form an SIO+ insulating layer 2 (
Figure 1 (8)).

次に同図（ｂ）に示される如く全面に０．８〜１．０μ
ｍの膜厚にポリシリコンを成長してポリシリコン層３を
形成する。Next, as shown in the same figure (b), 0.8 to 1.0μ is applied to the entire surface.
A polysilicon layer 3 is formed by growing polysilicon to a thickness of m.

次いで同図（Ｃ１に示される如く絶縁層２の作られてい
ない部分にレーザビーム４を照射するレーザアニールに
よってその部分のポリシリコンを溶融すると、溶融部分
はシリコン基板の単結晶を種にして図に白地で示す如く
単結晶化し、単結晶層５が作られる。レーザビームを図
に見て右に移動し、同図ｆｄ＋に示される如（ポリシリ
コン層を単結晶層５に変える。Next, as shown in FIG. The polysilicon layer is converted into a single crystal layer 5 as shown by the white background in FIG.

次いで選択酸化法（ＬＯＣＯ５法）で絶縁層２のまわり
を酸化して５ｉＯｚ層６を形成すると、Ｓ＋０２で底と
まわりが分離された単結晶の島５ａが作られ、この島５
ａにトランジスタ等を形成すると特性に優れたものが得
られる。Next, when the area around the insulating layer 2 is oxidized using a selective oxidation method (LOCO5 method) to form a 5iOz layer 6, a single-crystal island 5a whose bottom and surroundings are separated by S+02 is created, and this island 5
If a transistor or the like is formed in a, a device with excellent characteristics can be obtained.

（３）発明の目的 本発明の目的は上記ＳＯＩ技術を用いて半導体素子、例
えばバイポーラトランジスタを形成するにおいて、埋没
拡散層（Ｎ＋ｂ　１ｉｔ）とのコンタクトを素子表面で
とることができる半導体装置の製造方法の提供を目的と
するものである。(3) Purpose of the Invention The purpose of the present invention is to manufacture a semiconductor device that can make contact with the buried diffusion layer (N+b 1it) at the surface of the device when forming a semiconductor device, such as a bipolar transistor, using the above-mentioned SOI technology. The purpose is to provide a method.

（４）発明の構成 そしてこの目的は本発明によれば、絶縁物上に多結晶シ
リコン層を設ける工程、この多結晶シリコン層の素子形
成領域以外の部分を選択酸化する工程、次いで素子形成
領域の多結晶シリコンを一導電型の不純物を含むガラス
膜をカバー膜としてエネルギービームを用いたアニール
により前記導電型単結晶層とする工程、全面にエピタキ
シャル層を成長し、素子形成領域以外のエピタキシャル
層を選択酸化する工程、素子形成領域の端部にエツチン
グにより前記絶縁物に達する溝を形成し当該溝をｎ型に
ドープした多結晶シリコンで埋める工程を含むことを特
徴とする半導体装置の製造方法を提供することによって
達成される。(4) Structure and object of the invention According to the present invention, a step of providing a polycrystalline silicon layer on an insulator, a step of selectively oxidizing a portion of this polycrystalline silicon layer other than an element formation region, and then a step of selectively oxidizing a portion of the polycrystalline silicon layer other than an element formation region. The process of converting the polycrystalline silicon into the conductivity type single crystal layer by annealing using an energy beam using a glass film containing impurities of one conductivity type as a cover film, growing an epitaxial layer on the entire surface, and forming an epitaxial layer in areas other than the element formation area. A method for manufacturing a semiconductor device, comprising the steps of: selectively oxidizing the silicon; forming a groove reaching the insulator by etching at the end of the element forming region; and filling the groove with n-type doped polycrystalline silicon. This is achieved by providing

（５）発明の実施例 以下本発明実施例を図面によって詳述する。(5) Examples of the invention Embodiments of the present invention will be described in detail below with reference to the drawings.

一般にバイポーラトランジスタにおけるコレクタコンタ
クトは、エミッタおよびベース拡散領域を形成するエピ
タキシャル層が薄い場合はエミッタ拡散によってコレク
タコンタクト拡散を兼ねることができるので、コレクタ
コンタクトを深く形成する必要はなかった。本発明は、
ｎ＋型埋没層（ｎ”　ｂ層）に達する深いコレクタコン
タクトをいかに形成するかにかかわる。In general, when the epitaxial layer forming the emitter and base diffusion regions is thin, the collector contact in a bipolar transistor can double as the collector contact diffusion by emitter diffusion, so there is no need to form the collector contact deeply. The present invention
It concerns how to form a deep collector contact that reaches the n+ type buried layer (n''b layer).

本実施例はバイポーラ１ヘランジスタを例に、埋没層か
らコレクタコンタクトをとる方法を開示するもので、そ
の工程を第２図に示す半導体装置開部の断面図を参照し
て説明する。This embodiment uses a bipolar 1-helangistor as an example to disclose a method of making a collector contact from a buried layer.The process will be explained with reference to a cross-sectional view of an opening of a semiconductor device shown in FIG.

先ず、第２図（ａｌに示す如く、二酸化シリコン（Ｓ＋
０２）膜１２の全面に多結晶シリコン（ポリシリコン）
膜１３を例えば化学気相成長（ＣＶＤ　）法によって成
長する。その膜厚は形成されるべき　Ｎ＋ｂ層の深さに
対応して設定する。First, as shown in Figure 2 (al), silicon dioxide (S+
02) Polycrystalline silicon (polysilicon) on the entire surface of the film 12
The film 13 is grown by, for example, chemical vapor deposition (CVD). The film thickness is set corresponding to the depth of the N+b layer to be formed.

次いで全面に窒化膜（ＳｉＪＮ４１！ｉりを被着し、そ
れを素子形成領域をマスクする如くにパターニングして
窒化膜１９を作り、次いで熱酸化法によりポリシリコン
膜１３を選択酸化する。かかる選択酸化により窒化膜１
９がない部分のポリシリコンは酸化されて５ｉ０２とな
るが、窒化膜１９の下のポリシリコンは酸化されずその
まま残る。Next, a nitride film (SiJN41!i) is deposited on the entire surface and patterned to mask the element formation region to form a nitride film 19. Next, the polysilicon film 13 is selectively oxidized by a thermal oxidation method. Nitride film 1 due to oxidation
The polysilicon in the area without 9 is oxidized to 5i02, but the polysilicon under the nitride film 19 is not oxidized and remains as it is.

次に第２図（ｂ）に示す如く、上記窒化膜１９を除去し
た後アンチモン・シリケート・ガラス（ＳｂＳＧ）のカ
バー膜１４を塗布し、しかる後レーザアニールにより酸
化されずに残ったポリシリコン１３ａを単結晶化すると
同時にｎ＋型にドープしてｎ＋単結晶層１５を形成する
。Next, as shown in FIG. 2(b), after removing the nitride film 19, a cover film 14 of antimony silicate glass (SbSG) is applied, and then the remaining polysilicon 13a without being oxidized is subjected to laser annealing. is made into a single crystal, and at the same time it is doped to an n+ type to form an n+ single crystal layer 15.

次いで５ｂＳＧカバー膜１４を除去し全面にシリコンエ
ピタキシャル層を成長した後、前記選択酸化と同様に素
子形成領域に窒化膜をパターニングして熱酸化する。か
くして第２図（Ｃ）に示す如く素子形成領域にはｎ＋単
結晶層１５とエピタキシャル層１６との２層構造がＳｉ
Ｏ２膜１２ｂに囲まれて形成される。Next, after removing the 5bSG cover film 14 and growing a silicon epitaxial layer on the entire surface, a nitride film is patterned and thermally oxidized in the element formation region in the same manner as the selective oxidation. Thus, as shown in FIG. 2(C), a two-layer structure of the n+ single crystal layer 15 and the epitaxial layer 16 is formed in the element formation region.
It is formed surrounded by an O2 film 12b.

次にｎ＋単結晶層１５とのコンタク１−をとる溝を形成
するため、先ず全面にレジスト膜を塗布形成し、それを
同図ｔｅｌに示す如くパターニングしてエツチングマス
ク１７を形成する。当該エツチングマスク１７の大きさ
はエピタキシャル層１６より小さくし、このマスク１７
の周囲にはみ出したエピタキシャル層１６の部分が溝形
成領域となるよう設定する。Next, in order to form a groove that makes contact 1- with the n+ single crystal layer 15, a resist film is first applied to the entire surface and patterned as shown in the figure tel to form an etching mask 17. The size of the etching mask 17 is made smaller than the epitaxial layer 16.
The portion of the epitaxial layer 16 protruding from the periphery is set to become a groove forming region.

第２図１ｄｌはシリコンエツチングによりコンタクト溝
１８を形成した後エツチングマスク１７を除去した状態
を示し、溝１８はｎ＋型単結晶層１５底部まで垂直に形
成される。なおシリコンエツチングにおいてはＳｉ０２
層１２ｂがストッパーとなるため、単結晶層がエツチン
グされてＳｉＯ２層が露出したところでエツチングが止
る。また、横方向にもＳｉＯ２層で囲まれているのでサ
イドエツチングはほとんど進行することなく、溝形成の
ためのエツチングはきわめて容易になされ、僅かのオー
バーエツチングがあったとしてもそれが致命的なダメー
ジを与えることはない。FIG. 2Dl shows a state in which the etching mask 17 is removed after a contact groove 18 is formed by silicon etching, and the groove 18 is formed vertically to the bottom of the n+ type single crystal layer 15. In addition, in silicon etching, Si02
Since layer 12b acts as a stopper, etching stops when the single crystal layer is etched and the SiO2 layer is exposed. In addition, since it is surrounded by the SiO2 layer in the lateral direction, side etching hardly progresses, and etching for forming grooves is extremely easy, and even if there is a slight overetching, it will cause fatal damage. will not be given.

上記溝１８を形成した後は低温（最高８００℃）　ＣＶ
Ｄ法により燐ドープのポリシリコン層１９を成長する（
同図（ｅ））。このとき溝１８は上記ポリシリコン層１
９によって埋められる。After forming the groove 18, the temperature is low (maximum 800°C) CV
A phosphorus-doped polysilicon layer 19 is grown by method D (
Figure (e)). At this time, the groove 18 is formed in the polysilicon layer 1.
Filled in by 9.

続いてポリッシュによるエツチングでＳＳ１０２１Ｆ’
１２ｂ上のポリシリコシ層１９を除去し、通常の技術に
よってベース拡散領域２０およびエミッタ拡散領域２１
を形成しバイポーラトランジスタを形成する（同図（ｆ
））。か（して溝１８のポリシリコン層１９ａにより素
子表面からコレクタコンタクトをとることができる。Next, SS1021F' was etched with polish.
The polysilicon layer 19 on 12b is removed and the base diffusion region 20 and emitter diffusion region 21 are formed using conventional techniques.
is formed to form a bipolar transistor (see (f) in the same figure).
)). (Thus, the polysilicon layer 19a in the groove 18 allows a collector contact to be made from the element surface.

上述した本発明の方法の特徴は、第１にＳＯＩ技術を用
いた素子形成方法であって、素子形成領域がシリコンエ
ツチングのストッパーとなるＳｉＯ２膜に囲まれている
ためエツチングの終・点制御が容易であること、第２は
ポリシリコン層１９の成長およびポリッシュが低温処理
（ポリッシュは室温程度で行う）であるため、深いコレ
クタコンタクトの形成において高温状態がなく、従来高
温で起り易いｎ＋単結晶層１５のエピタキシャル層１６
へのはい上がりが少なくなり、その結果エピタキシャル
層重６を薄くすることができ、従ってベースが浅くなり
素子の動作速度を速くすることができる。なお、エピタ
キシャル層Ｉ６を薄く形成するために、溝１８の深さは
その分だけ小になり、そのことはポリシリコン層の成長
が容易になされる結果となる。The characteristics of the method of the present invention described above are as follows: Firstly, it is an element forming method using SOI technology, and since the element forming region is surrounded by a SiO2 film that acts as a stopper for silicon etching, it is possible to control the end point of etching. The second reason is that the growth and polishing of the polysilicon layer 19 is performed at a low temperature (polishing is performed at about room temperature), so there is no high temperature condition during the formation of a deep collector contact, which conventionally tends to occur at high temperatures. Epitaxial layer 16 of layer 15
As a result, the epitaxial layer weight 6 can be made thinner, so that the base becomes shallower and the operating speed of the device can be increased. Note that in order to form the epitaxial layer I6 thinly, the depth of the groove 18 is reduced accordingly, which results in easier growth of the polysilicon layer.

また第３の特徴として、従来あったコレクタコンタクト
用のｎ＋拡散層の形成が不必要となるため製造工程が短
縮できる利点がある。A third feature is that the manufacturing process can be shortened because the formation of an n+ diffusion layer for a collector contact, which was conventionally required, is no longer necessary.

（６）発明の効果 以上詳細に説明した如く本発明によれば、ＳＯＩ技術を
使ってｎ＋単結晶層を埋没層とする半導体素子の形成に
おいて、上記埋没層とのコンタクトを素子表面でとるこ
とができるため、例えばバイポーラトランジスタにおい
てコレクタコンタクトをとることが容易となり、またか
かる素子におい　（Ｑ］て動作速度の向上、製造工程数
の短縮が達成されるため、半導体装置の製造歩留りと製
品の信頼性第１図は従来技術によるＳＯＩの単結晶化の
工程を示す断面図、第２図は本発明の方法を実施するポ
リ・２シュ層、１４−アンチモンシリケートガラス膜、
１５−ｎ＋単結晶層、１６−・エピタキシャルＭ、１７
−エツチングマスク、　（ｄ゛１８、−溝、１９．　１
９ａ−・−鱗ドープポリシリコン層、２０−ベース拡散
領域、２１−エミッタ拡散領域第１図 手給補正書（自発） 昭和　年　月　１１ ５９．１１．１　’、） １・Ｉ＋　ｌ′ｌの表示 昭和布と年↑、胃Ｔ願第２２女乙≦−７号２発明の名称
　半導体装置の製造方法 ３、　ｔｉｌｌ止を′４る古 ’Ｂｆ’ｌとの関係　↑寵′「出願人 住所　神仝用県用崎市中原区ＩＩ［・（１１中１０１５
番地（５２２）名称富士通株式会社 ４　代　理　人　住所　神奈川県用崎市中原区ＩＩ］・
］１１中１０１５番地富士通株式会社内 （１）　本願明細書の特許請求の範囲を次のとおり補正
する。(6) Effects of the Invention As explained in detail above, according to the present invention, in forming a semiconductor device using an n+ single crystal layer as a buried layer using SOI technology, contact with the buried layer can be made at the surface of the device. This makes it easy to make collector contact in bipolar transistors, for example, and improves the operating speed and shortens the number of manufacturing steps in such devices, improving the manufacturing yield of semiconductor devices and product reliability. Fig. 1 is a cross-sectional view showing the SOI single crystallization process according to the prior art, and Fig. 2 shows a polysilicon layer, a 14-antimony silicate glass film, and a 14-antimony silicate glass film for implementing the method of the present invention.
15-n+ single crystal layer, 16-・epitaxial M, 17
-Etching mask, (d゛18, -groove, 19.1
9a--Scale doped polysilicon layer, 20-Base diffusion region, 21-Emitter diffusion region Figure 1 Hand-supplied correction form (self-initiated) Showa month 11 59.11.1',) 1・I+ l'l Showa Cloth and year ↑, Stomach T Application No. 22 ≦ -7 No. 2 Name of the invention Method of manufacturing semiconductor devices 3, Relationship with old 'Bf'l that stops '4' ↑ 'Applicant's address Nakahara-ku II, Yozaki City, Kaminoyo Prefecture [・(1015 out of 11)
Address (522) Name Fujitsu Limited 4 Agent Address II Nakahara Ward, Yozaki City, Kanagawa Prefecture]
] 11-1015 Fujitsu Limited (1) The scope of claims in the specification of the present application is amended as follows.

ト　域を形成　る工程とを含むことを特徴とする半導体
装置の製造方法。」A method for manufacturing a semiconductor device, comprising the step of forming a region. ”

Claims (1)

【特許請求の範囲】[Claims] 絶縁物上に多結晶シリコン層を設ける工程、この多結晶
シリコン層の素子形成領域以外の部分を選択酸化する工
程、次いで素子形成領域の多結晶シリコンを一導電型の
不純物を含むガラス膜をカバー膜としてエネルギービー
ムを用いたアニールにより前記導電型単結晶層とする工
程、全面にエピタキシャル層を成長し、素子形成領域以
外のエピタキシャル層を選択酸化する工程、素子形成領
域の端部にエツチングにより前記絶縁物に達する溝を形
成し当該溝をｎ型にドープした多結晶シリコンで埋める
工程を含むことを特徴とする半導体装置の製造方法。A step of providing a polycrystalline silicon layer on the insulator, a step of selectively oxidizing the portions of this polycrystalline silicon layer other than the device formation region, and then a glass film containing impurities of one conductivity type covers the polycrystalline silicon in the device formation region. A step of forming the conductive single crystal layer by annealing using an energy beam as a film, a step of growing an epitaxial layer on the entire surface and selectively oxidizing the epitaxial layer other than the element forming region, and etching the above-mentioned layer at the end of the element forming region. 1. A method of manufacturing a semiconductor device, comprising the steps of forming a trench that reaches an insulator and filling the trench with n-type doped polycrystalline silicon.
JP58225657A 1983-11-30 1983-11-30 Manufacture of semiconductor device Pending JPS60117748A (en)

Priority Applications (5)

Application Number Priority Date Filing Date Title
JP58225657A JPS60117748A (en) 1983-11-30 1983-11-30 Manufacture of semiconductor device
KR1019840006940A KR900001267B1 (en) 1983-11-30 1984-11-06 Manufacture of semiconductor device
US06/675,613 US4575925A (en) 1983-11-30 1984-11-28 Method for fabricating a SOI type semiconductor device
EP84308280A EP0143662B1 (en) 1983-11-30 1984-11-29 Soi type semiconductor device
DE8484308280T DE3477447D1 (en) 1983-11-30 1984-11-29 Soi type semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP58225657A JPS60117748A (en) 1983-11-30 1983-11-30 Manufacture of semiconductor device

Publications (1)

Publication Number Publication Date
JPS60117748A true JPS60117748A (en) 1985-06-25

Family

ID=16832725

Family Applications (1)

Application Number Title Priority Date Filing Date
JP58225657A Pending JPS60117748A (en) 1983-11-30 1983-11-30 Manufacture of semiconductor device

Country Status (1)

Country Link
JP (1) JPS60117748A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0897225A (en) * 1994-09-22 1996-04-12 Nec Corp Semiconductor device and its manufacture
US9629467B2 (en) 2008-07-25 2017-04-25 Herman Miller, Inc. Method for manufacturing a multi-layered support structure

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0897225A (en) * 1994-09-22 1996-04-12 Nec Corp Semiconductor device and its manufacture
US9629467B2 (en) 2008-07-25 2017-04-25 Herman Miller, Inc. Method for manufacturing a multi-layered support structure

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