JPS60115248A - Hermetic sealed semiconductor device and preparation thereof - Google Patents
Hermetic sealed semiconductor device and preparation thereofInfo
- Publication number
- JPS60115248A JPS60115248A JP19790783A JP19790783A JPS60115248A JP S60115248 A JPS60115248 A JP S60115248A JP 19790783 A JP19790783 A JP 19790783A JP 19790783 A JP19790783 A JP 19790783A JP S60115248 A JPS60115248 A JP S60115248A
- Authority
- JP
- Japan
- Prior art keywords
- lead
- resin
- semiconductor element
- tab
- semiconductor device
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 55
- 229920005989 resin Polymers 0.000 claims abstract description 31
- 239000011347 resin Substances 0.000 claims abstract description 31
- 238000003780 insertion Methods 0.000 claims abstract description 6
- 230000037431 insertion Effects 0.000 claims abstract description 6
- 238000000034 method Methods 0.000 claims description 17
- 238000003860 storage Methods 0.000 claims description 7
- 238000004519 manufacturing process Methods 0.000 claims description 6
- 239000000126 substance Substances 0.000 claims description 2
- 238000007789 sealing Methods 0.000 abstract description 14
- 239000011521 glass Substances 0.000 abstract description 13
- 229910052751 metal Inorganic materials 0.000 abstract description 7
- 239000002184 metal Substances 0.000 abstract description 7
- 238000010438 heat treatment Methods 0.000 abstract 1
- 239000010408 film Substances 0.000 description 9
- 239000000919 ceramic Substances 0.000 description 8
- 239000000758 substrate Substances 0.000 description 6
- 239000003822 epoxy resin Substances 0.000 description 4
- 239000000463 material Substances 0.000 description 4
- 229920000647 polyepoxide Polymers 0.000 description 4
- 239000003795 chemical substances by application Substances 0.000 description 3
- 238000000465 moulding Methods 0.000 description 3
- 229910052782 aluminium Inorganic materials 0.000 description 2
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 2
- 238000005538 encapsulation Methods 0.000 description 2
- 238000001721 transfer moulding Methods 0.000 description 2
- 230000002747 voluntary effect Effects 0.000 description 2
- PNEYBMLMFCGWSK-UHFFFAOYSA-N Alumina Chemical compound [O-2].[O-2].[O-2].[Al+3].[Al+3] PNEYBMLMFCGWSK-UHFFFAOYSA-N 0.000 description 1
- 239000004593 Epoxy Substances 0.000 description 1
- 229910001111 Fine metal Inorganic materials 0.000 description 1
- 238000012769 bulk production Methods 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 230000000593 degrading effect Effects 0.000 description 1
- 238000011161 development Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 1
- 238000002347 injection Methods 0.000 description 1
- 239000007924 injection Substances 0.000 description 1
- 230000001678 irradiating effect Effects 0.000 description 1
- 150000002739 metals Chemical class 0.000 description 1
- 239000004033 plastic Substances 0.000 description 1
- 238000012545 processing Methods 0.000 description 1
- 239000002994 raw material Substances 0.000 description 1
- 238000005488 sandblasting Methods 0.000 description 1
- 239000003566 sealing material Substances 0.000 description 1
- 229910000679 solder Inorganic materials 0.000 description 1
- 238000005476 soldering Methods 0.000 description 1
- 230000008961 swelling Effects 0.000 description 1
- 239000010409 thin film Substances 0.000 description 1
- 238000003466 welding Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/93—Batch processes
- H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
- H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Lead Frames For Integrated Circuits (AREA)
Abstract
Description
【発明の詳細な説明】
この発明は気密封止型半導体装置及びその製造方法に関
するものである。すなわち半導体素子収納容器に素子挿
入用の開口部を配設する様に１ノードフレームを樹脂封
止し、次に挿入用開口部の底面のリード先端部とタブ部
の樹脂皮膜を除去した後で半導体素子をタブ部に装着し
、次にリード先端部と半導体素子を結線した後に開口部
をふたで密封する事を特徴とする気密封止型半導体装置
及びその製造方法である。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a hermetically sealed semiconductor device and a method for manufacturing the same. In other words, after sealing the 1-node frame with resin so as to provide an opening for device insertion in a semiconductor device storage container, and then removing the resin film on the lead tips and tabs on the bottom of the insertion opening. This hermetically sealed semiconductor device and its manufacturing method are characterized in that a semiconductor element is mounted on a tab part, and then the lead tip and the semiconductor element are connected, and then the opening is sealed with a lid.
従来の半導体対正方法はセラミック形、サーディツプ形
（ガラス封止形）、及び樹脂封止形の製法が採用されて
いる。セラミック形とサーディツプ形製品は気密封止形
で、構造上から高信頼性機械の部品用に最適であシ、一
方の樹月旨封止形の製品は現在半導体封止法の主流とな
シ、民生用機械用に量産されている。Conventional semiconductor manufacturing methods include ceramic type, cerdip type (glass sealed type), and resin sealed type. Ceramic type and cerdip type products are hermetically sealed and are ideal for use as parts of highly reliable machines due to their structure, while cylindrical type products are currently the mainstream semiconductor encapsulation method. , are mass-produced for consumer machinery.
最近この樹脂封止形のものを高信頼度化して、気密封止
形の製品に近い封止技術を確保するための技術開発が進
められている。樹脂封止方法はモールド法と注入法の２
方法がある。その中で金属どに優れたエポキシ樹脂のト
ランスファーモールド法による樹脂封止が主流である。Recently, technological development has been underway to improve the reliability of resin-sealed products and to secure a sealing technology similar to that of hermetically sealed products. There are two resin sealing methods: molding and injection.
There is a way. Among these, the mainstream is resin sealing using a transfer molding method using epoxy resin, which has excellent properties against metals.
従来のモールド法による封止体を第１図にて説明する。A sealed body formed by a conventional molding method will be explained with reference to FIG.
封止体ＩＫ−２いて、リード先端２とタブ４上の半導体
素子５とを金線やアルミ線の金属細線６でボンディング
したリードフレーム８を上型７と下型８との間にはさみ
、エポキシ系の封止樹脂をゲートからキャビティ−９内
部に圧入して樹脂封止する。１０はパリ溜め、１１はリ
ード間隙である。In the sealing body IK-2, a lead frame 8 in which the lead tip 2 and the semiconductor element 5 on the tab 4 are bonded with a thin metal wire 6 such as a gold wire or an aluminum wire is sandwiched between an upper mold 7 and a lower mold 8. An epoxy-based sealing resin is press-fitted into the cavity 9 from the gate to perform resin sealing. 10 is a Paris reservoir, and 11 is a lead gap.
この封止方法においての難点はリードフレームの厚味の
バラツキ、金型加工の精度および使用にともなう損傷、
型締付圧の不均等などによって金型とリードフレーム間
の間隙から樹脂パリが発生する０このリード上のノ（り
はリート°とソケットの接触不良や半田づけの作業の妨
害となるため、）くるため、半導体機能の信頼性に影響
を受けるとい゛った欠点がある。またボンディングワイ
ヤの流れが生じて短絡不良が生じる欠点があった。The disadvantages of this sealing method are variations in the thickness of the lead frame, the precision of mold processing, and damage caused by use.
Resin flakes occur from the gap between the mold and the lead frame due to uneven mold clamping pressure, etc. This crease on the lead causes poor contact between the lead and the socket and interferes with the soldering work. ), which has the drawback of affecting the reliability of semiconductor functions. Furthermore, there is a drawback that the bonding wire flows and short circuits occur.
一方では集積回路（ＩＣやＬＳＩ）はセラミック製収納
容器内の半導体素子とリードとを結線した後でガラス封
止し、次にリードフレーム枠の部分を切断除去する形式
の半導体封止を採用している。詳細には、通常純度９０
チ前後の一般アルミナセラミックの絶縁基板容器の中央
凹部に半導体素子を固着すると共に、この半導体素子を
囲むように配置したリードフレームのリード部は、絶縁
基板の周辺部で固着されている０半導体素子とリード先
端とを金属細線で配線した後、前記半導体素子を覆うよ
うに封止ふたをかぶせ、封入ガラスを介して前記絶縁基
板周辺部とふた周辺の下面とを密封して製作する。この
従来例を第９図にて説明する。On the other hand, integrated circuits (ICs and LSIs) use a semiconductor encapsulation method in which the semiconductor element and leads are connected in a ceramic storage container and then sealed with glass, and then the lead frame frame is cut and removed. ing. In detail, the purity is usually 90
A semiconductor element is fixed to the central recess of the general alumina ceramic insulating substrate container before and after the chip, and the lead part of the lead frame arranged to surround this semiconductor element is connected to the semiconductor element fixed at the periphery of the insulating substrate. After wiring the semiconductor device and the lead tips with thin metal wires, a sealing lid is placed to cover the semiconductor element, and the periphery of the insulating substrate and the lower surface of the periphery of the lid are sealed via an encapsulating glass. This conventional example will be explained with reference to FIG.
セラミック製絶縁基板１２の容器中央部の凹部に半導体
素子１８を固着し、この半導体素子１８はリード先端１
４にかこまれて配置されている。A semiconductor element 18 is fixed to a recess in the center of the container of the ceramic insulating substrate 12, and this semiconductor element 18 is attached to the lead tip 1.
It is placed surrounded by 4.
リード先端１４と半導体素子１８とは金属細線１５で結
線されている。また上部はガラス窓１６、透明膜１７を
有する絶縁ふた１８でおおい、封入絶縁ガラス１９を介
して前記絶縁基板１２の周辺と絶縁ふた１８周辺の下面
とを気密封着して、気密封止型セラミック形の半導体装
置２０ｔ−製作する。この従来例の半導体は特に紫外線
消去型ＥＰＲＯＭのパッケージ封止構造であｊ、 １．
クツケージの半導体素子上部に情報消去用の紫外線を照
射するためのガラス窓１６を設けている０この従来構造
は絶縁容器にセラミック容器を利用し、リードフレーム
を埋設するときに低触点のガラス層を用いるが、この工
程で不良が発生して歩溜を低下させていた。またセラミ
ックス容器はエポキシ製樹脂容器に比較して原材料費が
高価でおるという欠点がある。The lead tip 14 and the semiconductor element 18 are connected by a thin metal wire 15. Further, the upper part is covered with an insulating lid 18 having a glass window 16 and a transparent film 17, and the periphery of the insulating substrate 12 and the lower surface of the periphery of the insulating lid 18 are hermetically sealed via the enclosed insulating glass 19. A ceramic type semiconductor device 20t is manufactured. This conventional semiconductor has a package sealing structure particularly for an ultraviolet erasable EPROM.1.
A glass window 16 is provided above the semiconductor element of the shoe cage for irradiating ultraviolet rays for erasing information.This conventional structure uses a ceramic container as an insulating container, and when embedding the lead frame, a glass window 16 with a low contact point is used. However, defects occurred during this process, reducing the yield. Additionally, ceramic containers have the disadvantage that raw materials are more expensive than epoxy resin containers.
本発明は前記の従来例の欠点を改善できる半導体封止方
法であり、量産的でかっ歩溜シが向上し改良して、樹脂
容器にて気密封止している。すなわち容器内のタブ上に
半導体素子を装着後にリード先端部とこの素子の電極と
を金属細線で結線する。なをリード先端部にパリ（樹脂
皮膜）が発生しても機械的にパリを除去し、あるいは化
学的に樹脂剥離剤や樹脂膨潤剤を用いてパリを除去する
事で結線が確実にでき、次にこの半導体収納容器をガラ
ス材や透明エポキシ樹脂材の封入ふたで気密封止する半
導体装置及びその製造方法である。The present invention is a semiconductor sealing method that can improve the drawbacks of the conventional example described above, and improves the bulk production capacity for mass production, and hermetically seals the semiconductor with a resin container. That is, after the semiconductor element is mounted on the tab in the container, the lead tip and the electrode of this element are connected with a thin metal wire. Even if paris (resin film) occurs at the tip of the lead, the wiring can be ensured by removing the paris mechanically or chemically using a resin stripping agent or resin swelling agent. Next, there is provided a semiconductor device and a method for manufacturing the same, in which the semiconductor storage container is hermetically sealed with an enclosing lid made of a glass material or a transparent epoxy resin material.
本発明を説明するために、以下図面にもとづいて実施例
を説明する。In order to explain the present invention, embodiments will be described below based on the drawings.
実施例１
第８図はトランスファ成形機金型の上型２１とと下型２
２、リードフレームｇ８とキャビティ２４を図示した図
面である。この金型のランナー２５とゲート２６からキ
ャビティ−２４内部に樹脂を充填し、これを加熱硬化さ
せて成形体２７をつくる。この時リードフレーム２８の
リード先端２８は金型の上型２１に圧接するために樹脂
中に埋設されてしまう事はない。但し圧接の状況によっ
てはエポキシ樹脂の薄い皮膜が形成される事が９除去工
程に入る。パリ除去工程はサンドブラストマシンを使用
して除去する。成形体２７の開口窓の凹部にプラストマ
シンのノズル口を順次あてて樹脂皮膜を除去し、次にリ
ード先端２８を洗浄したあとに乾燥する。この乾燥した
成形体２７のタブ２９上に半導体素子８０を装置し、こ
れをワイヤーポンディングマシンにてリード先端２８と
半導体素子８０とを結線する。この後に成形体２７の半
導体素子８０の上部に樹脂やガラス窓材のふた８２を利
用して気密封入し、ＩＣ半導体成形品を得る。Example 1 Figure 8 shows the upper mold 21 and lower mold 2 of a transfer molding machine mold.
2. It is a drawing illustrating a lead frame g8 and a cavity 24. A resin is filled into the cavity 24 through the runner 25 and gate 26 of this mold, and is heated and hardened to form a molded body 27. At this time, the lead tips 28 of the lead frame 28 are pressed against the upper mold 21 of the mold, so that they are not buried in the resin. However, depending on the conditions of pressure welding, a thin film of epoxy resin may be formed during the removal step (9). The paris removal process uses a sandblasting machine. The resin film is removed by sequentially applying the nozzle port of the plastic machine to the concave portion of the opening window of the molded body 27, and then the lead tip 28 is washed and then dried. A semiconductor element 80 is mounted on the tab 29 of this dried molded body 27, and the lead tip 28 and the semiconductor element 80 are connected using a wire bonding machine. Thereafter, the semiconductor element 80 of the molded body 27 is hermetically sealed using a lid 82 made of resin or glass window material to obtain an IC semiconductor molded product.
実施例９
実施例１にもとづいて成形体ｇｑを得る。この成形体２
７の開口部凹部のリード先端２８の樹脂皮膜を除去する
工程から説明する。成形体２７の開口窓から樹脂剥離剤
（商品名ゲルダツクスーＰ）を注入してリード先端２８
の樹脂皮膜を剥離する。次にリード先端２８を′軽くプ
ラッシイングする事で確実に皮膜を除去し、これを洗浄
した後で乾燥させる。この樹脂皮膜を除去した成形体２
７のタブ２９に半導体素子８０を装着し、次にワイヤボ
ンディングマシンでリード先端２８と半導体素子８０と
を金属細線８１で結線する。この後に成形体２７の開口
窓を実施例１と同様に透明樹脂板又はガラス板材のふた
８２で気密刺入し、ＩＣ半導体成形品を製作する。Example 9 A molded body gq is obtained based on Example 1. This molded body 2
The process will be explained starting from the step of removing the resin film on the lead tip 28 of the opening recessed part No. 7. A resin release agent (product name: GEL DATS-P) is injected through the opening window of the molded body 27 and the lead tip 28 is injected.
Peel off the resin film. Next, the lead tip 28 is gently brushed to ensure that the film is removed, washed, and then dried. Molded object 2 from which this resin film has been removed
The semiconductor element 80 is attached to the tab 29 of 7, and then the lead tip 28 and the semiconductor element 80 are connected with a thin metal wire 81 using a wire bonding machine. Thereafter, the opening window of the molded body 27 is hermetically pierced with a lid 82 made of a transparent resin plate or glass plate material in the same manner as in Example 1, thereby producing an IC semiconductor molded product.
本発明の他の実施例として図８と図４に示す様に角形の
素子挿入用開口窓を図示しているが、丸形でも目的を果
せる。開口窓の形は自由にできる。As another embodiment of the present invention, as shown in FIGS. 8 and 4, a rectangular element insertion opening window is shown, but a round opening window can also serve the purpose. The shape of the opening window can be freely chosen.
上記の本発明の記述は全て半導体素子の電極をワイヤボ
ンディングマシンによって結線する方法を例にとって説
明したが、半田バンプその他アルミワイヤを用いないで
接続する手法に対しても適用可能である。All of the above description of the present invention has been explained by taking as an example a method of connecting electrodes of semiconductor elements using a wire bonding machine, but it is also applicable to methods of connecting without using solder bumps or other aluminum wires.
本発明によれば、タブやリード先端にノくツケージ時の
樹脂皮膜などの／クリが仮に発生しても機械的もしくは
化学的手段で除去するために半導体素子とリードとの結
線が確実にできる。さらに従来のセラミック形やサーデ
ィツプ形に比較して作業り工程数、さらに封止材料価格
の面で経済的で、ま友景産的である。また従来の樹脂封
止型成形方法に比較して半導体素子近傍が気密封止でき
るために半導体素子機能を低下させる恐れ、５Ｅない。According to the present invention, even if creases, such as a resin film during notching, occur on the tips of tabs and leads, they can be removed by mechanical or chemical means, so that the connection between the semiconductor element and the leads can be ensured. . Furthermore, compared to the conventional ceramic type or cerdip type, it is economical in terms of the number of work steps and the cost of the sealing material, making it more cost-effective. Furthermore, compared to the conventional resin-sealing molding method, since the vicinity of the semiconductor element can be hermetically sealed, there is no risk of degrading the function of the semiconductor element.
第１図と第２図は従来の技術を示す図面である。
第８図と第４図とは本発明による実施例を示す図面であ
る。
ｌ・・成形品 ２・・・リード先端 ８・・・リードフ
レーム ５・・半導体素子 ７・・・上型 ８・・・下
型１２・・・絶縁基板 １８・・・半導体素子 １４・
・・リード先端 １６・・・ガラス窓 １９・・・封入
絶縁ガラス２１・・・上型 ２Ｂ・・・下髪 ２９・・
・りタブ ８０・・・半導体素子 ８１・・・金属細線
８２・・・ふた０寛１ 岨
（へ）
（シ）
２ ４、 ．４ ２
溝２国
（α）
（ｂ）
（シ）
豫 ４ 日
（Ｑ）
（ム）
手続補正書（自発）
（円） 昭和５８年１１月２５日
１、事件の表示
昭和５８年特許願第５８−１９７９０７ 号２、発明の
名称
久籟鍔開韮妊や。ｉ鼎ｒ
３、補正をする者
事件との関係 特許出願人
４、補正命令の日イリ（自発）
５、補正の対象
６、補正の内容
（１）、明細書第８頁の１６行の「形でも目的を果せる
。開１１窓の形は自由にできる。」を［形でも目的を果
せ、開Ｉ」窓の形は白１１１にてき、また配置は裏方で
も裏方でもよい。」と訂正する。
（２）、第３図（ａ）、ｌ）を添付図面第３図（、）、
（ｂ）と訂正する。。FIG. 1 and FIG. 2 are drawings showing a conventional technique. FIG. 8 and FIG. 4 are drawings showing an embodiment according to the present invention. l... Molded product 2... Lead tip 8... Lead frame 5... Semiconductor element 7... Upper die 8... Lower die 12... Insulating substrate 18... Semiconductor element 14.
...Lead tip 16...Glass window 19...Enclosed insulating glass 21...Upper mold 2B...Lower hair 29...
・Ritab 80... Semiconductor element 81... Fine metal wire 82... Lid 0 Hiroshi 1 岨 (HE) (SI) 2 4, . 4 2 Mizo 2 country (α) (b) (shi) Yu 4th (Q) (mu) Procedural amendment (voluntary) (yen) November 25, 1988 1, Indication of case 1988 Patent Application No. No. 58-197907 No. 2, name of the invention. 3. Relationship with the case of the person making the amendment Patent applicant 4. Date of amendment order (voluntary) 5. Subject of amendment 6. Contents of the amendment (1), line 16 on page 8 of the specification: The shape can also serve a purpose. The shape of the opening 11 window can be freely chosen." The shape of the window can also be used to achieve a purpose. ” he corrected. (2), Figure 3 (a), l) attached to Figure 3 (, ),
Correct (b). .
Claims (1)
製収納容器と、この容器内部に埋設されて半導体素子と
結線される複数の内部リードと、半導体素子を装着する
タブとから構成された気密封止型半導体に関して、収納
容器の挿入用開口部底面のリード先端部およびタブ部の
上面の樹脂皮膜を機械的もしくは化学的に除去した後に
半導体素子をタブ部に装着し、リード先端部と結線し、
次に容器開口部をふたで密封することを特徴とする気密
封止型半導体装置。 （２） 半導体素子を内部に収納する気密封止型の樹脂
製収納容器と、この容器内部に埋設されて半導体素子と
結線される複数の内部リードと、タブとから構成された
気密封止型半導体の製造方法において、収納容器の挿入
用開口部底面のリード先端部およびタブ部の上面の樹脂
皮膜を機械的手段もしくは化学的方法で除去後に半導体
素子を組み込み装着し、リード先端部と結線し、次に開
口部[Scope of Claims] +11 A hermetically sealed storage container made of resin that stores a semiconductor device therein, a plurality of internal leads buried inside the container and connected to the semiconductor device, and a semiconductor device mounted therein. Regarding hermetically sealed semiconductors consisting of a tab, the semiconductor element is attached to the tab after mechanically or chemically removing the lead tips on the bottom of the insertion opening of the storage container and the resin film on the top of the tab. and connect it to the lead tip,
Next, the hermetically sealed semiconductor device is characterized in that the opening of the container is sealed with a lid. (2) A hermetically sealed resin storage container that stores a semiconductor element inside, a plurality of internal leads buried inside the container and connected to the semiconductor element, and a tab. In a method for manufacturing semiconductors, the resin film on the top of the lead tips and tabs on the bottom of the insertion opening of a storage container is removed by mechanical or chemical methods, and then the semiconductor element is installed and connected to the lead tips. , then the opening
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP19790783A JPS60115248A (en) | 1983-10-21 | 1983-10-21 | Hermetic sealed semiconductor device and preparation thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP19790783A JPS60115248A (en) | 1983-10-21 | 1983-10-21 | Hermetic sealed semiconductor device and preparation thereof |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS60115248A true JPS60115248A (en) | 1985-06-21 |
Family
ID=16382258
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP19790783A Pending JPS60115248A (en) | 1983-10-21 | 1983-10-21 | Hermetic sealed semiconductor device and preparation thereof |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS60115248A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS63290472A (en) * | 1987-05-22 | 1988-11-28 | Olympus Optical Co Ltd | Solid-state image pickup device |
| US5990003A (en) * | 1996-04-24 | 1999-11-23 | Nec Corporation | Method of fabricating a semiconductor device |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5098275A (en) * | 1973-12-26 | 1975-08-05 |
-
1983
- 1983-10-21 JP JP19790783A patent/JPS60115248A/en active Pending
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5098275A (en) * | 1973-12-26 | 1975-08-05 |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS63290472A (en) * | 1987-05-22 | 1988-11-28 | Olympus Optical Co Ltd | Solid-state image pickup device |
| US5990003A (en) * | 1996-04-24 | 1999-11-23 | Nec Corporation | Method of fabricating a semiconductor device |
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