JPS6011479B2 - Manufacturing method of ceramic multilayer circuit board - Google Patents
Manufacturing method of ceramic multilayer circuit boardInfo
- Publication number
- JPS6011479B2 JPS6011479B2 JP11222377A JP11222377A JPS6011479B2 JP S6011479 B2 JPS6011479 B2 JP S6011479B2 JP 11222377 A JP11222377 A JP 11222377A JP 11222377 A JP11222377 A JP 11222377A JP S6011479 B2 JPS6011479 B2 JP S6011479B2
- Authority
- JP
- Japan
- Prior art keywords
- multilayer circuit
- circuit board
- ceramic
- manufacturing
- conductor
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
Landscapes
- Manufacturing Of Printed Wiring (AREA)
- Non-Insulated Conductors (AREA)
- Manufacturing Of Electric Cables (AREA)
Description
【発明の詳細な説明】
本発明は通常のセラミック焼成温度で焼結して得られる
低電気抵抗の金属導体材料及び該導体材料を用いたセラ
ミック多層回路基板の製造方法に関する。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a low electrical resistance metal conductor material obtained by sintering at a normal ceramic firing temperature, and a method for manufacturing a ceramic multilayer circuit board using the conductor material.
従来、電子回路に用いられるセラミック多層回路基板の
作成方法には、焼成されたセラミック基板上に導体ペー
ストと絶縁体ペーストとを交互に印刷・焼成し、これを
繰返して多層化を行う厚膜法と「セラミック生シート上
に印刷または積層により多層回路基板の未焼成体を形成
し、これらの多層回路基板未焼成体の導体とセラミック
を同時に焼成する印刷法および積層法とがある。Conventionally, the method for making ceramic multilayer circuit boards used in electronic circuits is the thick film method, in which conductor paste and insulator paste are alternately printed and fired on a fired ceramic substrate, and this process is repeated to create multiple layers. There is a printing method and a lamination method in which a green body of a multilayer circuit board is formed by printing or lamination on a raw ceramic sheet, and the conductor and ceramic of the green body of the multilayer circuit board are simultaneously fired.
この印刷法と積層法は導体とセラミックを同時に焼成し
てセラミック多層回路基板を得る方式であるため焼成は
1度だけであり厚膜法に比し作業工程が少ない。またこ
れらの方式で得られたセラミック多層回路基板はモノリ
シック構造をとるため機械的及び熱的強度が大きく信頼
性が高い。しかし、これらの方式においてはセラミック
と導体の焼成は通常1400〜1600ooの高温で行
うため、これらの方式に用いられる導体材料は少なくと
もこの焼成温度より高い融点をもち、また焼成中に蒸発
、飛散などの起らない材料でなければならない。このた
め一般にはW、Moなどの高融点金属が用いられている
。ところがこれらの高融点金属の融点は2500oo以
上であり、前記の焼成温度では充分な焼縞が行なわれな
いため導体は空隙の多い焼結体なり電気抵抗が高くなる
傾向にある。本発明はこの欠点を改良するために案出さ
れたものである。このため本発明においては、金属導体
材料としてMo又はW等の高融点金属粉末に1の重量パ
ーセント以下のTi及びZrの粉末を添加して加熱焼成
することを特徴とし、更に導体とセラミックとを同時に
焼成してセラミック多層回路基板を製造する過程におい
て、前記導体を形成するMo又はW等の高融点金属粉末
に10重量パーセント以下のTi及びZr粉末を添加す
ることを特徴とするものである。以下、添付図面に基づ
いて本発明の実施例につき詳細に説明する。Since the printing method and the lamination method obtain a ceramic multilayer circuit board by simultaneously firing the conductor and the ceramic, firing is performed only once, and the number of work steps is reduced compared to the thick film method. Furthermore, since the ceramic multilayer circuit boards obtained by these methods have a monolithic structure, they have high mechanical and thermal strength and are highly reliable. However, in these methods, the ceramic and conductor are usually fired at a high temperature of 1,400 to 1,600 oo, so the conductor materials used in these methods have a melting point at least higher than this firing temperature and are susceptible to evaporation, scattering, etc. during firing. The material must not cause For this reason, high melting point metals such as W and Mo are generally used. However, the melting point of these high-melting point metals is 2,500 oo or higher, and sufficient burning stripes cannot be formed at the above-mentioned firing temperature, so that the conductor tends to become a sintered body with many voids and high electrical resistance. The present invention has been devised to improve this drawback. Therefore, the present invention is characterized in that Ti and Zr powders of 1% by weight or less are added to a high-melting point metal powder such as Mo or W as a metal conductor material and then heated and fired. In the process of manufacturing a ceramic multilayer circuit board by simultaneous firing, Ti and Zr powders of 10 weight percent or less are added to the high melting point metal powder such as Mo or W forming the conductor. Hereinafter, embodiments of the present invention will be described in detail based on the accompanying drawings.
第1図は多層回路基板を得る製造工程の第1工程である
。この工程はセラミックの生シートーの上に導体ペース
トにより導体回路2を印刷するものである。この導体ペ
ーストの組成を第1表に示す。これはMo又はWを含む
ペーストに本発明の要点であるTi及びZrを焼結助剤
として添加したものである。第1表 MoおよびWペー
ストZ溢血戊
次に第2図に示すようにセラミックペーストを印刷して
絶縁層3を形成する。FIG. 1 shows the first step of the manufacturing process for obtaining a multilayer circuit board. In this process, a conductor circuit 2 is printed on a green ceramic sheet using a conductor paste. The composition of this conductive paste is shown in Table 1. This is a paste containing Mo or W to which Ti and Zr, which are the main points of the present invention, are added as sintering aids. Table 1 Mo and W Paste Z Exfusion Next, as shown in FIG. 2, a ceramic paste is printed to form an insulating layer 3.
この上に更に導体ペーストとセラミックペーストを交互
に印刷して、第3図の如く層を積み重ねる。これを必要
層.数重ねて形成されたセラミック多層回路基板の未焼
成体を加熱炉に入れて湿潤水素雰囲気中で約1600午
0に加熱焼成し多層回路基板を得るのである。このよう
にして得られた多層回路基板内の導体回路の電気抵抗を
四端子法を用いて測定した結果を第2表に示した。On top of this, conductive paste and ceramic paste are alternately printed and the layers are stacked as shown in FIG. This is the necessary layer. The unfired body of the ceramic multilayer circuit board formed by stacking several layers is placed in a heating furnace and fired at about 1600 o'clock in a humid hydrogen atmosphere to obtain a multilayer circuit board. The electrical resistance of the conductor circuit in the multilayer circuit board thus obtained was measured using the four-probe method, and the results are shown in Table 2.
第2表 Ti及びZrの添加量と電気抵抗これはTi「
Zr等の焼結助剤の添加量と電気抵抗の関係を示したも
のであるが、これよりTi、Zrの添加量が少ないとそ
の効果が顕著でなく、また添加量が多過ぎるとMo、W
などの高融点金属と合金をつくるため電気抵抗は逆に高
くなることがわかる。Table 2: Addition amount of Ti and Zr and electrical resistance.
This figure shows the relationship between the amount of added sintering aids such as Zr and electrical resistance.If the amount of Ti and Zr added is small, the effect is not noticeable, and if the amount added is too large, Mo, W
It can be seen that the electrical resistance increases because it is alloyed with high melting point metals such as.
このため適量の焼結勤剤の添加が必要である。この焼結
助剤の添加量は使用する高融点金属および暁綾助剤の種
類、粉末粒子の形状等により異なるが高融点金属に対し
1の重量パーセント以下が適当である。以上説明したよ
うにMo、W等の高融点金属粉末に焼結助剤としてTi
、Zr等の粉末を添加することにより通常のセラミック
嬢結温度において、Mo「Wなどの高融点金属の焼結が
活性化し、繊密で空隙の少ない暁結体が得られる。For this reason, it is necessary to add an appropriate amount of a sintering agent. The amount of this sintering aid added varies depending on the type of high melting point metal used, the type of sintering aid, the shape of the powder particles, etc., but it is suitably 1 weight percent or less based on the high melting point metal. As explained above, Ti is added to high melting point metal powder such as Mo and W as a sintering aid.
By adding powders such as , Zr, etc., the sintering of high melting point metals such as Mo'W is activated at normal ceramic sintering temperatures, and a dense compact with few voids can be obtained.
そのためこの焼結体の電気抵抗は通常のMo、Wなどに
比較して2ノ3〜1/2の低抵抗とすることが可能とな
る。更にこれらの低い電気抵抗をもった導体をセラミッ
ク多層回路基板に適用することにより導体回路の線幅を
狭くすることが可能になり、そのため配線密度を向上せ
しめることが可能になる。Therefore, the electrical resistance of this sintered body can be made 2/3 to 1/2 lower than that of ordinary Mo, W, etc. Furthermore, by applying these conductors with low electrical resistance to ceramic multilayer circuit boards, it becomes possible to narrow the line width of the conductor circuit, thereby making it possible to improve the wiring density.
第1図乃至第3図は本発明にかかるセラミック多層回路
基板の製造方法による各製造工程の多層回路基板の断面
図である。
1……セラミック生シート、2…・・・導体回路、3・
・・・・・絶縁層。
第1図
第2図
第3図1 to 3 are cross-sectional views of a multilayer circuit board in each manufacturing process according to the method for manufacturing a ceramic multilayer circuit board according to the present invention. 1...Ceramic raw sheet, 2...Conductor circuit, 3.
...Insulating layer. Figure 1 Figure 2 Figure 3
Claims (1)
回路基板を製造する過程において、前記導体はMo又は
W等の高融点金属粉末に10重量パーセント以下のTi
及びZr粉末が添加されたものであることを特徴とする
多層回路基板の製造方法。1. In the process of manufacturing a ceramic multilayer circuit board by simultaneously firing a conductor and ceramic, the conductor is formed by adding 10% by weight or less of Ti to a high melting point metal powder such as Mo or W.
and a method for manufacturing a multilayer circuit board, characterized in that Zr powder is added thereto.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP11222377A JPS6011479B2 (en) | 1977-09-20 | 1977-09-20 | Manufacturing method of ceramic multilayer circuit board |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP11222377A JPS6011479B2 (en) | 1977-09-20 | 1977-09-20 | Manufacturing method of ceramic multilayer circuit board |
Publications (2)
Publication Number | Publication Date |
---|---|
JPS5446398A JPS5446398A (en) | 1979-04-12 |
JPS6011479B2 true JPS6011479B2 (en) | 1985-03-26 |
Family
ID=14581324
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP11222377A Expired JPS6011479B2 (en) | 1977-09-20 | 1977-09-20 | Manufacturing method of ceramic multilayer circuit board |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS6011479B2 (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
WO1995016797A1 (en) * | 1993-12-14 | 1995-06-22 | Kabushiki Kaisha Toshiba | Molybdenum-tungsten material for wiring, molybdenum-tungsten target for wiring, process for producing the same, and molybdenum-tungsten wiring thin film |
Families Citing this family (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5504993A (en) * | 1994-08-30 | 1996-04-09 | Storage Technology Corporation | Method of fabricating a printed circuit board power core using powdered ceramic materials in organic binders |
-
1977
- 1977-09-20 JP JP11222377A patent/JPS6011479B2/en not_active Expired
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
WO1995016797A1 (en) * | 1993-12-14 | 1995-06-22 | Kabushiki Kaisha Toshiba | Molybdenum-tungsten material for wiring, molybdenum-tungsten target for wiring, process for producing the same, and molybdenum-tungsten wiring thin film |
Also Published As
Publication number | Publication date |
---|---|
JPS5446398A (en) | 1979-04-12 |
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