JPS644218B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a multiprocessor type real-time signal processing device.

With the recent advances in information processing technology, measurement control technology, etc., there is a demand in various fields for high-speed signal processing in real time. This signal processing is the execution of a certain set of operations on input signals. Conventionally, large-scale computers have been used to perform these complex operations.
However, in order to increase the number of input signals and perform high-speed arithmetic processing, the input signals must be processed in parallel in time, which requires multiple large-scale computers, resulting in extremely high costs. Become. Furthermore, the control becomes complicated, and there may be cases where the time allotted to such a large-scale computer is insufficient.

On the other hand, with the development of semiconductor technology, particularly LSI technology, integrated circuit components called microprocessors have been developed that can perform a certain amount of signal processing at high speed with one or several chips.
For details on microprocessors, please refer to ``Microcomputers and their Applications'' published by the Institute of Electronics and Communication Engineers on May 10, 1973, supervised by Hideo Aiso. This microprocessor has a smaller computing power than a large computer, but it can be programmed specifically for each operation, so it can execute operations at very high speed. It has been considered that a plurality of such processors can be used to perform signal processing similar to that performed in conventional large-scale computers, and this is generally referred to as a multiprocessor system. In signal processing using this multiprocessor system, certain types of complex operations that were traditionally performed by large computers are divided into small basic operations.For example, a single processor can perform logarithmic,
Processing such as square roots, exponential function calculations, and even FFT calculations will be performed as a unit and the calculations will be executed exclusively. When performing a certain type of computation using multiple processors, how should these processors be connected in order to be suitable for high-speed real-time signal processing and to have flexibility and expandability such as changing the computation? The question is how.

Typical multiprocessor configuration methods that have been used in the past are shown in FIGS. 1 and 2. For details on how to configure a multiprocessor, see, for example, the Journal of the Institute of Electronics and Communication Engineers, February 1977 issue, p.125~
Please refer to page 135. FIG. 1 shows a configuration generally called a multiplex bus system. In FIG. 1, reference numeral 1 represents a processor, reference numeral 2 represents a bus controller, reference numeral 3 represents an input/output bus, and reference numeral 4 represents a common bus. The configuration is such that a plurality of processors P and a bus controller C are connected by a plurality of buses 4. FIG. 2 shows a configuration generally called a circular bus system. In Figure 2, 1 is a processor, 2 is a bus controller, 3 is an input/output bus,
5 represents a circular bus. multiple processors P,
The bus controller C is connected to a regular one-ring bus 5.
It is a composition connected by.

However, since all of these configurations are aimed at flexible general-purpose computers, they are unsuitable for realizing high-speed real-time signal processing. That is, in each conventional configuration, input and output data transmission is performed using the same bus, so that each processor requires independent input and output time. Furthermore, between processors on the same bus, there are cases where one processor's data input or output time is interrupted by another processor's input or output action. As a result, bus usage efficiency is poor and data transmission time becomes long, and in real-time signal processing, calculation time is shortened accordingly. First, in the circular bus method shown in Figure 2, time-parallel processing is required, and when there is a large number of data to be processed, there is competition in bus usage because there is only one bus. This becomes a problem and requires a lot of time to transmit data. In the multiple bus system shown in Figure 1, bus contention is reduced, but the processor and bus controller do not have a mechanism for selecting a bus or for selecting one request from multiple buses. Since this is necessary, controlling the transfer of data between buses is extremely complicated and time consuming. Moreover, increasing the number of processors or changing the calculation method involves hardware difficulties, and the control of data transmission and reception becomes more complicated, making expandability particularly difficult.

The purpose of the present invention is to realize high-speed, large-scale real-time signal processing using a multiprocessor system, and to easily cope with the addition of processors and changes in the destination of signals between processors by expanding and changing calculations. It is an object of the present invention to provide a multiprocessor type real-time signal processing device having a connection configuration between processors that is easy to control.

The device of the present invention has a function of arranging a plurality of processor columns each consisting of a plurality of independent processors in the row direction, and supplying the output of a processor in the processor column as an input to an arbitrary processor in the processor column of the next row. Each processor row is connected by a data path having a plurality of processors, and the processor rows each having a plurality of processors are sequentially repeated so as to alternate with the data path. Data is input to the first processor column, signal processing is performed in each processor column sequentially, and processed data is obtained from the final processor column.

In general, real-time signal processing can be characterized as a single, complex operation, which consists of several stages of basic operations connected over time. That is, instead of many basic operations being performed in parallel, the result of one operation is used to perform the next operation, and the result of that operation is used to perform the next operation. For such calculations, high-speed calculations can be expected if a processor is determined for each basic calculation, and several processors are connected continuously in one direction to process the calculations. Further, among the operations that are continuously performed, there are operations that can be processed in parallel in time, and operations that must be processed using several processors in parallel depending on the processing capacity of the processor. Furthermore, in order to realize high-speed signal processing, it is of course necessary to shorten the calculation time within the processor, but an important issue is how to transmit data between processors in a short time. Therefore, it is necessary to have a configuration suitable for real-time signal processing, that is, a configuration that is easy to control so that the data flow between processors is unidirectional, and is also suitable for parallel processing. Moreover, it is necessary to consider a configuration that can shorten data transmission between processors and simplify control.

Next, this invention will be explained using the drawings.
FIG. 3 shows a block diagram of an embodiment of the present invention.
In FIG. 3, 6 is a processor input bus;
7 is a processor output bus, 8 is an input terminal, 9 is an output terminal, 10 is a first stage processor, 11 is a first stage data path, 12 is a second stage processor,
13 represents a second stage data path, and 14 represents a final stage processor. Dashed lines represent repetitions of the same configuration, and are the same in the following figures. Data path DP1
1 and 13 realize data transmission and reception between each stage of the processor according to arithmetic processing. The configuration may be of a combination type that allows output data from a previous processor to be input to any next processor, and various types can be considered, as will be described later. The data flow in the present invention is sequential, irreversible, and unidirectional from the processor to the data path in accordance with the characteristics of real-time signal processing. In FIG. 3, data input from an input terminal 8 is sent from left to right in terms of time, and the result of arithmetic processing is output to an output terminal 9. Therefore, in each of the processors shown in FIG. 3, numeral 6 serves as an input bus through which data from the previous stage processor is input, and data after arithmetic processing is outputted from the output bus 7 to the next stage processor. Hereinafter, such a multiprocessor type configuration will be referred to as a pipeline configuration.

The operation of the multiprocessor system using the pipeline configuration will be explained in detail below. The computing power that can be executed by a single processor is limited depending on the amount of data that it can handle and the capacity of its storage elements. Therefore, the number of stages in the pipeline configuration and the number of processors that perform parallel processing at each stage are determined by the size, method, and speed of the operation to be processed. Therefore, according to the flow of data in real-time signal processing, the processors are arranged in the order of operations, and data is transmitted between the rows of processors at each stage. For data transmission between each stage, it is only necessary to specify which processor in the next processor row is to be sent from each processor in the previous stage, so all processors are connected to one bus and the data destination can be specified to all processors. Control is easier than in the case where In FIG. 3, data input from the input terminal 8 is processed in parallel by a row of processors 10 in the first stage. Each processor 12 in the second stage processor row is supplied with necessary results from among the outputs of the preceding stage processors 10 by the first stage data path 11. The data path 11 is designed to be able to input the output data from each processor 10 in the previous stage to any processor 12 in the next stage according to the calculation, so the output from one processor 10 in the previous stage is It is possible to supply a plurality of processors 12 in a previous stage, or to supply output from a plurality of processors 10 in a previous stage to one processor 12 in a next stage. Also, depending on the type and method of calculation, some results may be obtained at intermediate stages. As described above, even very complicated calculations can be realized by increasing the number of stages and the number of processors in each stage according to the calculation, and expansion is easy. Furthermore, changes in the calculation method and order of calculations can be easily handled by simply replacing the processor.

Next, the calculation processing time of the multiprocessor method using this pipeline configuration will be described. In the conventional configuration, the same bus is used for input/output data, and furthermore, a plurality of processors use the same bus and are controlled by a bus controller. Therefore, each processor requires its own input/output time, and there is contention for bus usage between processors, so the data input/output time becomes long, which is a time consuming problem from the perspective of high-speed real-time signal processing. The waste was hot. However, in the pipeline configuration, the data input side and the data output side are separated. Therefore, data input and output can be executed independently to the extent permitted by arithmetic processing capacity, so each processor itself does not have to wait for data input/output. Furthermore, since each data path is completely separated, each data path can transmit data independently, excluding contention between processors connected to that data path, making it possible to realize an efficient data transmission system.

Here, a specific example of the data path used in FIG. 3 will be described below. Regarding the data path, any configuration may be used as long as it has the above-mentioned functions. The multiple bus method explained in the conventional example,
In addition to the circular bus method, there is also a single bus method in which multiple processors are connected by a single bus, a multiport method in which each processor is connected through a dedicated connection path, and a cross bus switch in which all processors are connected by a switch. Any connection method such as a matrix switch method for coupling processors may be used. However, a data path configuration that is considered to be easy to implement from various viewpoints such as simplicity of configuration, large circuit scale, ease of control, flexibility, and expandability will be described next.

One of them is the configuration shown in FIG. The figure illustrates one data path between processor rows as an example. In Fig. 4, 6 is an input bus;
7 is an output bus, 15 is a previous stage processor connected by a data path, 16 is a next stage processor, 17
is a common bus. The connection method is such that the output bus 7 of the processor 15 at the previous stage and the input bus 6 of the processor 16 at the next stage are sequentially connected by a common bus 17. There is a data transmission method that uses a packet switching method as a data transmission method that is compatible with this configuration.
The packet switching system is explained in detail in, for example, pages 381 to 385 of the April 1978 issue of the Journal of the Institute of Electronics and Communication Engineers, so the explanation will be omitted here. In data transmission using the packet switching method, processor 1 at the front stage
In step 5, the output data is sent with an address to the next processor 16, and the next processor 16 reads this address and takes in the data addressed to its own processor.

FIG. 5 includes the same configuration as FIG. 4, but is represented by a unidirectional transmission path without using a bidirectional bus. In FIG. 5, 15 is the previous stage processor connected by a data path, 16 is the next stage processor, 18 is a transmission line connecting the input side of the processor array, 19 is a transmission line connecting the output side of the processor array, and 20 is the previous stage processor. This is a transmission line that connects the output side of one processor to the input side of the next processor. The configuration is such that output data from each processor 15 at the same stage is sequentially sent to each processor 16 at the next stage. At this time, each of the processors 15 and 16 may be configured to hold the passing signal for a certain period of time as necessary. Whether to use the data path shown in FIG. 4 or the data path shown in FIG. 5 for data transmission using the packet switching method may be determined based on reliability, fan-out limitations, complexity of data output control, etc. Data transmission using this packet switching method is flexible in changing calculations, and the data transmission time can be shortened, but control is somewhat complicated.

Another implementation example of the data path is according to the configuration shown in FIG. In FIG. 6, 6 is an input bus, 7 is an output bus, 15 is a front and rear processor connected by a data path, 16 is a next-stage processor, 21 is a common bus on the output side, 22 is a common bus on the input side, 23 represents a switching circuit. The input buses 6 of each of the preceding processors 16 are connected by an input common bus 22, respectively. The switching circuit 23 collects output data from each of the front and rear processors 15,
It has a function of once storing the data in a memory and rearranging it in the order in which each processor in the next stage processor row receives it, and then sending it out as an input signal to each processor 16 in the next stage. The output side common bus 21 at the previous stage and the input side common bus 22 at the next stage are coupled via this switching circuit 23. Although this configuration is simple, the drawback is that it takes a long time to input and output the switching circuit.

Specific examples of the configuration of the data path and the data transmission method at that time have been described above with reference to FIGS. 4, 5, and 6. Although each has advantages and disadvantages, this configuration is superior to the conventional multiprocessor configurations shown in Figures 1 and 2 in terms of data transmission speed, flexibility, and circuit size. .

As explained above, according to the present invention, high-speed real-time signal processing is possible, and scalability is improved even when adding processors due to changes in calculations, etc., and when changing the destination of signals between processors. It is possible to realize signal processing that is highly flexible and easy to control.

[Brief explanation of the drawing]

1 and 2 are block diagrams showing the configuration of a conventional multiprocessor system, FIG. 3 is a block diagram showing an embodiment of the present invention, and FIG.
FIGS. 5 and 6 are block diagrams showing examples of data paths used in the present invention. In the figure, 1... Processor, 2... Bus controller, 3... Input/output bus, 4... Common bus, 5... Circular bus, 6... Processor input bus, 7... Processor output bus, 8 ...Input terminal, 9...Output terminal, 10...1st stage processor, 11...1st stage data path, 12...2nd stage processor
Stage processor, 13...Second stage data path,
14...Final stage processor, 15...Previous stage processor connected by data path, 16...Next stage processor, 17...Common bus, 18...Transmission line connecting input sides of processor rows, 19...Processor Transmission line connecting the output side of the column, 20...Transmission line connecting the output side of the previous stage processor and the input side of the next stage processor, 21...Output side common bus, 22...Input side common bus, 23... exchange circuit.

Claims (1)

[Scope of Claims] 1. In a multiprocessor type real-time signal processing device that executes real-time signal processing using a plurality of microprocessors, a plurality of microprocessor rows each consisting of a plurality of independent microprocessors are used. The microprocessors are arranged in rows, and each microprocessor is connected to the microprocessor by a data path that has the function of supplying the output of each microprocessor in the microprocessor row to the input of any microprocessor in the microprocessor row in the next row. The microprocessor rows consisting of a plurality of microprocessors and the data path are sequentially repeated so that they are alternately connected, and data is input to the first microprocessor row and then sequentially. A multiprocessor type real-time signal processing device characterized in that each microprocessor row performs signal processing and processed data is obtained from the final stage microprocessor row. 2. The data path includes an output common bus for connecting the outputs of each of the plurality of microprocessors in the microprocessor row, and each of the plurality of microprocessors in the next stage microprocessor row. It has a common input bus for connecting the inputs of each processor, and a memory for storing the output data of each microprocessor in the previous stage microprocessor row. Claim 1, further comprising a switching circuit disposed between the output common bus and the input common bus so as to send out the data as input data in the microprocessor array at the next stage. A multiprocessor-type real-time signal processing device as described in . 3. The data path is a common bus that connects the output of each of the plurality of microprocessors in the microprocessor bank to the input of each of the plurality of microprocessors in the next stage microprocessor bank. A multiprocessor type real-time signal processing device according to claim 1, wherein the multiprocessor type real-time signal processing device is configured.