JPS643223U

JPS643223U -

Info

Publication number: JPS643223U
Application number: JP9415787U
Authority: JP
Priority date: 1987-06-19
Filing date: 1987-06-19
Publication date: 1989-01-10

Description

[Brief explanation of drawings]

第１図はこの考案の実施例を示す構成図、第２
図はこの発明の他の実施例を示す構成図、第３図
はＤＡＣのアナログ信号が、その変化量により安
定する迄の時間が異なることを示す図、第４図は
ＤＡＣのアナログ出力に生ずるグリツチの例を示
す波形図、第５図は従来のＤＡＣの出力整定時間
制御装置の構成例を示す図、第６図は他の従来例
を示す構成図である。１１：デジタルデータ入力端子、１２：データ
変化量算出回路、１３：一時記憶メモリ、１４：
整定時間テーブル、１５：出力端、１６：安定時
間テーブル、１７：グリツチ最大時間メモリ、１
８：整定時間データ出力端、２１：デジタルデー
タ入力端、２２：一時記憶メモリ、２３：グリツ
チパターン検出回路、２４：データ変化量算出回
路、２５：グリツチ時間テーブル、２６：安定時
間テーブル、２７：整定時間出力回路、２８：デ
ータ出力端。 Figure 1 is a configuration diagram showing an embodiment of this invention, Figure 2
The figure is a block diagram showing another embodiment of the present invention, Figure 3 is a diagram showing that the time required for the DAC analog signal to stabilize depending on the amount of change, and Figure 4 is a diagram showing the time required for the DAC analog signal to stabilize depending on the amount of change. FIG. 5 is a waveform diagram showing an example of a glitch, FIG. 5 is a diagram showing a configuration example of a conventional DAC output settling time control device, and FIG. 6 is a configuration diagram showing another conventional example. 11: Digital data input terminal, 12: Data change amount calculation circuit, 13: Temporary storage memory, 14:
Settling time table, 15: Output end, 16: Stabilization time table, 17: Glitch maximum time memory, 1
8: Settling time data output terminal, 21: Digital data input terminal, 22: Temporary memory, 23: Glitch pattern detection circuit, 24: Data change amount calculation circuit, 25: Glitch time table, 26: Stability time table, 27 : Settling time output circuit, 28: Data output terminal.

Claims

[Claim for Utility Model Registration] In a DA converter that inputs digital data to a DA converter and outputs an analog signal from the DA converter after a settling time, the input digital data and the data input immediately before A glitch pattern detection circuit that detects data that causes a glitch from a data pattern with digital data, and a data change amount calculation circuit that calculates the amount of change between the input digital data and the digital data that was input immediately before. , a glitch time table that generates a glitch time according to the data detected by the glitch pattern detection circuit; and a stability time table that generates a stabilization time according to the data change amount calculated by the data change amount calculation circuit. , from the stability time from the constant time table and the glitch time from the glitch time table,
An optimal control device for a DAC settling time, comprising: a settling time output circuit that determines the time from inputting a digital signal to outputting the analog signal.