JPS6419587A - Semiconductor memory device - Google Patents
Semiconductor memory deviceInfo
- Publication number
- JPS6419587A JPS6419587A JP62176348A JP17634887A JPS6419587A JP S6419587 A JPS6419587 A JP S6419587A JP 62176348 A JP62176348 A JP 62176348A JP 17634887 A JP17634887 A JP 17634887A JP S6419587 A JPS6419587 A JP S6419587A
- Authority
- JP
- Japan
- Prior art keywords
- bus line
- write
- turned
- rwb
- read
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Landscapes
- Dram (AREA)
Abstract
PURPOSE:To realize a read or a write operation by one data bus line, by constituting a device so that the switching of the readout or the write of the data bus line can be performed by a transfer gate. CONSTITUTION:A read bus line RWB is commonly used for a read bus line and a write bus line. Firstly, since a write enable internal signal, the inverse of WE' is set at a high level and a WE' at a low level at the time of readout, a MOSFETQ1 is turned on, and a MOSFETQ2 is turned off. In other words, since a DIN buffer circuit 8 is cut off electrically, the bus line RWB functions as the lead bus line. Next, at the time of write, the signal, the inverse of WE' is set at the low level and the WE' at the high level, therefore, the FETQ1 is turned off and the Q3 turned on. Namely, since a sense amplifier circuit 5 is cut off electrically, the bus line RWB functions as the write bus line.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP62176348A JPH07122990B2 (en) | 1987-07-14 | 1987-07-14 | Semiconductor memory device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP62176348A JPH07122990B2 (en) | 1987-07-14 | 1987-07-14 | Semiconductor memory device |
Publications (2)
Publication Number | Publication Date |
---|---|
JPS6419587A true JPS6419587A (en) | 1989-01-23 |
JPH07122990B2 JPH07122990B2 (en) | 1995-12-25 |
Family
ID=16012028
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP62176348A Expired - Lifetime JPH07122990B2 (en) | 1987-07-14 | 1987-07-14 | Semiconductor memory device |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPH07122990B2 (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH04228179A (en) * | 1990-05-18 | 1992-08-18 | Nec Corp | Semiconductor memory device |
Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS54114132A (en) * | 1978-02-27 | 1979-09-06 | Cho Lsi Gijutsu Kenkyu Kumiai | Dynamic mis memory |
JPS57167186A (en) * | 1981-04-08 | 1982-10-14 | Nec Corp | Memory circuit |
JPS60197997A (en) * | 1984-03-21 | 1985-10-07 | Hitachi Ltd | Semiconductor storage device |
JPS62109292A (en) * | 1985-11-07 | 1987-05-20 | Nec Corp | Dynamic random access memory |
-
1987
- 1987-07-14 JP JP62176348A patent/JPH07122990B2/en not_active Expired - Lifetime
Patent Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS54114132A (en) * | 1978-02-27 | 1979-09-06 | Cho Lsi Gijutsu Kenkyu Kumiai | Dynamic mis memory |
JPS57167186A (en) * | 1981-04-08 | 1982-10-14 | Nec Corp | Memory circuit |
JPS60197997A (en) * | 1984-03-21 | 1985-10-07 | Hitachi Ltd | Semiconductor storage device |
JPS62109292A (en) * | 1985-11-07 | 1987-05-20 | Nec Corp | Dynamic random access memory |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH04228179A (en) * | 1990-05-18 | 1992-08-18 | Nec Corp | Semiconductor memory device |
Also Published As
Publication number | Publication date |
---|---|
JPH07122990B2 (en) | 1995-12-25 |
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