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JPS53110337A - Data write method for non-volatile memory array - Google Patents

Data write method for non-volatile memory array

Info

Publication number
JPS53110337A
JPS53110337A JP2577877A JP2577877A JPS53110337A JP S53110337 A JPS53110337 A JP S53110337A JP 2577877 A JP2577877 A JP 2577877A JP 2577877 A JP2577877 A JP 2577877A JP S53110337 A JPS53110337 A JP S53110337A
Authority
JP
Japan
Prior art keywords
volatile memory
memory array
data write
write method
memory cell
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP2577877A
Other languages
Japanese (ja)
Other versions
JPS578551B2 (en
Inventor
Minoru Hamada
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sanyo Electric Co Ltd
Original Assignee
Sanyo Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sanyo Electric Co Ltd filed Critical Sanyo Electric Co Ltd
Priority to JP2577877A priority Critical patent/JPS53110337A/en
Publication of JPS53110337A publication Critical patent/JPS53110337A/en
Publication of JPS578551B2 publication Critical patent/JPS578551B2/ja
Granted legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/04—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
    • G11C16/0408—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells containing floating gate transistors
    • G11C16/0433—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells containing floating gate transistors comprising cells containing a single floating gate transistor and one or more separate select transistors

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Non-Volatile Memory (AREA)
  • Read Only Memory (AREA)

Abstract

PURPOSE:To prevent the erroneous write to a non-selected memory cell by discharging the electric charge stored in the non-selected memory cell due to the leakage current each time the write to a selected memory cell.
JP2577877A 1977-03-08 1977-03-08 Data write method for non-volatile memory array Granted JPS53110337A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2577877A JPS53110337A (en) 1977-03-08 1977-03-08 Data write method for non-volatile memory array

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2577877A JPS53110337A (en) 1977-03-08 1977-03-08 Data write method for non-volatile memory array

Publications (2)

Publication Number Publication Date
JPS53110337A true JPS53110337A (en) 1978-09-27
JPS578551B2 JPS578551B2 (en) 1982-02-17

Family

ID=12175290

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2577877A Granted JPS53110337A (en) 1977-03-08 1977-03-08 Data write method for non-volatile memory array

Country Status (1)

Country Link
JP (1) JPS53110337A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9030877B2 (en) 2007-08-30 2015-05-12 Infineon Technologies Ag Memory cell arrangement, method for controlling a memory cell, memory array and electronic device

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9030877B2 (en) 2007-08-30 2015-05-12 Infineon Technologies Ag Memory cell arrangement, method for controlling a memory cell, memory array and electronic device

Also Published As

Publication number Publication date
JPS578551B2 (en) 1982-02-17

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